/* libgcc routines for R8C/M16C/M32C
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/* libgcc routines for R8C/M16C/M32C
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Copyright (C) 2005, 2009
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Copyright (C) 2005, 2009
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Contributed by Red Hat.
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Contributed by Red Hat.
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This file is part of GCC.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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. */
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. */
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#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
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#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
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#define A16
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#define A16
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#define A(n,w) n
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#define A(n,w) n
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#define W w
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#define W w
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#else
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#else
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#define A24
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#define A24
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#define A(n,w) w
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#define A(n,w) w
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#define W l
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#define W l
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#endif
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#endif
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#ifdef L__m32c_memregs
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#ifdef L__m32c_memregs
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/* Warning: these memory locations are used as a register bank. They
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/* Warning: these memory locations are used as a register bank. They
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*must* end up consecutive in any final executable, so you may *not*
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*must* end up consecutive in any final executable, so you may *not*
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use the otherwise obvious ".comm" directive to allocate space for
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use the otherwise obvious ".comm" directive to allocate space for
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them. */
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them. */
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.bss
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.bss
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.global mem0
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.global mem0
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mem0: .space 1
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mem0: .space 1
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.global mem1
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.global mem1
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mem1: .space 1
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mem1: .space 1
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.global mem2
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.global mem2
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mem2: .space 1
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mem2: .space 1
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.global mem3
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.global mem3
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mem3: .space 1
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mem3: .space 1
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.global mem4
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.global mem4
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mem4: .space 1
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mem4: .space 1
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.global mem5
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.global mem5
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mem5: .space 1
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mem5: .space 1
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.global mem6
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.global mem6
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mem6: .space 1
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mem6: .space 1
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.global mem7
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.global mem7
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mem7: .space 1
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mem7: .space 1
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.global mem8
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.global mem8
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mem8: .space 1
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mem8: .space 1
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.global mem9
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.global mem9
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mem9: .space 1
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mem9: .space 1
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.global mem10
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.global mem10
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mem10: .space 1
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mem10: .space 1
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.global mem11
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.global mem11
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mem11: .space 1
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mem11: .space 1
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.global mem12
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.global mem12
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mem12: .space 1
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mem12: .space 1
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.global mem13
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.global mem13
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mem13: .space 1
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mem13: .space 1
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.global mem14
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.global mem14
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mem14: .space 1
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mem14: .space 1
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.global mem15
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.global mem15
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mem15: .space 1
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mem15: .space 1
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#endif
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#endif
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#ifdef L__m32c_eh_return
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#ifdef L__m32c_eh_return
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.text
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.text
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.global __m32c_eh_return
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.global __m32c_eh_return
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__m32c_eh_return:
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__m32c_eh_return:
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/* At this point, r0 has the stack adjustment, r1r3 has the
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/* At this point, r0 has the stack adjustment, r1r3 has the
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address to return to. The stack looks like this:
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address to return to. The stack looks like this:
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old_ra
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old_ra
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old_fp
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old_fp
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<- unwound sp
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<- unwound sp
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...
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...
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fb
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fb
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through
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through
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r0
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r0
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<- sp
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<- sp
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What we need to do is restore all the registers, update the
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What we need to do is restore all the registers, update the
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stack, and return to the right place.
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stack, and return to the right place.
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*/
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*/
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stc sp,a0
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stc sp,a0
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add.W A(#16,#24),a0
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add.W A(#16,#24),a0
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/* a0 points to the current stack, just above the register
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/* a0 points to the current stack, just above the register
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save areas */
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save areas */
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mov.w a0,a1
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mov.w a0,a1
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exts.w r0
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exts.w r0
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sub.W A(r0,r2r0),a1
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sub.W A(r0,r2r0),a1
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sub.W A(#3,#4),a1
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sub.W A(#3,#4),a1
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/* a1 points to the new stack. */
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/* a1 points to the new stack. */
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/* This is for the "rts" below. */
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/* This is for the "rts" below. */
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mov.w r1,[a1]
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mov.w r1,[a1]
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#ifdef A16
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#ifdef A16
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mov.w r2,r1
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mov.w r2,r1
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mov.b r1l,2[a1]
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mov.b r1l,2[a1]
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#else
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#else
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mov.w r2,2[a1]
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mov.w r2,2[a1]
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#endif
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#endif
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/* This is for the "popc sp" below. */
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/* This is for the "popc sp" below. */
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mov.W a1,[a0]
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mov.W a1,[a0]
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popm r0,r1,r2,r3,a0,a1,sb,fb
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popm r0,r1,r2,r3,a0,a1,sb,fb
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popc sp
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popc sp
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rts
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rts
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#endif
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#endif
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/* SImode arguments for SI foo(SI,SI) functions. */
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/* SImode arguments for SI foo(SI,SI) functions. */
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#ifdef A16
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#ifdef A16
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#define SAL 5[fb]
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#define SAL 5[fb]
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#define SAH 7[fb]
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#define SAH 7[fb]
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#define SBL 9[fb]
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#define SBL 9[fb]
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#define SBH 11[fb]
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#define SBH 11[fb]
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#else
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#else
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#define SAL 8[fb]
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#define SAL 8[fb]
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#define SAH 10[fb]
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#define SAH 10[fb]
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#define SBL 12[fb]
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#define SBL 12[fb]
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#define SBH 14[fb]
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#define SBH 14[fb]
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#endif
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#endif
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#ifdef L__m32c_mulsi3
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#ifdef L__m32c_mulsi3
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.text
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.text
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.global ___mulsi3
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.global ___mulsi3
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___mulsi3:
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___mulsi3:
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enter #0
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enter #0
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push.w r2
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push.w r2
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mov.w SAL,r0
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mov.w SAL,r0
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mulu.w SBL,r0 /* writes to r2r0 */
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mulu.w SBL,r0 /* writes to r2r0 */
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mov.w r0,mem0
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mov.w r0,mem0
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mov.w r2,mem2
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mov.w r2,mem2
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mov.w SAL,r0
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mov.w SAL,r0
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mulu.w SBH,r0 /* writes to r2r0 */
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mulu.w SBH,r0 /* writes to r2r0 */
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add.w r0,mem2
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add.w r0,mem2
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mov.w SAH,r0
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mov.w SAH,r0
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mulu.w SBL,r0 /* writes to r2r0 */
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mulu.w SBL,r0 /* writes to r2r0 */
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add.w r0,mem2
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add.w r0,mem2
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pop.w r2
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pop.w r2
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exitd
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exitd
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#endif
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#endif
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#ifdef L__m32c_cmpsi2
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#ifdef L__m32c_cmpsi2
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.text
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.text
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.global ___cmpsi2
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.global ___cmpsi2
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___cmpsi2:
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___cmpsi2:
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enter #0
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enter #0
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cmp.w SBH,SAH
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cmp.w SBH,SAH
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jgt cmpsi_gt
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jgt cmpsi_gt
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jlt cmpsi_lt
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jlt cmpsi_lt
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cmp.w SBL,SAL
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cmp.w SBL,SAL
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jgt cmpsi_gt
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jgt cmpsi_gt
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jlt cmpsi_lt
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jlt cmpsi_lt
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mov.w #1,r0
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mov.w #1,r0
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exitd
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exitd
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cmpsi_gt:
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cmpsi_gt:
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mov.w #2,r0
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mov.w #2,r0
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exitd
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exitd
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cmpsi_lt:
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cmpsi_lt:
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mov.w #0,r0
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mov.w #0,r0
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exitd
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exitd
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#endif
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#endif
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#ifdef L__m32c_ucmpsi2
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#ifdef L__m32c_ucmpsi2
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.text
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.text
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.global ___ucmpsi2
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.global ___ucmpsi2
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___ucmpsi2:
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___ucmpsi2:
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enter #0
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enter #0
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cmp.w SBH,SAH
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cmp.w SBH,SAH
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jgtu cmpsi_gt
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jgtu cmpsi_gt
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jltu cmpsi_lt
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jltu cmpsi_lt
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cmp.w SBL,SAL
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cmp.w SBL,SAL
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jgtu cmpsi_gt
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jgtu cmpsi_gt
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jltu cmpsi_lt
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jltu cmpsi_lt
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mov.w #1,r0
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mov.w #1,r0
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exitd
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exitd
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cmpsi_gt:
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cmpsi_gt:
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mov.w #2,r0
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mov.w #2,r0
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exitd
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exitd
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cmpsi_lt:
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cmpsi_lt:
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mov.w #0,r0
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mov.w #0,r0
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exitd
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exitd
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#endif
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#endif
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#ifdef L__m32c_jsri16
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#ifdef L__m32c_jsri16
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.data
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.data
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m32c_jsri_addr:
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m32c_jsri_addr:
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.byte 0, 0, 0
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.byte 0, 0, 0
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m32c_jsri_ret:
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m32c_jsri_ret:
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.byte 0, 0, 0
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.byte 0, 0, 0
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.text
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.text
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.global m32c_jsri16
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.global m32c_jsri16
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m32c_jsri16:
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m32c_jsri16:
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pop.w m32c_jsri_ret
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pop.w m32c_jsri_ret
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pop.b m32c_jsri_ret+2
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pop.b m32c_jsri_ret+2
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pop.w m32c_jsri_addr
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pop.w m32c_jsri_addr
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push.b m32c_jsri_ret+2
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push.b m32c_jsri_ret+2
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push.w m32c_jsri_ret
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push.w m32c_jsri_ret
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jmpi.a m32c_jsri_addr
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jmpi.a m32c_jsri_addr
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#endif
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#endif
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