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[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [config/] [m32c/] [m32c.c] - Diff between revs 282 and 384

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/* Target Code for R8C/M16C/M32C
/* Target Code for R8C/M16C/M32C
   Copyright (C) 2005, 2006, 2007, 2008, 2009
   Copyright (C) 2005, 2006, 2007, 2008, 2009
   Free Software Foundation, Inc.
   Free Software Foundation, Inc.
   Contributed by Red Hat.
   Contributed by Red Hat.
 
 
   This file is part of GCC.
   This file is part of GCC.
 
 
   GCC is free software; you can redistribute it and/or modify it
   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.
   option) any later version.
 
 
   GCC is distributed in the hope that it will be useful, but WITHOUT
   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.
   License for more details.
 
 
   You should have received a copy of the GNU General Public License
   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */
   <http://www.gnu.org/licenses/>.  */
 
 
#include "config.h"
#include "config.h"
#include "system.h"
#include "system.h"
#include "coretypes.h"
#include "coretypes.h"
#include "tm.h"
#include "tm.h"
#include "rtl.h"
#include "rtl.h"
#include "regs.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "hard-reg-set.h"
#include "real.h"
#include "real.h"
#include "insn-config.h"
#include "insn-config.h"
#include "conditions.h"
#include "conditions.h"
#include "insn-flags.h"
#include "insn-flags.h"
#include "output.h"
#include "output.h"
#include "insn-attr.h"
#include "insn-attr.h"
#include "flags.h"
#include "flags.h"
#include "recog.h"
#include "recog.h"
#include "reload.h"
#include "reload.h"
#include "toplev.h"
#include "toplev.h"
#include "obstack.h"
#include "obstack.h"
#include "tree.h"
#include "tree.h"
#include "expr.h"
#include "expr.h"
#include "optabs.h"
#include "optabs.h"
#include "except.h"
#include "except.h"
#include "function.h"
#include "function.h"
#include "ggc.h"
#include "ggc.h"
#include "target.h"
#include "target.h"
#include "target-def.h"
#include "target-def.h"
#include "tm_p.h"
#include "tm_p.h"
#include "langhooks.h"
#include "langhooks.h"
#include "gimple.h"
#include "gimple.h"
#include "df.h"
#include "df.h"
 
 
/* Prototypes */
/* Prototypes */
 
 
/* Used by m32c_pushm_popm.  */
/* Used by m32c_pushm_popm.  */
typedef enum
typedef enum
{
{
  PP_pushm,
  PP_pushm,
  PP_popm,
  PP_popm,
  PP_justcount
  PP_justcount
} Push_Pop_Type;
} Push_Pop_Type;
 
 
static bool m32c_function_needs_enter (void);
static bool m32c_function_needs_enter (void);
static tree interrupt_handler (tree *, tree, tree, int, bool *);
static tree interrupt_handler (tree *, tree, tree, int, bool *);
static tree function_vector_handler (tree *, tree, tree, int, bool *);
static tree function_vector_handler (tree *, tree, tree, int, bool *);
static int interrupt_p (tree node);
static int interrupt_p (tree node);
static int bank_switch_p (tree node);
static int bank_switch_p (tree node);
static int fast_interrupt_p (tree node);
static int fast_interrupt_p (tree node);
static int interrupt_p (tree node);
static int interrupt_p (tree node);
static bool m32c_asm_integer (rtx, unsigned int, int);
static bool m32c_asm_integer (rtx, unsigned int, int);
static int m32c_comp_type_attributes (const_tree, const_tree);
static int m32c_comp_type_attributes (const_tree, const_tree);
static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
static struct machine_function *m32c_init_machine_status (void);
static struct machine_function *m32c_init_machine_status (void);
static void m32c_insert_attributes (tree, tree *);
static void m32c_insert_attributes (tree, tree *);
static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
                                    const_tree, bool);
                                    const_tree, bool);
static bool m32c_promote_prototypes (const_tree);
static bool m32c_promote_prototypes (const_tree);
static int m32c_pushm_popm (Push_Pop_Type);
static int m32c_pushm_popm (Push_Pop_Type);
static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
static rtx m32c_struct_value_rtx (tree, int);
static rtx m32c_struct_value_rtx (tree, int);
static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
static int need_to_save (int);
static int need_to_save (int);
static rtx m32c_function_value (const_tree, const_tree, bool);
static rtx m32c_function_value (const_tree, const_tree, bool);
static rtx m32c_libcall_value (enum machine_mode, const_rtx);
static rtx m32c_libcall_value (enum machine_mode, const_rtx);
 
 
int current_function_special_page_vector (rtx);
int current_function_special_page_vector (rtx);
 
 
#define SYMBOL_FLAG_FUNCVEC_FUNCTION    (SYMBOL_FLAG_MACH_DEP << 0)
#define SYMBOL_FLAG_FUNCVEC_FUNCTION    (SYMBOL_FLAG_MACH_DEP << 0)
 
 
#define streq(a,b) (strcmp ((a), (b)) == 0)
#define streq(a,b) (strcmp ((a), (b)) == 0)
 
 
/* Internal support routines */
/* Internal support routines */
 
 
/* Debugging statements are tagged with DEBUG0 only so that they can
/* Debugging statements are tagged with DEBUG0 only so that they can
   be easily enabled individually, by replacing the '0' with '1' as
   be easily enabled individually, by replacing the '0' with '1' as
   needed.  */
   needed.  */
#define DEBUG0 0
#define DEBUG0 0
#define DEBUG1 1
#define DEBUG1 1
 
 
#if DEBUG0
#if DEBUG0
/* This is needed by some of the commented-out debug statements
/* This is needed by some of the commented-out debug statements
   below.  */
   below.  */
static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
#endif
#endif
static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
 
 
/* These are all to support encode_pattern().  */
/* These are all to support encode_pattern().  */
static char pattern[30], *patternp;
static char pattern[30], *patternp;
static GTY(()) rtx patternr[30];
static GTY(()) rtx patternr[30];
#define RTX_IS(x) (streq (pattern, x))
#define RTX_IS(x) (streq (pattern, x))
 
 
/* Some macros to simplify the logic throughout this file.  */
/* Some macros to simplify the logic throughout this file.  */
#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
 
 
#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
 
 
/* We do most RTX matching by converting the RTX into a string, and
/* We do most RTX matching by converting the RTX into a string, and
   using string compares.  This vastly simplifies the logic in many of
   using string compares.  This vastly simplifies the logic in many of
   the functions in this file.
   the functions in this file.
 
 
   On exit, pattern[] has the encoded string (use RTX_IS("...") to
   On exit, pattern[] has the encoded string (use RTX_IS("...") to
   compare it) and patternr[] has pointers to the nodes in the RTX
   compare it) and patternr[] has pointers to the nodes in the RTX
   corresponding to each character in the encoded string.  The latter
   corresponding to each character in the encoded string.  The latter
   is mostly used by print_operand().
   is mostly used by print_operand().
 
 
   Unrecognized patterns have '?' in them; this shows up when the
   Unrecognized patterns have '?' in them; this shows up when the
   assembler complains about syntax errors.
   assembler complains about syntax errors.
*/
*/
 
 
static void
static void
encode_pattern_1 (rtx x)
encode_pattern_1 (rtx x)
{
{
  int i;
  int i;
 
 
  if (patternp == pattern + sizeof (pattern) - 2)
  if (patternp == pattern + sizeof (pattern) - 2)
    {
    {
      patternp[-1] = '?';
      patternp[-1] = '?';
      return;
      return;
    }
    }
 
 
  patternr[patternp - pattern] = x;
  patternr[patternp - pattern] = x;
 
 
  switch (GET_CODE (x))
  switch (GET_CODE (x))
    {
    {
    case REG:
    case REG:
      *patternp++ = 'r';
      *patternp++ = 'r';
      break;
      break;
    case SUBREG:
    case SUBREG:
      if (GET_MODE_SIZE (GET_MODE (x)) !=
      if (GET_MODE_SIZE (GET_MODE (x)) !=
          GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
          GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
        *patternp++ = 'S';
        *patternp++ = 'S';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      break;
      break;
    case MEM:
    case MEM:
      *patternp++ = 'm';
      *patternp++ = 'm';
    case CONST:
    case CONST:
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      break;
      break;
    case PLUS:
    case PLUS:
      *patternp++ = '+';
      *patternp++ = '+';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 1));
      encode_pattern_1 (XEXP (x, 1));
      break;
      break;
    case PRE_DEC:
    case PRE_DEC:
      *patternp++ = '>';
      *patternp++ = '>';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      break;
      break;
    case POST_INC:
    case POST_INC:
      *patternp++ = '<';
      *patternp++ = '<';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      break;
      break;
    case LO_SUM:
    case LO_SUM:
      *patternp++ = 'L';
      *patternp++ = 'L';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 1));
      encode_pattern_1 (XEXP (x, 1));
      break;
      break;
    case HIGH:
    case HIGH:
      *patternp++ = 'H';
      *patternp++ = 'H';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      break;
      break;
    case SYMBOL_REF:
    case SYMBOL_REF:
      *patternp++ = 's';
      *patternp++ = 's';
      break;
      break;
    case LABEL_REF:
    case LABEL_REF:
      *patternp++ = 'l';
      *patternp++ = 'l';
      break;
      break;
    case CODE_LABEL:
    case CODE_LABEL:
      *patternp++ = 'c';
      *patternp++ = 'c';
      break;
      break;
    case CONST_INT:
    case CONST_INT:
    case CONST_DOUBLE:
    case CONST_DOUBLE:
      *patternp++ = 'i';
      *patternp++ = 'i';
      break;
      break;
    case UNSPEC:
    case UNSPEC:
      *patternp++ = 'u';
      *patternp++ = 'u';
      *patternp++ = '0' + XCINT (x, 1, UNSPEC);
      *patternp++ = '0' + XCINT (x, 1, UNSPEC);
      for (i = 0; i < XVECLEN (x, 0); i++)
      for (i = 0; i < XVECLEN (x, 0); i++)
        encode_pattern_1 (XVECEXP (x, 0, i));
        encode_pattern_1 (XVECEXP (x, 0, i));
      break;
      break;
    case USE:
    case USE:
      *patternp++ = 'U';
      *patternp++ = 'U';
      break;
      break;
    case PARALLEL:
    case PARALLEL:
      *patternp++ = '|';
      *patternp++ = '|';
      for (i = 0; i < XVECLEN (x, 0); i++)
      for (i = 0; i < XVECLEN (x, 0); i++)
        encode_pattern_1 (XVECEXP (x, 0, i));
        encode_pattern_1 (XVECEXP (x, 0, i));
      break;
      break;
    case EXPR_LIST:
    case EXPR_LIST:
      *patternp++ = 'E';
      *patternp++ = 'E';
      encode_pattern_1 (XEXP (x, 0));
      encode_pattern_1 (XEXP (x, 0));
      if (XEXP (x, 1))
      if (XEXP (x, 1))
        encode_pattern_1 (XEXP (x, 1));
        encode_pattern_1 (XEXP (x, 1));
      break;
      break;
    default:
    default:
      *patternp++ = '?';
      *patternp++ = '?';
#if DEBUG0
#if DEBUG0
      fprintf (stderr, "can't encode pattern %s\n",
      fprintf (stderr, "can't encode pattern %s\n",
               GET_RTX_NAME (GET_CODE (x)));
               GET_RTX_NAME (GET_CODE (x)));
      debug_rtx (x);
      debug_rtx (x);
      gcc_unreachable ();
      gcc_unreachable ();
#endif
#endif
      break;
      break;
    }
    }
}
}
 
 
static void
static void
encode_pattern (rtx x)
encode_pattern (rtx x)
{
{
  patternp = pattern;
  patternp = pattern;
  encode_pattern_1 (x);
  encode_pattern_1 (x);
  *patternp = 0;
  *patternp = 0;
}
}
 
 
/* Since register names indicate the mode they're used in, we need a
/* Since register names indicate the mode they're used in, we need a
   way to determine which name to refer to the register with.  Called
   way to determine which name to refer to the register with.  Called
   by print_operand().  */
   by print_operand().  */
 
 
static const char *
static const char *
reg_name_with_mode (int regno, enum machine_mode mode)
reg_name_with_mode (int regno, enum machine_mode mode)
{
{
  int mlen = GET_MODE_SIZE (mode);
  int mlen = GET_MODE_SIZE (mode);
  if (regno == R0_REGNO && mlen == 1)
  if (regno == R0_REGNO && mlen == 1)
    return "r0l";
    return "r0l";
  if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
  if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
    return "r2r0";
    return "r2r0";
  if (regno == R0_REGNO && mlen == 6)
  if (regno == R0_REGNO && mlen == 6)
    return "r2r1r0";
    return "r2r1r0";
  if (regno == R0_REGNO && mlen == 8)
  if (regno == R0_REGNO && mlen == 8)
    return "r3r1r2r0";
    return "r3r1r2r0";
  if (regno == R1_REGNO && mlen == 1)
  if (regno == R1_REGNO && mlen == 1)
    return "r1l";
    return "r1l";
  if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
  if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
    return "r3r1";
    return "r3r1";
  if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
  if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
    return "a1a0";
    return "a1a0";
  return reg_names[regno];
  return reg_names[regno];
}
}
 
 
/* How many bytes a register uses on stack when it's pushed.  We need
/* How many bytes a register uses on stack when it's pushed.  We need
   to know this because the push opcode needs to explicitly indicate
   to know this because the push opcode needs to explicitly indicate
   the size of the register, even though the name of the register
   the size of the register, even though the name of the register
   already tells it that.  Used by m32c_output_reg_{push,pop}, which
   already tells it that.  Used by m32c_output_reg_{push,pop}, which
   is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}.  */
   is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}.  */
 
 
static int
static int
reg_push_size (int regno)
reg_push_size (int regno)
{
{
  switch (regno)
  switch (regno)
    {
    {
    case R0_REGNO:
    case R0_REGNO:
    case R1_REGNO:
    case R1_REGNO:
      return 2;
      return 2;
    case R2_REGNO:
    case R2_REGNO:
    case R3_REGNO:
    case R3_REGNO:
    case FLG_REGNO:
    case FLG_REGNO:
      return 2;
      return 2;
    case A0_REGNO:
    case A0_REGNO:
    case A1_REGNO:
    case A1_REGNO:
    case SB_REGNO:
    case SB_REGNO:
    case FB_REGNO:
    case FB_REGNO:
    case SP_REGNO:
    case SP_REGNO:
      if (TARGET_A16)
      if (TARGET_A16)
        return 2;
        return 2;
      else
      else
        return 3;
        return 3;
    default:
    default:
      gcc_unreachable ();
      gcc_unreachable ();
    }
    }
}
}
 
 
static int *class_sizes = 0;
static int *class_sizes = 0;
 
 
/* Given two register classes, find the largest intersection between
/* Given two register classes, find the largest intersection between
   them.  If there is no intersection, return RETURNED_IF_EMPTY
   them.  If there is no intersection, return RETURNED_IF_EMPTY
   instead.  */
   instead.  */
static int
static int
reduce_class (int original_class, int limiting_class, int returned_if_empty)
reduce_class (int original_class, int limiting_class, int returned_if_empty)
{
{
  int cc = class_contents[original_class][0];
  int cc = class_contents[original_class][0];
  int i, best = NO_REGS;
  int i, best = NO_REGS;
  int best_size = 0;
  int best_size = 0;
 
 
  if (original_class == limiting_class)
  if (original_class == limiting_class)
    return original_class;
    return original_class;
 
 
  if (!class_sizes)
  if (!class_sizes)
    {
    {
      int r;
      int r;
      class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
      class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
      for (i = 0; i < LIM_REG_CLASSES; i++)
      for (i = 0; i < LIM_REG_CLASSES; i++)
        {
        {
          class_sizes[i] = 0;
          class_sizes[i] = 0;
          for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
          for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
            if (class_contents[i][0] & (1 << r))
            if (class_contents[i][0] & (1 << r))
              class_sizes[i]++;
              class_sizes[i]++;
        }
        }
    }
    }
 
 
  cc &= class_contents[limiting_class][0];
  cc &= class_contents[limiting_class][0];
  for (i = 0; i < LIM_REG_CLASSES; i++)
  for (i = 0; i < LIM_REG_CLASSES; i++)
    {
    {
      int ic = class_contents[i][0];
      int ic = class_contents[i][0];
 
 
      if ((~cc & ic) == 0)
      if ((~cc & ic) == 0)
        if (best_size < class_sizes[i])
        if (best_size < class_sizes[i])
          {
          {
            best = i;
            best = i;
            best_size = class_sizes[i];
            best_size = class_sizes[i];
          }
          }
 
 
    }
    }
  if (best == NO_REGS)
  if (best == NO_REGS)
    return returned_if_empty;
    return returned_if_empty;
  return best;
  return best;
}
}
 
 
/* Returns TRUE If there are any registers that exist in both register
/* Returns TRUE If there are any registers that exist in both register
   classes.  */
   classes.  */
static int
static int
classes_intersect (int class1, int class2)
classes_intersect (int class1, int class2)
{
{
  return class_contents[class1][0] & class_contents[class2][0];
  return class_contents[class1][0] & class_contents[class2][0];
}
}
 
 
/* Used by m32c_register_move_cost to determine if a move is
/* Used by m32c_register_move_cost to determine if a move is
   impossibly expensive.  */
   impossibly expensive.  */
static int
static int
class_can_hold_mode (int rclass, enum machine_mode mode)
class_can_hold_mode (int rclass, enum machine_mode mode)
{
{
  /* Cache the results:  0=untested  1=no  2=yes */
  /* Cache the results:  0=untested  1=no  2=yes */
  static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
  static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
  if (results[rclass][mode] == 0)
  if (results[rclass][mode] == 0)
    {
    {
      int r, n, i;
      int r, n, i;
      results[rclass][mode] = 1;
      results[rclass][mode] = 1;
      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
      for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
        if (class_contents[rclass][0] & (1 << r)
        if (class_contents[rclass][0] & (1 << r)
            && HARD_REGNO_MODE_OK (r, mode))
            && HARD_REGNO_MODE_OK (r, mode))
          {
          {
            int ok = 1;
            int ok = 1;
            n = HARD_REGNO_NREGS (r, mode);
            n = HARD_REGNO_NREGS (r, mode);
            for (i = 1; i < n; i++)
            for (i = 1; i < n; i++)
              if (!(class_contents[rclass][0] & (1 << (r + i))))
              if (!(class_contents[rclass][0] & (1 << (r + i))))
                ok = 0;
                ok = 0;
            if (ok)
            if (ok)
              {
              {
                results[rclass][mode] = 2;
                results[rclass][mode] = 2;
                break;
                break;
              }
              }
          }
          }
    }
    }
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "class %s can hold %s? %s\n",
  fprintf (stderr, "class %s can hold %s? %s\n",
           class_names[rclass], mode_name[mode],
           class_names[rclass], mode_name[mode],
           (results[rclass][mode] == 2) ? "yes" : "no");
           (results[rclass][mode] == 2) ? "yes" : "no");
#endif
#endif
  return results[rclass][mode] == 2;
  return results[rclass][mode] == 2;
}
}
 
 
/* Run-time Target Specification.  */
/* Run-time Target Specification.  */
 
 
/* Memregs are memory locations that gcc treats like general
/* Memregs are memory locations that gcc treats like general
   registers, as there are a limited number of true registers and the
   registers, as there are a limited number of true registers and the
   m32c families can use memory in most places that registers can be
   m32c families can use memory in most places that registers can be
   used.
   used.
 
 
   However, since memory accesses are more expensive than registers,
   However, since memory accesses are more expensive than registers,
   we allow the user to limit the number of memregs available, in
   we allow the user to limit the number of memregs available, in
   order to try to persuade gcc to try harder to use real registers.
   order to try to persuade gcc to try harder to use real registers.
 
 
   Memregs are provided by m32c-lib1.S.
   Memregs are provided by m32c-lib1.S.
*/
*/
 
 
int target_memregs = 16;
int target_memregs = 16;
static bool target_memregs_set = FALSE;
static bool target_memregs_set = FALSE;
int ok_to_change_target_memregs = TRUE;
int ok_to_change_target_memregs = TRUE;
 
 
#undef  TARGET_HANDLE_OPTION
#undef  TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION m32c_handle_option
#define TARGET_HANDLE_OPTION m32c_handle_option
static bool
static bool
m32c_handle_option (size_t code,
m32c_handle_option (size_t code,
                    const char *arg ATTRIBUTE_UNUSED,
                    const char *arg ATTRIBUTE_UNUSED,
                    int value ATTRIBUTE_UNUSED)
                    int value ATTRIBUTE_UNUSED)
{
{
  if (code == OPT_memregs_)
  if (code == OPT_memregs_)
    {
    {
      target_memregs_set = TRUE;
      target_memregs_set = TRUE;
      target_memregs = atoi (arg);
      target_memregs = atoi (arg);
    }
    }
  return TRUE;
  return TRUE;
}
}
 
 
/* Implements OVERRIDE_OPTIONS.  We limit memregs to 0..16, and
/* Implements OVERRIDE_OPTIONS.  We limit memregs to 0..16, and
   provide a default.  */
   provide a default.  */
void
void
m32c_override_options (void)
m32c_override_options (void)
{
{
  if (target_memregs_set)
  if (target_memregs_set)
    {
    {
      if (target_memregs < 0 || target_memregs > 16)
      if (target_memregs < 0 || target_memregs > 16)
        error ("invalid target memregs value '%d'", target_memregs);
        error ("invalid target memregs value '%d'", target_memregs);
    }
    }
  else
  else
    target_memregs = 16;
    target_memregs = 16;
 
 
  if (TARGET_A24)
  if (TARGET_A24)
    flag_ivopts = 0;
    flag_ivopts = 0;
}
}
 
 
/* Defining data structures for per-function information */
/* Defining data structures for per-function information */
 
 
/* The usual; we set up our machine_function data.  */
/* The usual; we set up our machine_function data.  */
static struct machine_function *
static struct machine_function *
m32c_init_machine_status (void)
m32c_init_machine_status (void)
{
{
  struct machine_function *machine;
  struct machine_function *machine;
  machine =
  machine =
    (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
    (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
 
 
  return machine;
  return machine;
}
}
 
 
/* Implements INIT_EXPANDERS.  We just set up to call the above
/* Implements INIT_EXPANDERS.  We just set up to call the above
   function.  */
   function.  */
void
void
m32c_init_expanders (void)
m32c_init_expanders (void)
{
{
  init_machine_status = m32c_init_machine_status;
  init_machine_status = m32c_init_machine_status;
}
}
 
 
/* Storage Layout */
/* Storage Layout */
 
 
/* Register Basics */
/* Register Basics */
 
 
/* Basic Characteristics of Registers */
/* Basic Characteristics of Registers */
 
 
/* Whether a mode fits in a register is complex enough to warrant a
/* Whether a mode fits in a register is complex enough to warrant a
   table.  */
   table.  */
static struct
static struct
{
{
  char qi_regs;
  char qi_regs;
  char hi_regs;
  char hi_regs;
  char pi_regs;
  char pi_regs;
  char si_regs;
  char si_regs;
  char di_regs;
  char di_regs;
} nregs_table[FIRST_PSEUDO_REGISTER] =
} nregs_table[FIRST_PSEUDO_REGISTER] =
{
{
  { 1, 1, 2, 2, 4 },            /* r0 */
  { 1, 1, 2, 2, 4 },            /* r0 */
  { 0, 1, 0, 0, 0 },                /* r2 */
  { 0, 1, 0, 0, 0 },                /* r2 */
  { 1, 1, 2, 2, 0 },             /* r1 */
  { 1, 1, 2, 2, 0 },             /* r1 */
  { 0, 1, 0, 0, 0 },                /* r3 */
  { 0, 1, 0, 0, 0 },                /* r3 */
  { 0, 1, 1, 0, 0 },               /* a0 */
  { 0, 1, 1, 0, 0 },               /* a0 */
  { 0, 1, 1, 0, 0 },               /* a1 */
  { 0, 1, 1, 0, 0 },               /* a1 */
  { 0, 1, 1, 0, 0 },               /* sb */
  { 0, 1, 1, 0, 0 },               /* sb */
  { 0, 1, 1, 0, 0 },               /* fb */
  { 0, 1, 1, 0, 0 },               /* fb */
  { 0, 1, 1, 0, 0 },               /* sp */
  { 0, 1, 1, 0, 0 },               /* sp */
  { 1, 1, 1, 0, 0 },              /* pc */
  { 1, 1, 1, 0, 0 },              /* pc */
  { 0, 0, 0, 0, 0 },         /* fl */
  { 0, 0, 0, 0, 0 },         /* fl */
  { 1, 1, 1, 0, 0 },              /* ap */
  { 1, 1, 1, 0, 0 },              /* ap */
  { 1, 1, 2, 2, 4 },            /* mem0 */
  { 1, 1, 2, 2, 4 },            /* mem0 */
  { 1, 1, 2, 2, 4 },            /* mem1 */
  { 1, 1, 2, 2, 4 },            /* mem1 */
  { 1, 1, 2, 2, 4 },            /* mem2 */
  { 1, 1, 2, 2, 4 },            /* mem2 */
  { 1, 1, 2, 2, 4 },            /* mem3 */
  { 1, 1, 2, 2, 4 },            /* mem3 */
  { 1, 1, 2, 2, 4 },            /* mem4 */
  { 1, 1, 2, 2, 4 },            /* mem4 */
  { 1, 1, 2, 2, 0 },             /* mem5 */
  { 1, 1, 2, 2, 0 },             /* mem5 */
  { 1, 1, 2, 2, 0 },             /* mem6 */
  { 1, 1, 2, 2, 0 },             /* mem6 */
  { 1, 1, 0, 0, 0 },               /* mem7 */
  { 1, 1, 0, 0, 0 },               /* mem7 */
};
};
 
 
/* Implements CONDITIONAL_REGISTER_USAGE.  We adjust the number of
/* Implements CONDITIONAL_REGISTER_USAGE.  We adjust the number of
   available memregs, and select which registers need to be preserved
   available memregs, and select which registers need to be preserved
   across calls based on the chip family.  */
   across calls based on the chip family.  */
 
 
void
void
m32c_conditional_register_usage (void)
m32c_conditional_register_usage (void)
{
{
  int i;
  int i;
 
 
  if (0 <= target_memregs && target_memregs <= 16)
  if (0 <= target_memregs && target_memregs <= 16)
    {
    {
      /* The command line option is bytes, but our "registers" are
      /* The command line option is bytes, but our "registers" are
         16-bit words.  */
         16-bit words.  */
      for (i = (target_memregs+1)/2; i < 8; i++)
      for (i = (target_memregs+1)/2; i < 8; i++)
        {
        {
          fixed_regs[MEM0_REGNO + i] = 1;
          fixed_regs[MEM0_REGNO + i] = 1;
          CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
          CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
        }
        }
    }
    }
 
 
  /* M32CM and M32C preserve more registers across function calls.  */
  /* M32CM and M32C preserve more registers across function calls.  */
  if (TARGET_A24)
  if (TARGET_A24)
    {
    {
      call_used_regs[R1_REGNO] = 0;
      call_used_regs[R1_REGNO] = 0;
      call_used_regs[R2_REGNO] = 0;
      call_used_regs[R2_REGNO] = 0;
      call_used_regs[R3_REGNO] = 0;
      call_used_regs[R3_REGNO] = 0;
      call_used_regs[A0_REGNO] = 0;
      call_used_regs[A0_REGNO] = 0;
      call_used_regs[A1_REGNO] = 0;
      call_used_regs[A1_REGNO] = 0;
    }
    }
}
}
 
 
/* How Values Fit in Registers */
/* How Values Fit in Registers */
 
 
/* Implements HARD_REGNO_NREGS.  This is complicated by the fact that
/* Implements HARD_REGNO_NREGS.  This is complicated by the fact that
   different registers are different sizes from each other, *and* may
   different registers are different sizes from each other, *and* may
   be different sizes in different chip families.  */
   be different sizes in different chip families.  */
static int
static int
m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
{
{
  if (regno == FLG_REGNO && mode == CCmode)
  if (regno == FLG_REGNO && mode == CCmode)
    return 1;
    return 1;
  if (regno >= FIRST_PSEUDO_REGISTER)
  if (regno >= FIRST_PSEUDO_REGISTER)
    return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
    return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
 
 
  if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
  if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
    return (GET_MODE_SIZE (mode) + 1) / 2;
    return (GET_MODE_SIZE (mode) + 1) / 2;
 
 
  if (GET_MODE_SIZE (mode) <= 1)
  if (GET_MODE_SIZE (mode) <= 1)
    return nregs_table[regno].qi_regs;
    return nregs_table[regno].qi_regs;
  if (GET_MODE_SIZE (mode) <= 2)
  if (GET_MODE_SIZE (mode) <= 2)
    return nregs_table[regno].hi_regs;
    return nregs_table[regno].hi_regs;
  if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
  if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
    return 2;
    return 2;
  if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
  if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
    return nregs_table[regno].pi_regs;
    return nregs_table[regno].pi_regs;
  if (GET_MODE_SIZE (mode) <= 4)
  if (GET_MODE_SIZE (mode) <= 4)
    return nregs_table[regno].si_regs;
    return nregs_table[regno].si_regs;
  if (GET_MODE_SIZE (mode) <= 8)
  if (GET_MODE_SIZE (mode) <= 8)
    return nregs_table[regno].di_regs;
    return nregs_table[regno].di_regs;
  return 0;
  return 0;
}
}
 
 
int
int
m32c_hard_regno_nregs (int regno, enum machine_mode mode)
m32c_hard_regno_nregs (int regno, enum machine_mode mode)
{
{
  int rv = m32c_hard_regno_nregs_1 (regno, mode);
  int rv = m32c_hard_regno_nregs_1 (regno, mode);
  return rv ? rv : 1;
  return rv ? rv : 1;
}
}
 
 
/* Implements HARD_REGNO_MODE_OK.  The above function does the work
/* Implements HARD_REGNO_MODE_OK.  The above function does the work
   already; just test its return value.  */
   already; just test its return value.  */
int
int
m32c_hard_regno_ok (int regno, enum machine_mode mode)
m32c_hard_regno_ok (int regno, enum machine_mode mode)
{
{
  return m32c_hard_regno_nregs_1 (regno, mode) != 0;
  return m32c_hard_regno_nregs_1 (regno, mode) != 0;
}
}
 
 
/* Implements MODES_TIEABLE_P.  In general, modes aren't tieable since
/* Implements MODES_TIEABLE_P.  In general, modes aren't tieable since
   registers are all different sizes.  However, since most modes are
   registers are all different sizes.  However, since most modes are
   bigger than our registers anyway, it's easier to implement this
   bigger than our registers anyway, it's easier to implement this
   function that way, leaving QImode as the only unique case.  */
   function that way, leaving QImode as the only unique case.  */
int
int
m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
{
{
  if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
  if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
    return 1;
    return 1;
 
 
#if 0
#if 0
  if (m1 == QImode || m2 == QImode)
  if (m1 == QImode || m2 == QImode)
    return 0;
    return 0;
#endif
#endif
 
 
  return 1;
  return 1;
}
}
 
 
/* Register Classes */
/* Register Classes */
 
 
/* Implements REGNO_REG_CLASS.  */
/* Implements REGNO_REG_CLASS.  */
enum machine_mode
enum machine_mode
m32c_regno_reg_class (int regno)
m32c_regno_reg_class (int regno)
{
{
  switch (regno)
  switch (regno)
    {
    {
    case R0_REGNO:
    case R0_REGNO:
      return R0_REGS;
      return R0_REGS;
    case R1_REGNO:
    case R1_REGNO:
      return R1_REGS;
      return R1_REGS;
    case R2_REGNO:
    case R2_REGNO:
      return R2_REGS;
      return R2_REGS;
    case R3_REGNO:
    case R3_REGNO:
      return R3_REGS;
      return R3_REGS;
    case A0_REGNO:
    case A0_REGNO:
    case A1_REGNO:
    case A1_REGNO:
      return A_REGS;
      return A_REGS;
    case SB_REGNO:
    case SB_REGNO:
      return SB_REGS;
      return SB_REGS;
    case FB_REGNO:
    case FB_REGNO:
      return FB_REGS;
      return FB_REGS;
    case SP_REGNO:
    case SP_REGNO:
      return SP_REGS;
      return SP_REGS;
    case FLG_REGNO:
    case FLG_REGNO:
      return FLG_REGS;
      return FLG_REGS;
    default:
    default:
      if (IS_MEM_REGNO (regno))
      if (IS_MEM_REGNO (regno))
        return MEM_REGS;
        return MEM_REGS;
      return ALL_REGS;
      return ALL_REGS;
    }
    }
}
}
 
 
/* Implements REG_CLASS_FROM_CONSTRAINT.  Note that some constraints only match
/* Implements REG_CLASS_FROM_CONSTRAINT.  Note that some constraints only match
   for certain chip families.  */
   for certain chip families.  */
int
int
m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
{
{
  if (memcmp (s, "Rsp", 3) == 0)
  if (memcmp (s, "Rsp", 3) == 0)
    return SP_REGS;
    return SP_REGS;
  if (memcmp (s, "Rfb", 3) == 0)
  if (memcmp (s, "Rfb", 3) == 0)
    return FB_REGS;
    return FB_REGS;
  if (memcmp (s, "Rsb", 3) == 0)
  if (memcmp (s, "Rsb", 3) == 0)
    return SB_REGS;
    return SB_REGS;
  if (memcmp (s, "Rcr", 3) == 0)
  if (memcmp (s, "Rcr", 3) == 0)
    return TARGET_A16 ? CR_REGS : NO_REGS;
    return TARGET_A16 ? CR_REGS : NO_REGS;
  if (memcmp (s, "Rcl", 3) == 0)
  if (memcmp (s, "Rcl", 3) == 0)
    return TARGET_A24 ? CR_REGS : NO_REGS;
    return TARGET_A24 ? CR_REGS : NO_REGS;
  if (memcmp (s, "R0w", 3) == 0)
  if (memcmp (s, "R0w", 3) == 0)
    return R0_REGS;
    return R0_REGS;
  if (memcmp (s, "R1w", 3) == 0)
  if (memcmp (s, "R1w", 3) == 0)
    return R1_REGS;
    return R1_REGS;
  if (memcmp (s, "R2w", 3) == 0)
  if (memcmp (s, "R2w", 3) == 0)
    return R2_REGS;
    return R2_REGS;
  if (memcmp (s, "R3w", 3) == 0)
  if (memcmp (s, "R3w", 3) == 0)
    return R3_REGS;
    return R3_REGS;
  if (memcmp (s, "R02", 3) == 0)
  if (memcmp (s, "R02", 3) == 0)
    return R02_REGS;
    return R02_REGS;
  if (memcmp (s, "R13", 3) == 0)
  if (memcmp (s, "R13", 3) == 0)
    return R13_REGS;
    return R13_REGS;
  if (memcmp (s, "R03", 3) == 0)
  if (memcmp (s, "R03", 3) == 0)
    return R03_REGS;
    return R03_REGS;
  if (memcmp (s, "Rdi", 3) == 0)
  if (memcmp (s, "Rdi", 3) == 0)
    return DI_REGS;
    return DI_REGS;
  if (memcmp (s, "Rhl", 3) == 0)
  if (memcmp (s, "Rhl", 3) == 0)
    return HL_REGS;
    return HL_REGS;
  if (memcmp (s, "R23", 3) == 0)
  if (memcmp (s, "R23", 3) == 0)
    return R23_REGS;
    return R23_REGS;
  if (memcmp (s, "Ra0", 3) == 0)
  if (memcmp (s, "Ra0", 3) == 0)
    return A0_REGS;
    return A0_REGS;
  if (memcmp (s, "Ra1", 3) == 0)
  if (memcmp (s, "Ra1", 3) == 0)
    return A1_REGS;
    return A1_REGS;
  if (memcmp (s, "Raa", 3) == 0)
  if (memcmp (s, "Raa", 3) == 0)
    return A_REGS;
    return A_REGS;
  if (memcmp (s, "Raw", 3) == 0)
  if (memcmp (s, "Raw", 3) == 0)
    return TARGET_A16 ? A_REGS : NO_REGS;
    return TARGET_A16 ? A_REGS : NO_REGS;
  if (memcmp (s, "Ral", 3) == 0)
  if (memcmp (s, "Ral", 3) == 0)
    return TARGET_A24 ? A_REGS : NO_REGS;
    return TARGET_A24 ? A_REGS : NO_REGS;
  if (memcmp (s, "Rqi", 3) == 0)
  if (memcmp (s, "Rqi", 3) == 0)
    return QI_REGS;
    return QI_REGS;
  if (memcmp (s, "Rad", 3) == 0)
  if (memcmp (s, "Rad", 3) == 0)
    return AD_REGS;
    return AD_REGS;
  if (memcmp (s, "Rsi", 3) == 0)
  if (memcmp (s, "Rsi", 3) == 0)
    return SI_REGS;
    return SI_REGS;
  if (memcmp (s, "Rhi", 3) == 0)
  if (memcmp (s, "Rhi", 3) == 0)
    return HI_REGS;
    return HI_REGS;
  if (memcmp (s, "Rhc", 3) == 0)
  if (memcmp (s, "Rhc", 3) == 0)
    return HC_REGS;
    return HC_REGS;
  if (memcmp (s, "Rra", 3) == 0)
  if (memcmp (s, "Rra", 3) == 0)
    return RA_REGS;
    return RA_REGS;
  if (memcmp (s, "Rfl", 3) == 0)
  if (memcmp (s, "Rfl", 3) == 0)
    return FLG_REGS;
    return FLG_REGS;
  if (memcmp (s, "Rmm", 3) == 0)
  if (memcmp (s, "Rmm", 3) == 0)
    {
    {
      if (fixed_regs[MEM0_REGNO])
      if (fixed_regs[MEM0_REGNO])
        return NO_REGS;
        return NO_REGS;
      return MEM_REGS;
      return MEM_REGS;
    }
    }
 
 
  /* PSImode registers - i.e. whatever can hold a pointer.  */
  /* PSImode registers - i.e. whatever can hold a pointer.  */
  if (memcmp (s, "Rpi", 3) == 0)
  if (memcmp (s, "Rpi", 3) == 0)
    {
    {
      if (TARGET_A16)
      if (TARGET_A16)
        return HI_REGS;
        return HI_REGS;
      else
      else
        return RA_REGS; /* r2r0 and r3r1 can hold pointers.  */
        return RA_REGS; /* r2r0 and r3r1 can hold pointers.  */
    }
    }
 
 
  /* We handle this one as an EXTRA_CONSTRAINT.  */
  /* We handle this one as an EXTRA_CONSTRAINT.  */
  if (memcmp (s, "Rpa", 3) == 0)
  if (memcmp (s, "Rpa", 3) == 0)
    return NO_REGS;
    return NO_REGS;
 
 
  if (*s == 'R')
  if (*s == 'R')
    {
    {
      fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
      fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
      gcc_unreachable();
      gcc_unreachable();
    }
    }
 
 
  return NO_REGS;
  return NO_REGS;
}
}
 
 
/* Implements REGNO_OK_FOR_BASE_P.  */
/* Implements REGNO_OK_FOR_BASE_P.  */
int
int
m32c_regno_ok_for_base_p (int regno)
m32c_regno_ok_for_base_p (int regno)
{
{
  if (regno == A0_REGNO
  if (regno == A0_REGNO
      || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
      || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
    return 1;
    return 1;
  return 0;
  return 0;
}
}
 
 
#define DEBUG_RELOAD 0
#define DEBUG_RELOAD 0
 
 
/* Implements PREFERRED_RELOAD_CLASS.  In general, prefer general
/* Implements PREFERRED_RELOAD_CLASS.  In general, prefer general
   registers of the appropriate size.  */
   registers of the appropriate size.  */
int
int
m32c_preferred_reload_class (rtx x, int rclass)
m32c_preferred_reload_class (rtx x, int rclass)
{
{
  int newclass = rclass;
  int newclass = rclass;
 
 
#if DEBUG_RELOAD
#if DEBUG_RELOAD
  fprintf (stderr, "\npreferred_reload_class for %s is ",
  fprintf (stderr, "\npreferred_reload_class for %s is ",
           class_names[rclass]);
           class_names[rclass]);
#endif
#endif
  if (rclass == NO_REGS)
  if (rclass == NO_REGS)
    rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
    rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
 
 
  if (classes_intersect (rclass, CR_REGS))
  if (classes_intersect (rclass, CR_REGS))
    {
    {
      switch (GET_MODE (x))
      switch (GET_MODE (x))
        {
        {
        case QImode:
        case QImode:
          newclass = HL_REGS;
          newclass = HL_REGS;
          break;
          break;
        default:
        default:
          /*      newclass = HI_REGS; */
          /*      newclass = HI_REGS; */
          break;
          break;
        }
        }
    }
    }
 
 
  else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
  else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
    newclass = SI_REGS;
    newclass = SI_REGS;
  else if (GET_MODE_SIZE (GET_MODE (x)) > 4
  else if (GET_MODE_SIZE (GET_MODE (x)) > 4
           && ~class_contents[rclass][0] & 0x000f)
           && ~class_contents[rclass][0] & 0x000f)
    newclass = DI_REGS;
    newclass = DI_REGS;
 
 
  rclass = reduce_class (rclass, newclass, rclass);
  rclass = reduce_class (rclass, newclass, rclass);
 
 
  if (GET_MODE (x) == QImode)
  if (GET_MODE (x) == QImode)
    rclass = reduce_class (rclass, HL_REGS, rclass);
    rclass = reduce_class (rclass, HL_REGS, rclass);
 
 
#if DEBUG_RELOAD
#if DEBUG_RELOAD
  fprintf (stderr, "%s\n", class_names[rclass]);
  fprintf (stderr, "%s\n", class_names[rclass]);
  debug_rtx (x);
  debug_rtx (x);
 
 
  if (GET_CODE (x) == MEM
  if (GET_CODE (x) == MEM
      && GET_CODE (XEXP (x, 0)) == PLUS
      && GET_CODE (XEXP (x, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
    fprintf (stderr, "Glorm!\n");
    fprintf (stderr, "Glorm!\n");
#endif
#endif
  return rclass;
  return rclass;
}
}
 
 
/* Implements PREFERRED_OUTPUT_RELOAD_CLASS.  */
/* Implements PREFERRED_OUTPUT_RELOAD_CLASS.  */
int
int
m32c_preferred_output_reload_class (rtx x, int rclass)
m32c_preferred_output_reload_class (rtx x, int rclass)
{
{
  return m32c_preferred_reload_class (x, rclass);
  return m32c_preferred_reload_class (x, rclass);
}
}
 
 
/* Implements LIMIT_RELOAD_CLASS.  We basically want to avoid using
/* Implements LIMIT_RELOAD_CLASS.  We basically want to avoid using
   address registers for reloads since they're needed for address
   address registers for reloads since they're needed for address
   reloads.  */
   reloads.  */
int
int
m32c_limit_reload_class (enum machine_mode mode, int rclass)
m32c_limit_reload_class (enum machine_mode mode, int rclass)
{
{
#if DEBUG_RELOAD
#if DEBUG_RELOAD
  fprintf (stderr, "limit_reload_class for %s: %s ->",
  fprintf (stderr, "limit_reload_class for %s: %s ->",
           mode_name[mode], class_names[rclass]);
           mode_name[mode], class_names[rclass]);
#endif
#endif
 
 
  if (mode == QImode)
  if (mode == QImode)
    rclass = reduce_class (rclass, HL_REGS, rclass);
    rclass = reduce_class (rclass, HL_REGS, rclass);
  else if (mode == HImode)
  else if (mode == HImode)
    rclass = reduce_class (rclass, HI_REGS, rclass);
    rclass = reduce_class (rclass, HI_REGS, rclass);
  else if (mode == SImode)
  else if (mode == SImode)
    rclass = reduce_class (rclass, SI_REGS, rclass);
    rclass = reduce_class (rclass, SI_REGS, rclass);
 
 
  if (rclass != A_REGS)
  if (rclass != A_REGS)
    rclass = reduce_class (rclass, DI_REGS, rclass);
    rclass = reduce_class (rclass, DI_REGS, rclass);
 
 
#if DEBUG_RELOAD
#if DEBUG_RELOAD
  fprintf (stderr, " %s\n", class_names[rclass]);
  fprintf (stderr, " %s\n", class_names[rclass]);
#endif
#endif
  return rclass;
  return rclass;
}
}
 
 
/* Implements SECONDARY_RELOAD_CLASS.  QImode have to be reloaded in
/* Implements SECONDARY_RELOAD_CLASS.  QImode have to be reloaded in
   r0 or r1, as those are the only real QImode registers.  CR regs get
   r0 or r1, as those are the only real QImode registers.  CR regs get
   reloaded through appropriately sized general or address
   reloaded through appropriately sized general or address
   registers.  */
   registers.  */
int
int
m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
{
{
  int cc = class_contents[rclass][0];
  int cc = class_contents[rclass][0];
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "\nsecondary reload class %s %s\n",
  fprintf (stderr, "\nsecondary reload class %s %s\n",
           class_names[rclass], mode_name[mode]);
           class_names[rclass], mode_name[mode]);
  debug_rtx (x);
  debug_rtx (x);
#endif
#endif
  if (mode == QImode
  if (mode == QImode
      && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
      && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
    return QI_REGS;
    return QI_REGS;
  if (classes_intersect (rclass, CR_REGS)
  if (classes_intersect (rclass, CR_REGS)
      && GET_CODE (x) == REG
      && GET_CODE (x) == REG
      && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
      && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
    return TARGET_A16 ? HI_REGS : A_REGS;
    return TARGET_A16 ? HI_REGS : A_REGS;
  return NO_REGS;
  return NO_REGS;
}
}
 
 
/* Implements CLASS_LIKELY_SPILLED_P.  A_REGS is needed for address
/* Implements CLASS_LIKELY_SPILLED_P.  A_REGS is needed for address
   reloads.  */
   reloads.  */
int
int
m32c_class_likely_spilled_p (int regclass)
m32c_class_likely_spilled_p (int regclass)
{
{
  if (regclass == A_REGS)
  if (regclass == A_REGS)
    return 1;
    return 1;
  return reg_class_size[regclass] == 1;
  return reg_class_size[regclass] == 1;
}
}
 
 
/* Implements CLASS_MAX_NREGS.  We calculate this according to its
/* Implements CLASS_MAX_NREGS.  We calculate this according to its
   documented meaning, to avoid potential inconsistencies with actual
   documented meaning, to avoid potential inconsistencies with actual
   class definitions.  */
   class definitions.  */
int
int
m32c_class_max_nregs (int regclass, enum machine_mode mode)
m32c_class_max_nregs (int regclass, enum machine_mode mode)
{
{
  int rn, max = 0;
  int rn, max = 0;
 
 
  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
    if (class_contents[regclass][0] & (1 << rn))
    if (class_contents[regclass][0] & (1 << rn))
      {
      {
        int n = m32c_hard_regno_nregs (rn, mode);
        int n = m32c_hard_regno_nregs (rn, mode);
        if (max < n)
        if (max < n)
          max = n;
          max = n;
      }
      }
  return max;
  return max;
}
}
 
 
/* Implements CANNOT_CHANGE_MODE_CLASS.  Only r0 and r1 can change to
/* Implements CANNOT_CHANGE_MODE_CLASS.  Only r0 and r1 can change to
   QI (r0l, r1l) because the chip doesn't support QI ops on other
   QI (r0l, r1l) because the chip doesn't support QI ops on other
   registers (well, it does on a0/a1 but if we let gcc do that, reload
   registers (well, it does on a0/a1 but if we let gcc do that, reload
   suffers).  Otherwise, we allow changes to larger modes.  */
   suffers).  Otherwise, we allow changes to larger modes.  */
int
int
m32c_cannot_change_mode_class (enum machine_mode from,
m32c_cannot_change_mode_class (enum machine_mode from,
                               enum machine_mode to, int rclass)
                               enum machine_mode to, int rclass)
{
{
  int rn;
  int rn;
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "cannot change from %s to %s in %s\n",
  fprintf (stderr, "cannot change from %s to %s in %s\n",
           mode_name[from], mode_name[to], class_names[rclass]);
           mode_name[from], mode_name[to], class_names[rclass]);
#endif
#endif
 
 
  /* If the larger mode isn't allowed in any of these registers, we
  /* If the larger mode isn't allowed in any of these registers, we
     can't allow the change.  */
     can't allow the change.  */
  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
  for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
    if (class_contents[rclass][0] & (1 << rn))
    if (class_contents[rclass][0] & (1 << rn))
      if (! m32c_hard_regno_ok (rn, to))
      if (! m32c_hard_regno_ok (rn, to))
        return 1;
        return 1;
 
 
  if (to == QImode)
  if (to == QImode)
    return (class_contents[rclass][0] & 0x1ffa);
    return (class_contents[rclass][0] & 0x1ffa);
 
 
  if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
  if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
      && GET_MODE_SIZE (from) > 1)
      && GET_MODE_SIZE (from) > 1)
    return 0;
    return 0;
  if (GET_MODE_SIZE (from) > 2) /* all other regs */
  if (GET_MODE_SIZE (from) > 2) /* all other regs */
    return 0;
    return 0;
 
 
  return 1;
  return 1;
}
}
 
 
/* Helpers for the rest of the file.  */
/* Helpers for the rest of the file.  */
/* TRUE if the rtx is a REG rtx for the given register.  */
/* TRUE if the rtx is a REG rtx for the given register.  */
#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
                           && REGNO (rtx) == regno)
                           && REGNO (rtx) == regno)
/* TRUE if the rtx is a pseudo - specifically, one we can use as a
/* TRUE if the rtx is a pseudo - specifically, one we can use as a
   base register in address calculations (hence the "strict"
   base register in address calculations (hence the "strict"
   argument).  */
   argument).  */
#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
                               && (REGNO (rtx) == AP_REGNO \
                               && (REGNO (rtx) == AP_REGNO \
                                   || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
                                   || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
 
 
/* Implements CONST_OK_FOR_CONSTRAINT_P.  Currently, all constant
/* Implements CONST_OK_FOR_CONSTRAINT_P.  Currently, all constant
   constraints start with 'I', with the next two characters indicating
   constraints start with 'I', with the next two characters indicating
   the type and size of the range allowed.  */
   the type and size of the range allowed.  */
int
int
m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
                                char c ATTRIBUTE_UNUSED, const char *str)
                                char c ATTRIBUTE_UNUSED, const char *str)
{
{
  /* s=signed u=unsigned n=nonzero m=minus l=log2able,
  /* s=signed u=unsigned n=nonzero m=minus l=log2able,
     [sun] bits [SUN] bytes, p=pointer size
     [sun] bits [SUN] bytes, p=pointer size
     I[-0-9][0-9] matches that number */
     I[-0-9][0-9] matches that number */
  if (memcmp (str, "Is3", 3) == 0)
  if (memcmp (str, "Is3", 3) == 0)
    {
    {
      return (-8 <= value && value <= 7);
      return (-8 <= value && value <= 7);
    }
    }
  if (memcmp (str, "IS1", 3) == 0)
  if (memcmp (str, "IS1", 3) == 0)
    {
    {
      return (-128 <= value && value <= 127);
      return (-128 <= value && value <= 127);
    }
    }
  if (memcmp (str, "IS2", 3) == 0)
  if (memcmp (str, "IS2", 3) == 0)
    {
    {
      return (-32768 <= value && value <= 32767);
      return (-32768 <= value && value <= 32767);
    }
    }
  if (memcmp (str, "IU2", 3) == 0)
  if (memcmp (str, "IU2", 3) == 0)
    {
    {
      return (0 <= value && value <= 65535);
      return (0 <= value && value <= 65535);
    }
    }
  if (memcmp (str, "IU3", 3) == 0)
  if (memcmp (str, "IU3", 3) == 0)
    {
    {
      return (0 <= value && value <= 0x00ffffff);
      return (0 <= value && value <= 0x00ffffff);
    }
    }
  if (memcmp (str, "In4", 3) == 0)
  if (memcmp (str, "In4", 3) == 0)
    {
    {
      return (-8 <= value && value && value <= 8);
      return (-8 <= value && value && value <= 8);
    }
    }
  if (memcmp (str, "In5", 3) == 0)
  if (memcmp (str, "In5", 3) == 0)
    {
    {
      return (-16 <= value && value && value <= 16);
      return (-16 <= value && value && value <= 16);
    }
    }
  if (memcmp (str, "In6", 3) == 0)
  if (memcmp (str, "In6", 3) == 0)
    {
    {
      return (-32 <= value && value && value <= 32);
      return (-32 <= value && value && value <= 32);
    }
    }
  if (memcmp (str, "IM2", 3) == 0)
  if (memcmp (str, "IM2", 3) == 0)
    {
    {
      return (-65536 <= value && value && value <= -1);
      return (-65536 <= value && value && value <= -1);
    }
    }
  if (memcmp (str, "Ilb", 3) == 0)
  if (memcmp (str, "Ilb", 3) == 0)
    {
    {
      int b = exact_log2 (value);
      int b = exact_log2 (value);
      return (b >= 0 && b <= 7);
      return (b >= 0 && b <= 7);
    }
    }
  if (memcmp (str, "Imb", 3) == 0)
  if (memcmp (str, "Imb", 3) == 0)
    {
    {
      int b = exact_log2 ((value ^ 0xff) & 0xff);
      int b = exact_log2 ((value ^ 0xff) & 0xff);
      return (b >= 0 && b <= 7);
      return (b >= 0 && b <= 7);
    }
    }
  if (memcmp (str, "ImB", 3) == 0)
  if (memcmp (str, "ImB", 3) == 0)
    {
    {
      int b = exact_log2 ((value ^ 0xffff) & 0xffff);
      int b = exact_log2 ((value ^ 0xffff) & 0xffff);
      return (b >= 0 && b <= 7);
      return (b >= 0 && b <= 7);
    }
    }
  if (memcmp (str, "Ilw", 3) == 0)
  if (memcmp (str, "Ilw", 3) == 0)
    {
    {
      int b = exact_log2 (value);
      int b = exact_log2 (value);
      return (b >= 0 && b <= 15);
      return (b >= 0 && b <= 15);
    }
    }
  if (memcmp (str, "Imw", 3) == 0)
  if (memcmp (str, "Imw", 3) == 0)
    {
    {
      int b = exact_log2 ((value ^ 0xffff) & 0xffff);
      int b = exact_log2 ((value ^ 0xffff) & 0xffff);
      return (b >= 0 && b <= 15);
      return (b >= 0 && b <= 15);
    }
    }
  if (memcmp (str, "I00", 3) == 0)
  if (memcmp (str, "I00", 3) == 0)
    {
    {
      return (value == 0);
      return (value == 0);
    }
    }
  return 0;
  return 0;
}
}
 
 
/* Implements EXTRA_CONSTRAINT_STR (see next function too).  'S' is
/* Implements EXTRA_CONSTRAINT_STR (see next function too).  'S' is
   for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
   for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
   call return values.  */
   call return values.  */
int
int
m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
{
{
  encode_pattern (value);
  encode_pattern (value);
  if (memcmp (str, "Sd", 2) == 0)
  if (memcmp (str, "Sd", 2) == 0)
    {
    {
      /* This is the common "src/dest" address */
      /* This is the common "src/dest" address */
      rtx r;
      rtx r;
      if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
      if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
        return 1;
        return 1;
      if (RTX_IS ("ms") || RTX_IS ("m+si"))
      if (RTX_IS ("ms") || RTX_IS ("m+si"))
        return 1;
        return 1;
      if (RTX_IS ("m++rii"))
      if (RTX_IS ("m++rii"))
        {
        {
          if (REGNO (patternr[3]) == FB_REGNO
          if (REGNO (patternr[3]) == FB_REGNO
              && INTVAL (patternr[4]) == 0)
              && INTVAL (patternr[4]) == 0)
            return 1;
            return 1;
        }
        }
      if (RTX_IS ("mr"))
      if (RTX_IS ("mr"))
        r = patternr[1];
        r = patternr[1];
      else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
      else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
        r = patternr[2];
        r = patternr[2];
      else
      else
        return 0;
        return 0;
      if (REGNO (r) == SP_REGNO)
      if (REGNO (r) == SP_REGNO)
        return 0;
        return 0;
      return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
      return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
    }
    }
  else if (memcmp (str, "Sa", 2) == 0)
  else if (memcmp (str, "Sa", 2) == 0)
    {
    {
      rtx r;
      rtx r;
      if (RTX_IS ("mr"))
      if (RTX_IS ("mr"))
        r = patternr[1];
        r = patternr[1];
      else if (RTX_IS ("m+ri"))
      else if (RTX_IS ("m+ri"))
        r = patternr[2];
        r = patternr[2];
      else
      else
        return 0;
        return 0;
      return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
      return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
    }
    }
  else if (memcmp (str, "Si", 2) == 0)
  else if (memcmp (str, "Si", 2) == 0)
    {
    {
      return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
      return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
    }
    }
  else if (memcmp (str, "Ss", 2) == 0)
  else if (memcmp (str, "Ss", 2) == 0)
    {
    {
      return ((RTX_IS ("mr")
      return ((RTX_IS ("mr")
               && (IS_REG (patternr[1], SP_REGNO)))
               && (IS_REG (patternr[1], SP_REGNO)))
              || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
              || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
    }
    }
  else if (memcmp (str, "Sf", 2) == 0)
  else if (memcmp (str, "Sf", 2) == 0)
    {
    {
      return ((RTX_IS ("mr")
      return ((RTX_IS ("mr")
               && (IS_REG (patternr[1], FB_REGNO)))
               && (IS_REG (patternr[1], FB_REGNO)))
              || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
              || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
    }
    }
  else if (memcmp (str, "Sb", 2) == 0)
  else if (memcmp (str, "Sb", 2) == 0)
    {
    {
      return ((RTX_IS ("mr")
      return ((RTX_IS ("mr")
               && (IS_REG (patternr[1], SB_REGNO)))
               && (IS_REG (patternr[1], SB_REGNO)))
              || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
              || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
    }
    }
  else if (memcmp (str, "Sp", 2) == 0)
  else if (memcmp (str, "Sp", 2) == 0)
    {
    {
      /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
      /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
      return (RTX_IS ("mi")
      return (RTX_IS ("mi")
              && !(INTVAL (patternr[1]) & ~0x1fff));
              && !(INTVAL (patternr[1]) & ~0x1fff));
    }
    }
  else if (memcmp (str, "S1", 2) == 0)
  else if (memcmp (str, "S1", 2) == 0)
    {
    {
      return r1h_operand (value, QImode);
      return r1h_operand (value, QImode);
    }
    }
 
 
  gcc_assert (str[0] != 'S');
  gcc_assert (str[0] != 'S');
 
 
  if (memcmp (str, "Rpa", 2) == 0)
  if (memcmp (str, "Rpa", 2) == 0)
    return GET_CODE (value) == PARALLEL;
    return GET_CODE (value) == PARALLEL;
 
 
  return 0;
  return 0;
}
}
 
 
/* This is for when we're debugging the above.  */
/* This is for when we're debugging the above.  */
int
int
m32c_extra_constraint_p (rtx value, char c, const char *str)
m32c_extra_constraint_p (rtx value, char c, const char *str)
{
{
  int rv = m32c_extra_constraint_p2 (value, c, str);
  int rv = m32c_extra_constraint_p2 (value, c, str);
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
  fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
           rv);
           rv);
  debug_rtx (value);
  debug_rtx (value);
#endif
#endif
  return rv;
  return rv;
}
}
 
 
/* Implements EXTRA_MEMORY_CONSTRAINT.  Currently, we only use strings
/* Implements EXTRA_MEMORY_CONSTRAINT.  Currently, we only use strings
   starting with 'S'.  */
   starting with 'S'.  */
int
int
m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
{
{
  return c == 'S';
  return c == 'S';
}
}
 
 
/* Implements EXTRA_ADDRESS_CONSTRAINT.  We reserve 'A' strings for these,
/* Implements EXTRA_ADDRESS_CONSTRAINT.  We reserve 'A' strings for these,
   but don't currently define any.  */
   but don't currently define any.  */
int
int
m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
{
{
  return c == 'A';
  return c == 'A';
}
}
 
 
/* STACK AND CALLING */
/* STACK AND CALLING */
 
 
/* Frame Layout */
/* Frame Layout */
 
 
/* Implements RETURN_ADDR_RTX.  Note that R8C and M16C push 24 bits
/* Implements RETURN_ADDR_RTX.  Note that R8C and M16C push 24 bits
   (yes, THREE bytes) onto the stack for the return address, but we
   (yes, THREE bytes) onto the stack for the return address, but we
   don't support pointers bigger than 16 bits on those chips.  This
   don't support pointers bigger than 16 bits on those chips.  This
   will likely wreak havoc with exception unwinding.  FIXME.  */
   will likely wreak havoc with exception unwinding.  FIXME.  */
rtx
rtx
m32c_return_addr_rtx (int count)
m32c_return_addr_rtx (int count)
{
{
  enum machine_mode mode;
  enum machine_mode mode;
  int offset;
  int offset;
  rtx ra_mem;
  rtx ra_mem;
 
 
  if (count)
  if (count)
    return NULL_RTX;
    return NULL_RTX;
  /* we want 2[$fb] */
  /* we want 2[$fb] */
 
 
  if (TARGET_A24)
  if (TARGET_A24)
    {
    {
      /* It's four bytes */
      /* It's four bytes */
      mode = PSImode;
      mode = PSImode;
      offset = 4;
      offset = 4;
    }
    }
  else
  else
    {
    {
      /* FIXME: it's really 3 bytes */
      /* FIXME: it's really 3 bytes */
      mode = HImode;
      mode = HImode;
      offset = 2;
      offset = 2;
    }
    }
 
 
  ra_mem =
  ra_mem =
    gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
    gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
  return copy_to_mode_reg (mode, ra_mem);
  return copy_to_mode_reg (mode, ra_mem);
}
}
 
 
/* Implements INCOMING_RETURN_ADDR_RTX.  See comment above.  */
/* Implements INCOMING_RETURN_ADDR_RTX.  See comment above.  */
rtx
rtx
m32c_incoming_return_addr_rtx (void)
m32c_incoming_return_addr_rtx (void)
{
{
  /* we want [sp] */
  /* we want [sp] */
  return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
  return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
}
}
 
 
/* Exception Handling Support */
/* Exception Handling Support */
 
 
/* Implements EH_RETURN_DATA_REGNO.  Choose registers able to hold
/* Implements EH_RETURN_DATA_REGNO.  Choose registers able to hold
   pointers.  */
   pointers.  */
int
int
m32c_eh_return_data_regno (int n)
m32c_eh_return_data_regno (int n)
{
{
  switch (n)
  switch (n)
    {
    {
    case 0:
    case 0:
      return A0_REGNO;
      return A0_REGNO;
    case 1:
    case 1:
      if (TARGET_A16)
      if (TARGET_A16)
        return R3_REGNO;
        return R3_REGNO;
      else
      else
        return R1_REGNO;
        return R1_REGNO;
    default:
    default:
      return INVALID_REGNUM;
      return INVALID_REGNUM;
    }
    }
}
}
 
 
/* Implements EH_RETURN_STACKADJ_RTX.  Saved and used later in
/* Implements EH_RETURN_STACKADJ_RTX.  Saved and used later in
   m32c_emit_eh_epilogue.  */
   m32c_emit_eh_epilogue.  */
rtx
rtx
m32c_eh_return_stackadj_rtx (void)
m32c_eh_return_stackadj_rtx (void)
{
{
  if (!cfun->machine->eh_stack_adjust)
  if (!cfun->machine->eh_stack_adjust)
    {
    {
      rtx sa;
      rtx sa;
 
 
      sa = gen_rtx_REG (Pmode, R0_REGNO);
      sa = gen_rtx_REG (Pmode, R0_REGNO);
      cfun->machine->eh_stack_adjust = sa;
      cfun->machine->eh_stack_adjust = sa;
    }
    }
  return cfun->machine->eh_stack_adjust;
  return cfun->machine->eh_stack_adjust;
}
}
 
 
/* Registers That Address the Stack Frame */
/* Registers That Address the Stack Frame */
 
 
/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER.  Note that
/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER.  Note that
   the original spec called for dwarf numbers to vary with register
   the original spec called for dwarf numbers to vary with register
   width as well, for example, r0l, r0, and r2r0 would each have
   width as well, for example, r0l, r0, and r2r0 would each have
   different dwarf numbers.  GCC doesn't support this, and we don't do
   different dwarf numbers.  GCC doesn't support this, and we don't do
   it, and gdb seems to like it this way anyway.  */
   it, and gdb seems to like it this way anyway.  */
unsigned int
unsigned int
m32c_dwarf_frame_regnum (int n)
m32c_dwarf_frame_regnum (int n)
{
{
  switch (n)
  switch (n)
    {
    {
    case R0_REGNO:
    case R0_REGNO:
      return 5;
      return 5;
    case R1_REGNO:
    case R1_REGNO:
      return 6;
      return 6;
    case R2_REGNO:
    case R2_REGNO:
      return 7;
      return 7;
    case R3_REGNO:
    case R3_REGNO:
      return 8;
      return 8;
    case A0_REGNO:
    case A0_REGNO:
      return 9;
      return 9;
    case A1_REGNO:
    case A1_REGNO:
      return 10;
      return 10;
    case FB_REGNO:
    case FB_REGNO:
      return 11;
      return 11;
    case SB_REGNO:
    case SB_REGNO:
      return 19;
      return 19;
 
 
    case SP_REGNO:
    case SP_REGNO:
      return 12;
      return 12;
    case PC_REGNO:
    case PC_REGNO:
      return 13;
      return 13;
    default:
    default:
      return DWARF_FRAME_REGISTERS + 1;
      return DWARF_FRAME_REGISTERS + 1;
    }
    }
}
}
 
 
/* The frame looks like this:
/* The frame looks like this:
 
 
   ap -> +------------------------------
   ap -> +------------------------------
         | Return address (3 or 4 bytes)
         | Return address (3 or 4 bytes)
         | Saved FB (2 or 4 bytes)
         | Saved FB (2 or 4 bytes)
   fb -> +------------------------------
   fb -> +------------------------------
         | local vars
         | local vars
         | register saves fb
         | register saves fb
         |        through r0 as needed
         |        through r0 as needed
   sp -> +------------------------------
   sp -> +------------------------------
*/
*/
 
 
/* We use this to wrap all emitted insns in the prologue.  */
/* We use this to wrap all emitted insns in the prologue.  */
static rtx
static rtx
F (rtx x)
F (rtx x)
{
{
  RTX_FRAME_RELATED_P (x) = 1;
  RTX_FRAME_RELATED_P (x) = 1;
  return x;
  return x;
}
}
 
 
/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
   how much the stack pointer moves for each, for each cpu family.  */
   how much the stack pointer moves for each, for each cpu family.  */
static struct
static struct
{
{
  int reg1;
  int reg1;
  int bit;
  int bit;
  int a16_bytes;
  int a16_bytes;
  int a24_bytes;
  int a24_bytes;
} pushm_info[] =
} pushm_info[] =
{
{
  /* These are in reverse push (nearest-to-sp) order.  */
  /* These are in reverse push (nearest-to-sp) order.  */
  { R0_REGNO, 0x80, 2, 2 },
  { R0_REGNO, 0x80, 2, 2 },
  { R1_REGNO, 0x40, 2, 2 },
  { R1_REGNO, 0x40, 2, 2 },
  { R2_REGNO, 0x20, 2, 2 },
  { R2_REGNO, 0x20, 2, 2 },
  { R3_REGNO, 0x10, 2, 2 },
  { R3_REGNO, 0x10, 2, 2 },
  { A0_REGNO, 0x08, 2, 4 },
  { A0_REGNO, 0x08, 2, 4 },
  { A1_REGNO, 0x04, 2, 4 },
  { A1_REGNO, 0x04, 2, 4 },
  { SB_REGNO, 0x02, 2, 4 },
  { SB_REGNO, 0x02, 2, 4 },
  { FB_REGNO, 0x01, 2, 4 }
  { FB_REGNO, 0x01, 2, 4 }
};
};
 
 
#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
 
 
/* Returns TRUE if we need to save/restore the given register.  We
/* Returns TRUE if we need to save/restore the given register.  We
   save everything for exception handlers, so that any register can be
   save everything for exception handlers, so that any register can be
   unwound.  For interrupt handlers, we save everything if the handler
   unwound.  For interrupt handlers, we save everything if the handler
   calls something else (because we don't know what *that* function
   calls something else (because we don't know what *that* function
   might do), but try to be a bit smarter if the handler is a leaf
   might do), but try to be a bit smarter if the handler is a leaf
   function.  We always save $a0, though, because we use that in the
   function.  We always save $a0, though, because we use that in the
   epilogue to copy $fb to $sp.  */
   epilogue to copy $fb to $sp.  */
static int
static int
need_to_save (int regno)
need_to_save (int regno)
{
{
  if (fixed_regs[regno])
  if (fixed_regs[regno])
    return 0;
    return 0;
  if (crtl->calls_eh_return)
  if (crtl->calls_eh_return)
    return 1;
    return 1;
  if (regno == FP_REGNO)
  if (regno == FP_REGNO)
    return 0;
    return 0;
  if (cfun->machine->is_interrupt
  if (cfun->machine->is_interrupt
      && (!cfun->machine->is_leaf
      && (!cfun->machine->is_leaf
          || (regno == A0_REGNO
          || (regno == A0_REGNO
              && m32c_function_needs_enter ())
              && m32c_function_needs_enter ())
          ))
          ))
    return 1;
    return 1;
  if (df_regs_ever_live_p (regno)
  if (df_regs_ever_live_p (regno)
      && (!call_used_regs[regno] || cfun->machine->is_interrupt))
      && (!call_used_regs[regno] || cfun->machine->is_interrupt))
    return 1;
    return 1;
  return 0;
  return 0;
}
}
 
 
/* This function contains all the intelligence about saving and
/* This function contains all the intelligence about saving and
   restoring registers.  It always figures out the register save set.
   restoring registers.  It always figures out the register save set.
   When called with PP_justcount, it merely returns the size of the
   When called with PP_justcount, it merely returns the size of the
   save set (for eliminating the frame pointer, for example).  When
   save set (for eliminating the frame pointer, for example).  When
   called with PP_pushm or PP_popm, it emits the appropriate
   called with PP_pushm or PP_popm, it emits the appropriate
   instructions for saving (pushm) or restoring (popm) the
   instructions for saving (pushm) or restoring (popm) the
   registers.  */
   registers.  */
static int
static int
m32c_pushm_popm (Push_Pop_Type ppt)
m32c_pushm_popm (Push_Pop_Type ppt)
{
{
  int reg_mask = 0;
  int reg_mask = 0;
  int byte_count = 0, bytes;
  int byte_count = 0, bytes;
  int i;
  int i;
  rtx dwarf_set[PUSHM_N];
  rtx dwarf_set[PUSHM_N];
  int n_dwarfs = 0;
  int n_dwarfs = 0;
  int nosave_mask = 0;
  int nosave_mask = 0;
 
 
  if (crtl->return_rtx
  if (crtl->return_rtx
      && GET_CODE (crtl->return_rtx) == PARALLEL
      && GET_CODE (crtl->return_rtx) == PARALLEL
      && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
      && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
    {
    {
      rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
      rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
      rtx rv = XEXP (exp, 0);
      rtx rv = XEXP (exp, 0);
      int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
      int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
 
 
      if (rv_bytes > 2)
      if (rv_bytes > 2)
        nosave_mask |= 0x20;    /* PSI, SI */
        nosave_mask |= 0x20;    /* PSI, SI */
      else
      else
        nosave_mask |= 0xf0;    /* DF */
        nosave_mask |= 0xf0;    /* DF */
      if (rv_bytes > 4)
      if (rv_bytes > 4)
        nosave_mask |= 0x50;    /* DI */
        nosave_mask |= 0x50;    /* DI */
    }
    }
 
 
  for (i = 0; i < (int) PUSHM_N; i++)
  for (i = 0; i < (int) PUSHM_N; i++)
    {
    {
      /* Skip if neither register needs saving.  */
      /* Skip if neither register needs saving.  */
      if (!need_to_save (pushm_info[i].reg1))
      if (!need_to_save (pushm_info[i].reg1))
        continue;
        continue;
 
 
      if (pushm_info[i].bit & nosave_mask)
      if (pushm_info[i].bit & nosave_mask)
        continue;
        continue;
 
 
      reg_mask |= pushm_info[i].bit;
      reg_mask |= pushm_info[i].bit;
      bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
      bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
 
 
      if (ppt == PP_pushm)
      if (ppt == PP_pushm)
        {
        {
          enum machine_mode mode = (bytes == 2) ? HImode : SImode;
          enum machine_mode mode = (bytes == 2) ? HImode : SImode;
          rtx addr;
          rtx addr;
 
 
          /* Always use stack_pointer_rtx instead of calling
          /* Always use stack_pointer_rtx instead of calling
             rtx_gen_REG ourselves.  Code elsewhere in GCC assumes
             rtx_gen_REG ourselves.  Code elsewhere in GCC assumes
             that there is a single rtx representing the stack pointer,
             that there is a single rtx representing the stack pointer,
             namely stack_pointer_rtx, and uses == to recognize it.  */
             namely stack_pointer_rtx, and uses == to recognize it.  */
          addr = stack_pointer_rtx;
          addr = stack_pointer_rtx;
 
 
          if (byte_count != 0)
          if (byte_count != 0)
            addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
            addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
 
 
          dwarf_set[n_dwarfs++] =
          dwarf_set[n_dwarfs++] =
            gen_rtx_SET (VOIDmode,
            gen_rtx_SET (VOIDmode,
                         gen_rtx_MEM (mode, addr),
                         gen_rtx_MEM (mode, addr),
                         gen_rtx_REG (mode, pushm_info[i].reg1));
                         gen_rtx_REG (mode, pushm_info[i].reg1));
          F (dwarf_set[n_dwarfs - 1]);
          F (dwarf_set[n_dwarfs - 1]);
 
 
        }
        }
      byte_count += bytes;
      byte_count += bytes;
    }
    }
 
 
  if (cfun->machine->is_interrupt)
  if (cfun->machine->is_interrupt)
    {
    {
      cfun->machine->intr_pushm = reg_mask & 0xfe;
      cfun->machine->intr_pushm = reg_mask & 0xfe;
      reg_mask = 0;
      reg_mask = 0;
      byte_count = 0;
      byte_count = 0;
    }
    }
 
 
  if (cfun->machine->is_interrupt)
  if (cfun->machine->is_interrupt)
    for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
    for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
      if (need_to_save (i))
      if (need_to_save (i))
        {
        {
          byte_count += 2;
          byte_count += 2;
          cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
          cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
        }
        }
 
 
  if (ppt == PP_pushm && byte_count)
  if (ppt == PP_pushm && byte_count)
    {
    {
      rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
      rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
      rtx pushm;
      rtx pushm;
 
 
      if (reg_mask)
      if (reg_mask)
        {
        {
          XVECEXP (note, 0, 0)
          XVECEXP (note, 0, 0)
            = gen_rtx_SET (VOIDmode,
            = gen_rtx_SET (VOIDmode,
                           stack_pointer_rtx,
                           stack_pointer_rtx,
                           gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
                           gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
                                         stack_pointer_rtx,
                                         stack_pointer_rtx,
                                         GEN_INT (-byte_count)));
                                         GEN_INT (-byte_count)));
          F (XVECEXP (note, 0, 0));
          F (XVECEXP (note, 0, 0));
 
 
          for (i = 0; i < n_dwarfs; i++)
          for (i = 0; i < n_dwarfs; i++)
            XVECEXP (note, 0, i + 1) = dwarf_set[i];
            XVECEXP (note, 0, i + 1) = dwarf_set[i];
 
 
          pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
          pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
 
 
          REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
          REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
                                                 REG_NOTES (pushm));
                                                 REG_NOTES (pushm));
        }
        }
 
 
      if (cfun->machine->is_interrupt)
      if (cfun->machine->is_interrupt)
        for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
        for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
          if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
          if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
            {
            {
              if (TARGET_A16)
              if (TARGET_A16)
                pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
                pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
              else
              else
                pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
                pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
              F (pushm);
              F (pushm);
            }
            }
    }
    }
  if (ppt == PP_popm && byte_count)
  if (ppt == PP_popm && byte_count)
    {
    {
      if (cfun->machine->is_interrupt)
      if (cfun->machine->is_interrupt)
        for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
        for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
          if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
          if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
            {
            {
              if (TARGET_A16)
              if (TARGET_A16)
                emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
                emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
              else
              else
                emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
                emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
            }
            }
      if (reg_mask)
      if (reg_mask)
        emit_insn (gen_popm (GEN_INT (reg_mask)));
        emit_insn (gen_popm (GEN_INT (reg_mask)));
    }
    }
 
 
  return byte_count;
  return byte_count;
}
}
 
 
/* Implements INITIAL_ELIMINATION_OFFSET.  See the comment above that
/* Implements INITIAL_ELIMINATION_OFFSET.  See the comment above that
   diagrams our call frame.  */
   diagrams our call frame.  */
int
int
m32c_initial_elimination_offset (int from, int to)
m32c_initial_elimination_offset (int from, int to)
{
{
  int ofs = 0;
  int ofs = 0;
 
 
  if (from == AP_REGNO)
  if (from == AP_REGNO)
    {
    {
      if (TARGET_A16)
      if (TARGET_A16)
        ofs += 5;
        ofs += 5;
      else
      else
        ofs += 8;
        ofs += 8;
    }
    }
 
 
  if (to == SP_REGNO)
  if (to == SP_REGNO)
    {
    {
      ofs += m32c_pushm_popm (PP_justcount);
      ofs += m32c_pushm_popm (PP_justcount);
      ofs += get_frame_size ();
      ofs += get_frame_size ();
    }
    }
 
 
  /* Account for push rounding.  */
  /* Account for push rounding.  */
  if (TARGET_A24)
  if (TARGET_A24)
    ofs = (ofs + 1) & ~1;
    ofs = (ofs + 1) & ~1;
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
  fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
           to, ofs);
           to, ofs);
#endif
#endif
  return ofs;
  return ofs;
}
}
 
 
/* Passing Function Arguments on the Stack */
/* Passing Function Arguments on the Stack */
 
 
/* Implements PUSH_ROUNDING.  The R8C and M16C have byte stacks, the
/* Implements PUSH_ROUNDING.  The R8C and M16C have byte stacks, the
   M32C has word stacks.  */
   M32C has word stacks.  */
int
int
m32c_push_rounding (int n)
m32c_push_rounding (int n)
{
{
  if (TARGET_R8C || TARGET_M16C)
  if (TARGET_R8C || TARGET_M16C)
    return n;
    return n;
  return (n + 1) & ~1;
  return (n + 1) & ~1;
}
}
 
 
/* Passing Arguments in Registers */
/* Passing Arguments in Registers */
 
 
/* Implements FUNCTION_ARG.  Arguments are passed partly in registers,
/* Implements FUNCTION_ARG.  Arguments are passed partly in registers,
   partly on stack.  If our function returns a struct, a pointer to a
   partly on stack.  If our function returns a struct, a pointer to a
   buffer for it is at the top of the stack (last thing pushed).  The
   buffer for it is at the top of the stack (last thing pushed).  The
   first few real arguments may be in registers as follows:
   first few real arguments may be in registers as follows:
 
 
   R8C/M16C:    arg1 in r1 if it's QI or HI (else it's pushed on stack)
   R8C/M16C:    arg1 in r1 if it's QI or HI (else it's pushed on stack)
                arg2 in r2 if it's HI (else pushed on stack)
                arg2 in r2 if it's HI (else pushed on stack)
                rest on stack
                rest on stack
   M32C:        arg1 in r0 if it's QI or HI (else it's pushed on stack)
   M32C:        arg1 in r0 if it's QI or HI (else it's pushed on stack)
                rest on stack
                rest on stack
 
 
   Structs are not passed in registers, even if they fit.  Only
   Structs are not passed in registers, even if they fit.  Only
   integer and pointer types are passed in registers.
   integer and pointer types are passed in registers.
 
 
   Note that when arg1 doesn't fit in r1, arg2 may still be passed in
   Note that when arg1 doesn't fit in r1, arg2 may still be passed in
   r2 if it fits.  */
   r2 if it fits.  */
rtx
rtx
m32c_function_arg (CUMULATIVE_ARGS * ca,
m32c_function_arg (CUMULATIVE_ARGS * ca,
                   enum machine_mode mode, tree type, int named)
                   enum machine_mode mode, tree type, int named)
{
{
  /* Can return a reg, parallel, or 0 for stack */
  /* Can return a reg, parallel, or 0 for stack */
  rtx rv = NULL_RTX;
  rtx rv = NULL_RTX;
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "func_arg %d (%s, %d)\n",
  fprintf (stderr, "func_arg %d (%s, %d)\n",
           ca->parm_num, mode_name[mode], named);
           ca->parm_num, mode_name[mode], named);
  debug_tree (type);
  debug_tree (type);
#endif
#endif
 
 
  if (mode == VOIDmode)
  if (mode == VOIDmode)
    return GEN_INT (0);
    return GEN_INT (0);
 
 
  if (ca->force_mem || !named)
  if (ca->force_mem || !named)
    {
    {
#if DEBUG0
#if DEBUG0
      fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
      fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
               named);
               named);
#endif
#endif
      return NULL_RTX;
      return NULL_RTX;
    }
    }
 
 
  if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
  if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
    return NULL_RTX;
    return NULL_RTX;
 
 
  if (type && AGGREGATE_TYPE_P (type))
  if (type && AGGREGATE_TYPE_P (type))
    return NULL_RTX;
    return NULL_RTX;
 
 
  switch (ca->parm_num)
  switch (ca->parm_num)
    {
    {
    case 1:
    case 1:
      if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
      if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
        rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
        rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
      break;
      break;
 
 
    case 2:
    case 2:
      if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
      if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
        rv = gen_rtx_REG (mode, R2_REGNO);
        rv = gen_rtx_REG (mode, R2_REGNO);
      break;
      break;
    }
    }
 
 
#if DEBUG0
#if DEBUG0
  debug_rtx (rv);
  debug_rtx (rv);
#endif
#endif
  return rv;
  return rv;
}
}
 
 
#undef TARGET_PASS_BY_REFERENCE
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
static bool
static bool
m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
                        enum machine_mode mode ATTRIBUTE_UNUSED,
                        enum machine_mode mode ATTRIBUTE_UNUSED,
                        const_tree type ATTRIBUTE_UNUSED,
                        const_tree type ATTRIBUTE_UNUSED,
                        bool named ATTRIBUTE_UNUSED)
                        bool named ATTRIBUTE_UNUSED)
{
{
  return 0;
  return 0;
}
}
 
 
/* Implements INIT_CUMULATIVE_ARGS.  */
/* Implements INIT_CUMULATIVE_ARGS.  */
void
void
m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
                           tree fntype,
                           tree fntype,
                           rtx libname ATTRIBUTE_UNUSED,
                           rtx libname ATTRIBUTE_UNUSED,
                           tree fndecl,
                           tree fndecl,
                           int n_named_args ATTRIBUTE_UNUSED)
                           int n_named_args ATTRIBUTE_UNUSED)
{
{
  if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
  if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
    ca->force_mem = 1;
    ca->force_mem = 1;
  else
  else
    ca->force_mem = 0;
    ca->force_mem = 0;
  ca->parm_num = 1;
  ca->parm_num = 1;
}
}
 
 
/* Implements FUNCTION_ARG_ADVANCE.  force_mem is set for functions
/* Implements FUNCTION_ARG_ADVANCE.  force_mem is set for functions
   returning structures, so we always reset that.  Otherwise, we only
   returning structures, so we always reset that.  Otherwise, we only
   need to know the sequence number of the argument to know what to do
   need to know the sequence number of the argument to know what to do
   with it.  */
   with it.  */
void
void
m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
                           enum machine_mode mode ATTRIBUTE_UNUSED,
                           enum machine_mode mode ATTRIBUTE_UNUSED,
                           tree type ATTRIBUTE_UNUSED,
                           tree type ATTRIBUTE_UNUSED,
                           int named ATTRIBUTE_UNUSED)
                           int named ATTRIBUTE_UNUSED)
{
{
  if (ca->force_mem)
  if (ca->force_mem)
    ca->force_mem = 0;
    ca->force_mem = 0;
  else
  else
    ca->parm_num++;
    ca->parm_num++;
}
}
 
 
/* Implements FUNCTION_ARG_REGNO_P.  */
/* Implements FUNCTION_ARG_REGNO_P.  */
int
int
m32c_function_arg_regno_p (int r)
m32c_function_arg_regno_p (int r)
{
{
  if (TARGET_A24)
  if (TARGET_A24)
    return (r == R0_REGNO);
    return (r == R0_REGNO);
  return (r == R1_REGNO || r == R2_REGNO);
  return (r == R1_REGNO || r == R2_REGNO);
}
}
 
 
/* HImode and PSImode are the two "native" modes as far as GCC is
/* HImode and PSImode are the two "native" modes as far as GCC is
   concerned, but the chips also support a 32-bit mode which is used
   concerned, but the chips also support a 32-bit mode which is used
   for some opcodes in R8C/M16C and for reset vectors and such.  */
   for some opcodes in R8C/M16C and for reset vectors and such.  */
#undef TARGET_VALID_POINTER_MODE
#undef TARGET_VALID_POINTER_MODE
#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
static bool
static bool
m32c_valid_pointer_mode (enum machine_mode mode)
m32c_valid_pointer_mode (enum machine_mode mode)
{
{
  if (mode == HImode
  if (mode == HImode
      || mode == PSImode
      || mode == PSImode
      || mode == SImode
      || mode == SImode
      )
      )
    return 1;
    return 1;
  return 0;
  return 0;
}
}
 
 
/* How Scalar Function Values Are Returned */
/* How Scalar Function Values Are Returned */
 
 
/* Implements TARGET_LIBCALL_VALUE.  Most values are returned in $r0, or some
/* Implements TARGET_LIBCALL_VALUE.  Most values are returned in $r0, or some
   combination of registers starting there (r2r0 for longs, r3r1r2r0
   combination of registers starting there (r2r0 for longs, r3r1r2r0
   for long long, r3r2r1r0 for doubles), except that that ABI
   for long long, r3r2r1r0 for doubles), except that that ABI
   currently doesn't work because it ends up using all available
   currently doesn't work because it ends up using all available
   general registers and gcc often can't compile it.  So, instead, we
   general registers and gcc often can't compile it.  So, instead, we
   return anything bigger than 16 bits in "mem0" (effectively, a
   return anything bigger than 16 bits in "mem0" (effectively, a
   memory location).  */
   memory location).  */
 
 
#undef TARGET_LIBCALL_VALUE
#undef TARGET_LIBCALL_VALUE
#define TARGET_LIBCALL_VALUE m32c_libcall_value
#define TARGET_LIBCALL_VALUE m32c_libcall_value
 
 
static rtx
static rtx
m32c_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
m32c_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
{
{
  /* return reg or parallel */
  /* return reg or parallel */
#if 0
#if 0
  /* FIXME: GCC has difficulty returning large values in registers,
  /* FIXME: GCC has difficulty returning large values in registers,
     because that ties up most of the general registers and gives the
     because that ties up most of the general registers and gives the
     register allocator little to work with.  Until we can resolve
     register allocator little to work with.  Until we can resolve
     this, large values are returned in memory.  */
     this, large values are returned in memory.  */
  if (mode == DFmode)
  if (mode == DFmode)
    {
    {
      rtx rv;
      rtx rv;
 
 
      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
                                              gen_rtx_REG (HImode,
                                              gen_rtx_REG (HImode,
                                                           R0_REGNO),
                                                           R0_REGNO),
                                              GEN_INT (0));
                                              GEN_INT (0));
      XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
      XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
                                              gen_rtx_REG (HImode,
                                              gen_rtx_REG (HImode,
                                                           R1_REGNO),
                                                           R1_REGNO),
                                              GEN_INT (2));
                                              GEN_INT (2));
      XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
      XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
                                              gen_rtx_REG (HImode,
                                              gen_rtx_REG (HImode,
                                                           R2_REGNO),
                                                           R2_REGNO),
                                              GEN_INT (4));
                                              GEN_INT (4));
      XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
      XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
                                              gen_rtx_REG (HImode,
                                              gen_rtx_REG (HImode,
                                                           R3_REGNO),
                                                           R3_REGNO),
                                              GEN_INT (6));
                                              GEN_INT (6));
      return rv;
      return rv;
    }
    }
 
 
  if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
  if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
    {
    {
      rtx rv;
      rtx rv;
 
 
      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
      rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
      XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
                                              gen_rtx_REG (mode,
                                              gen_rtx_REG (mode,
                                                           R0_REGNO),
                                                           R0_REGNO),
                                              GEN_INT (0));
                                              GEN_INT (0));
      return rv;
      return rv;
    }
    }
#endif
#endif
 
 
  if (GET_MODE_SIZE (mode) > 2)
  if (GET_MODE_SIZE (mode) > 2)
    return gen_rtx_REG (mode, MEM0_REGNO);
    return gen_rtx_REG (mode, MEM0_REGNO);
  return gen_rtx_REG (mode, R0_REGNO);
  return gen_rtx_REG (mode, R0_REGNO);
}
}
 
 
/* Implements TARGET_FUNCTION_VALUE.  Functions and libcalls have the same
/* Implements TARGET_FUNCTION_VALUE.  Functions and libcalls have the same
   conventions.  */
   conventions.  */
 
 
#undef TARGET_FUNCTION_VALUE
#undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE m32c_function_value
#define TARGET_FUNCTION_VALUE m32c_function_value
 
 
static rtx
static rtx
m32c_function_value (const_tree valtype,
m32c_function_value (const_tree valtype,
                     const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
                     const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
                     bool outgoing ATTRIBUTE_UNUSED)
                     bool outgoing ATTRIBUTE_UNUSED)
{
{
  /* return reg or parallel */
  /* return reg or parallel */
  const enum machine_mode mode = TYPE_MODE (valtype);
  const enum machine_mode mode = TYPE_MODE (valtype);
  return m32c_libcall_value (mode, NULL_RTX);
  return m32c_libcall_value (mode, NULL_RTX);
}
}
 
 
/* Implements FUNCTION_VALUE_REGNO_P.  */
/* Implements FUNCTION_VALUE_REGNO_P.  */
 
 
bool
bool
m32c_function_value_regno_p (const unsigned int regno)
m32c_function_value_regno_p (const unsigned int regno)
{
{
  return (regno == R0_REGNO || regno == MEM0_REGNO);
  return (regno == R0_REGNO || regno == MEM0_REGNO);
}
}
 
 
/* How Large Values Are Returned */
/* How Large Values Are Returned */
 
 
/* We return structures by pushing the address on the stack, even if
/* We return structures by pushing the address on the stack, even if
   we use registers for the first few "real" arguments.  */
   we use registers for the first few "real" arguments.  */
#undef TARGET_STRUCT_VALUE_RTX
#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
static rtx
static rtx
m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
                       int incoming ATTRIBUTE_UNUSED)
                       int incoming ATTRIBUTE_UNUSED)
{
{
  return 0;
  return 0;
}
}
 
 
/* Function Entry and Exit */
/* Function Entry and Exit */
 
 
/* Implements EPILOGUE_USES.  Interrupts restore all registers.  */
/* Implements EPILOGUE_USES.  Interrupts restore all registers.  */
int
int
m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
{
{
  if (cfun->machine->is_interrupt)
  if (cfun->machine->is_interrupt)
    return 1;
    return 1;
  return 0;
  return 0;
}
}
 
 
/* Implementing the Varargs Macros */
/* Implementing the Varargs Macros */
 
 
#undef TARGET_STRICT_ARGUMENT_NAMING
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
static bool
static bool
m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
{
{
  return 1;
  return 1;
}
}
 
 
/* Trampolines for Nested Functions */
/* Trampolines for Nested Functions */
 
 
/*
/*
   m16c:
   m16c:
   1 0000 75C43412              mov.w   #0x1234,a0
   1 0000 75C43412              mov.w   #0x1234,a0
   2 0004 FC000000              jmp.a   label
   2 0004 FC000000              jmp.a   label
 
 
   m32c:
   m32c:
   1 0000 BC563412              mov.l:s #0x123456,a0
   1 0000 BC563412              mov.l:s #0x123456,a0
   2 0004 CC000000              jmp.a   label
   2 0004 CC000000              jmp.a   label
*/
*/
 
 
/* Implements TRAMPOLINE_SIZE.  */
/* Implements TRAMPOLINE_SIZE.  */
int
int
m32c_trampoline_size (void)
m32c_trampoline_size (void)
{
{
  /* Allocate extra space so we can avoid the messy shifts when we
  /* Allocate extra space so we can avoid the messy shifts when we
     initialize the trampoline; we just write past the end of the
     initialize the trampoline; we just write past the end of the
     opcode.  */
     opcode.  */
  return TARGET_A16 ? 8 : 10;
  return TARGET_A16 ? 8 : 10;
}
}
 
 
/* Implements TRAMPOLINE_ALIGNMENT.  */
/* Implements TRAMPOLINE_ALIGNMENT.  */
int
int
m32c_trampoline_alignment (void)
m32c_trampoline_alignment (void)
{
{
  return 2;
  return 2;
}
}
 
 
/* Implements TARGET_TRAMPOLINE_INIT.  */
/* Implements TARGET_TRAMPOLINE_INIT.  */
 
 
#undef TARGET_TRAMPOLINE_INIT
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
static void
static void
m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
{
{
  rtx function = XEXP (DECL_RTL (fndecl), 0);
  rtx function = XEXP (DECL_RTL (fndecl), 0);
 
 
#define A0(m,i) adjust_address (m_tramp, m, i)
#define A0(m,i) adjust_address (m_tramp, m, i)
  if (TARGET_A16)
  if (TARGET_A16)
    {
    {
      /* Note: we subtract a "word" because the moves want signed
      /* Note: we subtract a "word" because the moves want signed
         constants, not unsigned constants.  */
         constants, not unsigned constants.  */
      emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
      emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
      emit_move_insn (A0 (HImode, 2), chainval);
      emit_move_insn (A0 (HImode, 2), chainval);
      emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
      emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
      /* We use 16-bit addresses here, but store the zero to turn it
      /* We use 16-bit addresses here, but store the zero to turn it
         into a 24-bit offset.  */
         into a 24-bit offset.  */
      emit_move_insn (A0 (HImode, 5), function);
      emit_move_insn (A0 (HImode, 5), function);
      emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
      emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
    }
    }
  else
  else
    {
    {
      /* Note that the PSI moves actually write 4 bytes.  Make sure we
      /* Note that the PSI moves actually write 4 bytes.  Make sure we
         write stuff out in the right order, and leave room for the
         write stuff out in the right order, and leave room for the
         extra byte at the end.  */
         extra byte at the end.  */
      emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
      emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
      emit_move_insn (A0 (PSImode, 1), chainval);
      emit_move_insn (A0 (PSImode, 1), chainval);
      emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
      emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
      emit_move_insn (A0 (PSImode, 5), function);
      emit_move_insn (A0 (PSImode, 5), function);
    }
    }
#undef A0
#undef A0
}
}
 
 
/* Implicit Calls to Library Routines */
/* Implicit Calls to Library Routines */
 
 
#undef TARGET_INIT_LIBFUNCS
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
static void
static void
m32c_init_libfuncs (void)
m32c_init_libfuncs (void)
{
{
  /* We do this because the M32C has an HImode operand, but the
  /* We do this because the M32C has an HImode operand, but the
     M16C has an 8-bit operand.  Since gcc looks at the match data
     M16C has an 8-bit operand.  Since gcc looks at the match data
     and not the expanded rtl, we have to reset the optab so that
     and not the expanded rtl, we have to reset the optab so that
     the right modes are found. */
     the right modes are found. */
  if (TARGET_A24)
  if (TARGET_A24)
    {
    {
      optab_handler (cstore_optab, QImode)->insn_code = CODE_FOR_cstoreqi4_24;
      optab_handler (cstore_optab, QImode)->insn_code = CODE_FOR_cstoreqi4_24;
      optab_handler (cstore_optab, HImode)->insn_code = CODE_FOR_cstorehi4_24;
      optab_handler (cstore_optab, HImode)->insn_code = CODE_FOR_cstorehi4_24;
      optab_handler (cstore_optab, PSImode)->insn_code = CODE_FOR_cstorepsi4_24;
      optab_handler (cstore_optab, PSImode)->insn_code = CODE_FOR_cstorepsi4_24;
    }
    }
}
}
 
 
/* Addressing Modes */
/* Addressing Modes */
 
 
/* The r8c/m32c family supports a wide range of non-orthogonal
/* The r8c/m32c family supports a wide range of non-orthogonal
   addressing modes, including the ability to double-indirect on *some*
   addressing modes, including the ability to double-indirect on *some*
   of them.  Not all insns support all modes, either, but we rely on
   of them.  Not all insns support all modes, either, but we rely on
   predicates and constraints to deal with that.  */
   predicates and constraints to deal with that.  */
#undef TARGET_LEGITIMATE_ADDRESS_P
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
bool
bool
m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
{
{
  int mode_adjust;
  int mode_adjust;
  if (CONSTANT_P (x))
  if (CONSTANT_P (x))
    return 1;
    return 1;
 
 
  /* Wide references to memory will be split after reload, so we must
  /* Wide references to memory will be split after reload, so we must
     ensure that all parts of such splits remain legitimate
     ensure that all parts of such splits remain legitimate
     addresses.  */
     addresses.  */
  mode_adjust = GET_MODE_SIZE (mode) - 1;
  mode_adjust = GET_MODE_SIZE (mode) - 1;
 
 
  /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
  /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
  if (GET_CODE (x) == PRE_DEC
  if (GET_CODE (x) == PRE_DEC
      || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
      || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
    {
    {
      return (GET_CODE (XEXP (x, 0)) == REG
      return (GET_CODE (XEXP (x, 0)) == REG
              && REGNO (XEXP (x, 0)) == SP_REGNO);
              && REGNO (XEXP (x, 0)) == SP_REGNO);
    }
    }
 
 
#if 0
#if 0
  /* This is the double indirection detection, but it currently
  /* This is the double indirection detection, but it currently
     doesn't work as cleanly as this code implies, so until we've had
     doesn't work as cleanly as this code implies, so until we've had
     a chance to debug it, leave it disabled.  */
     a chance to debug it, leave it disabled.  */
  if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
  if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
    {
    {
#if DEBUG_DOUBLE
#if DEBUG_DOUBLE
      fprintf (stderr, "double indirect\n");
      fprintf (stderr, "double indirect\n");
#endif
#endif
      x = XEXP (x, 0);
      x = XEXP (x, 0);
    }
    }
#endif
#endif
 
 
  encode_pattern (x);
  encode_pattern (x);
  if (RTX_IS ("r"))
  if (RTX_IS ("r"))
    {
    {
      /* Most indexable registers can be used without displacements,
      /* Most indexable registers can be used without displacements,
         although some of them will be emitted with an explicit zero
         although some of them will be emitted with an explicit zero
         to please the assembler.  */
         to please the assembler.  */
      switch (REGNO (patternr[0]))
      switch (REGNO (patternr[0]))
        {
        {
        case A0_REGNO:
        case A0_REGNO:
        case A1_REGNO:
        case A1_REGNO:
        case SB_REGNO:
        case SB_REGNO:
        case FB_REGNO:
        case FB_REGNO:
        case SP_REGNO:
        case SP_REGNO:
          return 1;
          return 1;
 
 
        default:
        default:
          if (IS_PSEUDO (patternr[0], strict))
          if (IS_PSEUDO (patternr[0], strict))
            return 1;
            return 1;
          return 0;
          return 0;
        }
        }
    }
    }
  if (RTX_IS ("+ri"))
  if (RTX_IS ("+ri"))
    {
    {
      /* This is more interesting, because different base registers
      /* This is more interesting, because different base registers
         allow for different displacements - both range and signedness
         allow for different displacements - both range and signedness
         - and it differs from chip series to chip series too.  */
         - and it differs from chip series to chip series too.  */
      int rn = REGNO (patternr[1]);
      int rn = REGNO (patternr[1]);
      HOST_WIDE_INT offs = INTVAL (patternr[2]);
      HOST_WIDE_INT offs = INTVAL (patternr[2]);
      switch (rn)
      switch (rn)
        {
        {
        case A0_REGNO:
        case A0_REGNO:
        case A1_REGNO:
        case A1_REGNO:
        case SB_REGNO:
        case SB_REGNO:
          /* The syntax only allows positive offsets, but when the
          /* The syntax only allows positive offsets, but when the
             offsets span the entire memory range, we can simulate
             offsets span the entire memory range, we can simulate
             negative offsets by wrapping.  */
             negative offsets by wrapping.  */
          if (TARGET_A16)
          if (TARGET_A16)
            return (offs >= -65536 && offs <= 65535 - mode_adjust);
            return (offs >= -65536 && offs <= 65535 - mode_adjust);
          if (rn == SB_REGNO)
          if (rn == SB_REGNO)
            return (offs >= 0 && offs <= 65535 - mode_adjust);
            return (offs >= 0 && offs <= 65535 - mode_adjust);
          /* A0 or A1 */
          /* A0 or A1 */
          return (offs >= -16777216 && offs <= 16777215);
          return (offs >= -16777216 && offs <= 16777215);
 
 
        case FB_REGNO:
        case FB_REGNO:
          if (TARGET_A16)
          if (TARGET_A16)
            return (offs >= -128 && offs <= 127 - mode_adjust);
            return (offs >= -128 && offs <= 127 - mode_adjust);
          return (offs >= -65536 && offs <= 65535 - mode_adjust);
          return (offs >= -65536 && offs <= 65535 - mode_adjust);
 
 
        case SP_REGNO:
        case SP_REGNO:
          return (offs >= -128 && offs <= 127 - mode_adjust);
          return (offs >= -128 && offs <= 127 - mode_adjust);
 
 
        default:
        default:
          if (IS_PSEUDO (patternr[1], strict))
          if (IS_PSEUDO (patternr[1], strict))
            return 1;
            return 1;
          return 0;
          return 0;
        }
        }
    }
    }
  if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
  if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
    {
    {
      rtx reg = patternr[1];
      rtx reg = patternr[1];
 
 
      /* We don't know where the symbol is, so only allow base
      /* We don't know where the symbol is, so only allow base
         registers which support displacements spanning the whole
         registers which support displacements spanning the whole
         address range.  */
         address range.  */
      switch (REGNO (reg))
      switch (REGNO (reg))
        {
        {
        case A0_REGNO:
        case A0_REGNO:
        case A1_REGNO:
        case A1_REGNO:
          /* $sb needs a secondary reload, but since it's involved in
          /* $sb needs a secondary reload, but since it's involved in
             memory address reloads too, we don't deal with it very
             memory address reloads too, we don't deal with it very
             well.  */
             well.  */
          /*    case SB_REGNO: */
          /*    case SB_REGNO: */
          return 1;
          return 1;
        default:
        default:
          if (IS_PSEUDO (reg, strict))
          if (IS_PSEUDO (reg, strict))
            return 1;
            return 1;
          return 0;
          return 0;
        }
        }
    }
    }
  return 0;
  return 0;
}
}
 
 
/* Implements REG_OK_FOR_BASE_P.  */
/* Implements REG_OK_FOR_BASE_P.  */
int
int
m32c_reg_ok_for_base_p (rtx x, int strict)
m32c_reg_ok_for_base_p (rtx x, int strict)
{
{
  if (GET_CODE (x) != REG)
  if (GET_CODE (x) != REG)
    return 0;
    return 0;
  switch (REGNO (x))
  switch (REGNO (x))
    {
    {
    case A0_REGNO:
    case A0_REGNO:
    case A1_REGNO:
    case A1_REGNO:
    case SB_REGNO:
    case SB_REGNO:
    case FB_REGNO:
    case FB_REGNO:
    case SP_REGNO:
    case SP_REGNO:
      return 1;
      return 1;
    default:
    default:
      if (IS_PSEUDO (x, strict))
      if (IS_PSEUDO (x, strict))
        return 1;
        return 1;
      return 0;
      return 0;
    }
    }
}
}
 
 
/* We have three choices for choosing fb->aN offsets.  If we choose -128,
/* We have three choices for choosing fb->aN offsets.  If we choose -128,
   we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
   we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
   like this:
   like this:
       EB 4B FF    mova    -128[$fb],$a0
       EB 4B FF    mova    -128[$fb],$a0
       D8 0C FF FF mov.w:Q #0,-1[$a0]
       D8 0C FF FF mov.w:Q #0,-1[$a0]
 
 
   Alternately, we subtract the frame size, and hopefully use 8-bit aN
   Alternately, we subtract the frame size, and hopefully use 8-bit aN
   displacements:
   displacements:
       7B F4       stc $fb,$a0
       7B F4       stc $fb,$a0
       77 54 00 01 sub #256,$a0
       77 54 00 01 sub #256,$a0
       D8 08 01    mov.w:Q #0,1[$a0]
       D8 08 01    mov.w:Q #0,1[$a0]
 
 
   If we don't offset (i.e. offset by zero), we end up with:
   If we don't offset (i.e. offset by zero), we end up with:
       7B F4       stc $fb,$a0
       7B F4       stc $fb,$a0
       D8 0C 00 FF mov.w:Q #0,-256[$a0]
       D8 0C 00 FF mov.w:Q #0,-256[$a0]
 
 
   We have to subtract *something* so that we have a PLUS rtx to mark
   We have to subtract *something* so that we have a PLUS rtx to mark
   that we've done this reload.  The -128 offset will never result in
   that we've done this reload.  The -128 offset will never result in
   an 8-bit aN offset, and the payoff for the second case is five
   an 8-bit aN offset, and the payoff for the second case is five
   loads *if* those loads are within 256 bytes of the other end of the
   loads *if* those loads are within 256 bytes of the other end of the
   frame, so the third case seems best.  Note that we subtract the
   frame, so the third case seems best.  Note that we subtract the
   zero, but detect that in the addhi3 pattern.  */
   zero, but detect that in the addhi3 pattern.  */
 
 
#define BIG_FB_ADJ 0
#define BIG_FB_ADJ 0
 
 
/* Implements LEGITIMIZE_ADDRESS.  The only address we really have to
/* Implements LEGITIMIZE_ADDRESS.  The only address we really have to
   worry about is frame base offsets, as $fb has a limited
   worry about is frame base offsets, as $fb has a limited
   displacement range.  We deal with this by attempting to reload $fb
   displacement range.  We deal with this by attempting to reload $fb
   itself into an address register; that seems to result in the best
   itself into an address register; that seems to result in the best
   code.  */
   code.  */
#undef TARGET_LEGITIMIZE_ADDRESS
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
static rtx
static rtx
m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
                         enum machine_mode mode)
                         enum machine_mode mode)
{
{
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
  fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
  debug_rtx (x);
  debug_rtx (x);
  fprintf (stderr, "\n");
  fprintf (stderr, "\n");
#endif
#endif
 
 
  if (GET_CODE (x) == PLUS
  if (GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == REG
      && GET_CODE (XEXP (x, 0)) == REG
      && REGNO (XEXP (x, 0)) == FB_REGNO
      && REGNO (XEXP (x, 0)) == FB_REGNO
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && (INTVAL (XEXP (x, 1)) < -128
      && (INTVAL (XEXP (x, 1)) < -128
          || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
          || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
    {
    {
      /* reload FB to A_REGS */
      /* reload FB to A_REGS */
      rtx temp = gen_reg_rtx (Pmode);
      rtx temp = gen_reg_rtx (Pmode);
      x = copy_rtx (x);
      x = copy_rtx (x);
      emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (x, 0)));
      emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (x, 0)));
      XEXP (x, 0) = temp;
      XEXP (x, 0) = temp;
    }
    }
 
 
  return x;
  return x;
}
}
 
 
/* Implements LEGITIMIZE_RELOAD_ADDRESS.  See comment above.  */
/* Implements LEGITIMIZE_RELOAD_ADDRESS.  See comment above.  */
int
int
m32c_legitimize_reload_address (rtx * x,
m32c_legitimize_reload_address (rtx * x,
                                enum machine_mode mode,
                                enum machine_mode mode,
                                int opnum,
                                int opnum,
                                int type, int ind_levels ATTRIBUTE_UNUSED)
                                int type, int ind_levels ATTRIBUTE_UNUSED)
{
{
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
  fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
           mode_name[mode]);
           mode_name[mode]);
  debug_rtx (*x);
  debug_rtx (*x);
#endif
#endif
 
 
  /* At one point, this function tried to get $fb copied to an address
  /* At one point, this function tried to get $fb copied to an address
     register, which in theory would maximize sharing, but gcc was
     register, which in theory would maximize sharing, but gcc was
     *also* still trying to reload the whole address, and we'd run out
     *also* still trying to reload the whole address, and we'd run out
     of address registers.  So we let gcc do the naive (but safe)
     of address registers.  So we let gcc do the naive (but safe)
     reload instead, when the above function doesn't handle it for
     reload instead, when the above function doesn't handle it for
     us.
     us.
 
 
     The code below is a second attempt at the above.  */
     The code below is a second attempt at the above.  */
 
 
  if (GET_CODE (*x) == PLUS
  if (GET_CODE (*x) == PLUS
      && GET_CODE (XEXP (*x, 0)) == REG
      && GET_CODE (XEXP (*x, 0)) == REG
      && REGNO (XEXP (*x, 0)) == FB_REGNO
      && REGNO (XEXP (*x, 0)) == FB_REGNO
      && GET_CODE (XEXP (*x, 1)) == CONST_INT
      && GET_CODE (XEXP (*x, 1)) == CONST_INT
      && (INTVAL (XEXP (*x, 1)) < -128
      && (INTVAL (XEXP (*x, 1)) < -128
          || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
          || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
    {
    {
      rtx sum;
      rtx sum;
      int offset = INTVAL (XEXP (*x, 1));
      int offset = INTVAL (XEXP (*x, 1));
      int adjustment = -BIG_FB_ADJ;
      int adjustment = -BIG_FB_ADJ;
 
 
      sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
      sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
                          GEN_INT (adjustment));
                          GEN_INT (adjustment));
      *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
      *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
      if (type == RELOAD_OTHER)
      if (type == RELOAD_OTHER)
        type = RELOAD_FOR_OTHER_ADDRESS;
        type = RELOAD_FOR_OTHER_ADDRESS;
      push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
      push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
                   A_REGS, Pmode, VOIDmode, 0, 0, opnum,
                   A_REGS, Pmode, VOIDmode, 0, 0, opnum,
                   type);
                   type);
      return 1;
      return 1;
    }
    }
 
 
  if (GET_CODE (*x) == PLUS
  if (GET_CODE (*x) == PLUS
      && GET_CODE (XEXP (*x, 0)) == PLUS
      && GET_CODE (XEXP (*x, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
      && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
      && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
      && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
      && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
      && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
      && GET_CODE (XEXP (*x, 1)) == CONST_INT
      && GET_CODE (XEXP (*x, 1)) == CONST_INT
      )
      )
    {
    {
      if (type == RELOAD_OTHER)
      if (type == RELOAD_OTHER)
        type = RELOAD_FOR_OTHER_ADDRESS;
        type = RELOAD_FOR_OTHER_ADDRESS;
      push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
      push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
                   A_REGS, Pmode, VOIDmode, 0, 0, opnum,
                   A_REGS, Pmode, VOIDmode, 0, 0, opnum,
                   type);
                   type);
      return 1;
      return 1;
    }
    }
 
 
  return 0;
  return 0;
}
}
 
 
/* Implements LEGITIMATE_CONSTANT_P.  We split large constants anyway,
/* Implements LEGITIMATE_CONSTANT_P.  We split large constants anyway,
   so we can allow anything.  */
   so we can allow anything.  */
int
int
m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
{
{
  return 1;
  return 1;
}
}
 
 
 
 
/* Condition Code Status */
/* Condition Code Status */
 
 
#undef TARGET_FIXED_CONDITION_CODE_REGS
#undef TARGET_FIXED_CONDITION_CODE_REGS
#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
static bool
static bool
m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
{
{
  *p1 = FLG_REGNO;
  *p1 = FLG_REGNO;
  *p2 = INVALID_REGNUM;
  *p2 = INVALID_REGNUM;
  return true;
  return true;
}
}
 
 
/* Describing Relative Costs of Operations */
/* Describing Relative Costs of Operations */
 
 
/* Implements REGISTER_MOVE_COST.  We make impossible moves
/* Implements REGISTER_MOVE_COST.  We make impossible moves
   prohibitively expensive, like trying to put QIs in r2/r3 (there are
   prohibitively expensive, like trying to put QIs in r2/r3 (there are
   no opcodes to do that).  We also discourage use of mem* registers
   no opcodes to do that).  We also discourage use of mem* registers
   since they're really memory.  */
   since they're really memory.  */
int
int
m32c_register_move_cost (enum machine_mode mode, int from, int to)
m32c_register_move_cost (enum machine_mode mode, int from, int to)
{
{
  int cost = COSTS_N_INSNS (3);
  int cost = COSTS_N_INSNS (3);
  int cc = class_contents[from][0] | class_contents[to][0];
  int cc = class_contents[from][0] | class_contents[to][0];
  /* FIXME: pick real values, but not 2 for now.  */
  /* FIXME: pick real values, but not 2 for now.  */
  if (mode == QImode && (cc & class_contents[R23_REGS][0]))
  if (mode == QImode && (cc & class_contents[R23_REGS][0]))
    {
    {
      if (!(cc & ~class_contents[R23_REGS][0]))
      if (!(cc & ~class_contents[R23_REGS][0]))
        cost = COSTS_N_INSNS (1000);
        cost = COSTS_N_INSNS (1000);
      else
      else
        cost = COSTS_N_INSNS (80);
        cost = COSTS_N_INSNS (80);
    }
    }
 
 
  if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
  if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
    cost = COSTS_N_INSNS (1000);
    cost = COSTS_N_INSNS (1000);
 
 
  if (classes_intersect (from, CR_REGS))
  if (classes_intersect (from, CR_REGS))
    cost += COSTS_N_INSNS (5);
    cost += COSTS_N_INSNS (5);
 
 
  if (classes_intersect (to, CR_REGS))
  if (classes_intersect (to, CR_REGS))
    cost += COSTS_N_INSNS (5);
    cost += COSTS_N_INSNS (5);
 
 
  if (from == MEM_REGS || to == MEM_REGS)
  if (from == MEM_REGS || to == MEM_REGS)
    cost += COSTS_N_INSNS (50);
    cost += COSTS_N_INSNS (50);
  else if (classes_intersect (from, MEM_REGS)
  else if (classes_intersect (from, MEM_REGS)
           || classes_intersect (to, MEM_REGS))
           || classes_intersect (to, MEM_REGS))
    cost += COSTS_N_INSNS (10);
    cost += COSTS_N_INSNS (10);
 
 
#if DEBUG0
#if DEBUG0
  fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
  fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
           mode_name[mode], class_names[from], class_names[to], cost);
           mode_name[mode], class_names[from], class_names[to], cost);
#endif
#endif
  return cost;
  return cost;
}
}
 
 
/*  Implements MEMORY_MOVE_COST.  */
/*  Implements MEMORY_MOVE_COST.  */
int
int
m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
                       int reg_class ATTRIBUTE_UNUSED,
                       int reg_class ATTRIBUTE_UNUSED,
                       int in ATTRIBUTE_UNUSED)
                       int in ATTRIBUTE_UNUSED)
{
{
  /* FIXME: pick real values.  */
  /* FIXME: pick real values.  */
  return COSTS_N_INSNS (10);
  return COSTS_N_INSNS (10);
}
}
 
 
/* Here we try to describe when we use multiple opcodes for one RTX so
/* Here we try to describe when we use multiple opcodes for one RTX so
   that gcc knows when to use them.  */
   that gcc knows when to use them.  */
#undef TARGET_RTX_COSTS
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS m32c_rtx_costs
#define TARGET_RTX_COSTS m32c_rtx_costs
static bool
static bool
m32c_rtx_costs (rtx x, int code, int outer_code, int *total,
m32c_rtx_costs (rtx x, int code, int outer_code, int *total,
                bool speed ATTRIBUTE_UNUSED)
                bool speed ATTRIBUTE_UNUSED)
{
{
  switch (code)
  switch (code)
    {
    {
    case REG:
    case REG:
      if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
      if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
        *total += COSTS_N_INSNS (500);
        *total += COSTS_N_INSNS (500);
      else
      else
        *total += COSTS_N_INSNS (1);
        *total += COSTS_N_INSNS (1);
      return true;
      return true;
 
 
    case ASHIFT:
    case ASHIFT:
    case LSHIFTRT:
    case LSHIFTRT:
    case ASHIFTRT:
    case ASHIFTRT:
      if (GET_CODE (XEXP (x, 1)) != CONST_INT)
      if (GET_CODE (XEXP (x, 1)) != CONST_INT)
        {
        {
          /* mov.b r1l, r1h */
          /* mov.b r1l, r1h */
          *total +=  COSTS_N_INSNS (1);
          *total +=  COSTS_N_INSNS (1);
          return true;
          return true;
        }
        }
      if (INTVAL (XEXP (x, 1)) > 8
      if (INTVAL (XEXP (x, 1)) > 8
          || INTVAL (XEXP (x, 1)) < -8)
          || INTVAL (XEXP (x, 1)) < -8)
        {
        {
          /* mov.b #N, r1l */
          /* mov.b #N, r1l */
          /* mov.b r1l, r1h */
          /* mov.b r1l, r1h */
          *total +=  COSTS_N_INSNS (2);
          *total +=  COSTS_N_INSNS (2);
          return true;
          return true;
        }
        }
      return true;
      return true;
 
 
    case LE:
    case LE:
    case LEU:
    case LEU:
    case LT:
    case LT:
    case LTU:
    case LTU:
    case GT:
    case GT:
    case GTU:
    case GTU:
    case GE:
    case GE:
    case GEU:
    case GEU:
    case NE:
    case NE:
    case EQ:
    case EQ:
      if (outer_code == SET)
      if (outer_code == SET)
        {
        {
          *total += COSTS_N_INSNS (2);
          *total += COSTS_N_INSNS (2);
          return true;
          return true;
        }
        }
      break;
      break;
 
 
    case ZERO_EXTRACT:
    case ZERO_EXTRACT:
      {
      {
        rtx dest = XEXP (x, 0);
        rtx dest = XEXP (x, 0);
        rtx addr = XEXP (dest, 0);
        rtx addr = XEXP (dest, 0);
        switch (GET_CODE (addr))
        switch (GET_CODE (addr))
          {
          {
          case CONST_INT:
          case CONST_INT:
            *total += COSTS_N_INSNS (1);
            *total += COSTS_N_INSNS (1);
            break;
            break;
          case SYMBOL_REF:
          case SYMBOL_REF:
            *total += COSTS_N_INSNS (3);
            *total += COSTS_N_INSNS (3);
            break;
            break;
          default:
          default:
            *total += COSTS_N_INSNS (2);
            *total += COSTS_N_INSNS (2);
            break;
            break;
          }
          }
        return true;
        return true;
      }
      }
      break;
      break;
 
 
    default:
    default:
      /* Reasonable default.  */
      /* Reasonable default.  */
      if (TARGET_A16 && GET_MODE(x) == SImode)
      if (TARGET_A16 && GET_MODE(x) == SImode)
        *total += COSTS_N_INSNS (2);
        *total += COSTS_N_INSNS (2);
      break;
      break;
    }
    }
  return false;
  return false;
}
}
 
 
#undef TARGET_ADDRESS_COST
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST m32c_address_cost
#define TARGET_ADDRESS_COST m32c_address_cost
static int
static int
m32c_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
m32c_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
{
{
  int i;
  int i;
  /*  fprintf(stderr, "\naddress_cost\n");
  /*  fprintf(stderr, "\naddress_cost\n");
      debug_rtx(addr);*/
      debug_rtx(addr);*/
  switch (GET_CODE (addr))
  switch (GET_CODE (addr))
    {
    {
    case CONST_INT:
    case CONST_INT:
      i = INTVAL (addr);
      i = INTVAL (addr);
      if (i == 0)
      if (i == 0)
        return COSTS_N_INSNS(1);
        return COSTS_N_INSNS(1);
      if (0 < i && i <= 255)
      if (0 < i && i <= 255)
        return COSTS_N_INSNS(2);
        return COSTS_N_INSNS(2);
      if (0 < i && i <= 65535)
      if (0 < i && i <= 65535)
        return COSTS_N_INSNS(3);
        return COSTS_N_INSNS(3);
      return COSTS_N_INSNS(4);
      return COSTS_N_INSNS(4);
    case SYMBOL_REF:
    case SYMBOL_REF:
      return COSTS_N_INSNS(4);
      return COSTS_N_INSNS(4);
    case REG:
    case REG:
      return COSTS_N_INSNS(1);
      return COSTS_N_INSNS(1);
    case PLUS:
    case PLUS:
      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
        {
        {
          i = INTVAL (XEXP (addr, 1));
          i = INTVAL (XEXP (addr, 1));
          if (i == 0)
          if (i == 0)
            return COSTS_N_INSNS(1);
            return COSTS_N_INSNS(1);
          if (0 < i && i <= 255)
          if (0 < i && i <= 255)
            return COSTS_N_INSNS(2);
            return COSTS_N_INSNS(2);
          if (0 < i && i <= 65535)
          if (0 < i && i <= 65535)
            return COSTS_N_INSNS(3);
            return COSTS_N_INSNS(3);
        }
        }
      return COSTS_N_INSNS(4);
      return COSTS_N_INSNS(4);
    default:
    default:
      return 0;
      return 0;
    }
    }
}
}
 
 
/* Defining the Output Assembler Language */
/* Defining the Output Assembler Language */
 
 
/* The Overall Framework of an Assembler File */
/* The Overall Framework of an Assembler File */
 
 
#undef TARGET_HAVE_NAMED_SECTIONS
#undef TARGET_HAVE_NAMED_SECTIONS
#define TARGET_HAVE_NAMED_SECTIONS true
#define TARGET_HAVE_NAMED_SECTIONS true
 
 
/* Output of Data */
/* Output of Data */
 
 
/* We may have 24 bit sizes, which is the native address size.
/* We may have 24 bit sizes, which is the native address size.
   Currently unused, but provided for completeness.  */
   Currently unused, but provided for completeness.  */
#undef TARGET_ASM_INTEGER
#undef TARGET_ASM_INTEGER
#define TARGET_ASM_INTEGER m32c_asm_integer
#define TARGET_ASM_INTEGER m32c_asm_integer
static bool
static bool
m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
{
{
  switch (size)
  switch (size)
    {
    {
    case 3:
    case 3:
      fprintf (asm_out_file, "\t.3byte\t");
      fprintf (asm_out_file, "\t.3byte\t");
      output_addr_const (asm_out_file, x);
      output_addr_const (asm_out_file, x);
      fputc ('\n', asm_out_file);
      fputc ('\n', asm_out_file);
      return true;
      return true;
    case 4:
    case 4:
      if (GET_CODE (x) == SYMBOL_REF)
      if (GET_CODE (x) == SYMBOL_REF)
        {
        {
          fprintf (asm_out_file, "\t.long\t");
          fprintf (asm_out_file, "\t.long\t");
          output_addr_const (asm_out_file, x);
          output_addr_const (asm_out_file, x);
          fputc ('\n', asm_out_file);
          fputc ('\n', asm_out_file);
          return true;
          return true;
        }
        }
      break;
      break;
    }
    }
  return default_assemble_integer (x, size, aligned_p);
  return default_assemble_integer (x, size, aligned_p);
}
}
 
 
/* Output of Assembler Instructions */
/* Output of Assembler Instructions */
 
 
/* We use a lookup table because the addressing modes are non-orthogonal.  */
/* We use a lookup table because the addressing modes are non-orthogonal.  */
 
 
static struct
static struct
{
{
  char code;
  char code;
  char const *pattern;
  char const *pattern;
  char const *format;
  char const *format;
}
}
const conversions[] = {
const conversions[] = {
  { 0, "r", "0" },
  { 0, "r", "0" },
 
 
  { 0, "mr", "z[1]" },
  { 0, "mr", "z[1]" },
  { 0, "m+ri", "3[2]" },
  { 0, "m+ri", "3[2]" },
  { 0, "m+rs", "3[2]" },
  { 0, "m+rs", "3[2]" },
  { 0, "m+r+si", "4+5[2]" },
  { 0, "m+r+si", "4+5[2]" },
  { 0, "ms", "1" },
  { 0, "ms", "1" },
  { 0, "mi", "1" },
  { 0, "mi", "1" },
  { 0, "m+si", "2+3" },
  { 0, "m+si", "2+3" },
 
 
  { 0, "mmr", "[z[2]]" },
  { 0, "mmr", "[z[2]]" },
  { 0, "mm+ri", "[4[3]]" },
  { 0, "mm+ri", "[4[3]]" },
  { 0, "mm+rs", "[4[3]]" },
  { 0, "mm+rs", "[4[3]]" },
  { 0, "mm+r+si", "[5+6[3]]" },
  { 0, "mm+r+si", "[5+6[3]]" },
  { 0, "mms", "[[2]]" },
  { 0, "mms", "[[2]]" },
  { 0, "mmi", "[[2]]" },
  { 0, "mmi", "[[2]]" },
  { 0, "mm+si", "[4[3]]" },
  { 0, "mm+si", "[4[3]]" },
 
 
  { 0, "i", "#0" },
  { 0, "i", "#0" },
  { 0, "s", "#0" },
  { 0, "s", "#0" },
  { 0, "+si", "#1+2" },
  { 0, "+si", "#1+2" },
  { 0, "l", "#0" },
  { 0, "l", "#0" },
 
 
  { 'l', "l", "0" },
  { 'l', "l", "0" },
  { 'd', "i", "0" },
  { 'd', "i", "0" },
  { 'd', "s", "0" },
  { 'd', "s", "0" },
  { 'd', "+si", "1+2" },
  { 'd', "+si", "1+2" },
  { 'D', "i", "0" },
  { 'D', "i", "0" },
  { 'D', "s", "0" },
  { 'D', "s", "0" },
  { 'D', "+si", "1+2" },
  { 'D', "+si", "1+2" },
  { 'x', "i", "#0" },
  { 'x', "i", "#0" },
  { 'X', "i", "#0" },
  { 'X', "i", "#0" },
  { 'm', "i", "#0" },
  { 'm', "i", "#0" },
  { 'b', "i", "#0" },
  { 'b', "i", "#0" },
  { 'B', "i", "0" },
  { 'B', "i", "0" },
  { 'p', "i", "0" },
  { 'p', "i", "0" },
 
 
  { 0, 0, 0 }
  { 0, 0, 0 }
};
};
 
 
/* This is in order according to the bitfield that pushm/popm use.  */
/* This is in order according to the bitfield that pushm/popm use.  */
static char const *pushm_regs[] = {
static char const *pushm_regs[] = {
  "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
  "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
};
};
 
 
/* Implements PRINT_OPERAND.  */
/* Implements PRINT_OPERAND.  */
void
void
m32c_print_operand (FILE * file, rtx x, int code)
m32c_print_operand (FILE * file, rtx x, int code)
{
{
  int i, j, b;
  int i, j, b;
  const char *comma;
  const char *comma;
  HOST_WIDE_INT ival;
  HOST_WIDE_INT ival;
  int unsigned_const = 0;
  int unsigned_const = 0;
  int force_sign;
  int force_sign;
 
 
  /* Multiplies; constants are converted to sign-extended format but
  /* Multiplies; constants are converted to sign-extended format but
   we need unsigned, so 'u' and 'U' tell us what size unsigned we
   we need unsigned, so 'u' and 'U' tell us what size unsigned we
   need.  */
   need.  */
  if (code == 'u')
  if (code == 'u')
    {
    {
      unsigned_const = 2;
      unsigned_const = 2;
      code = 0;
      code = 0;
    }
    }
  if (code == 'U')
  if (code == 'U')
    {
    {
      unsigned_const = 1;
      unsigned_const = 1;
      code = 0;
      code = 0;
    }
    }
  /* This one is only for debugging; you can put it in a pattern to
  /* This one is only for debugging; you can put it in a pattern to
     force this error.  */
     force this error.  */
  if (code == '!')
  if (code == '!')
    {
    {
      fprintf (stderr, "dj: unreviewed pattern:");
      fprintf (stderr, "dj: unreviewed pattern:");
      if (current_output_insn)
      if (current_output_insn)
        debug_rtx (current_output_insn);
        debug_rtx (current_output_insn);
      gcc_unreachable ();
      gcc_unreachable ();
    }
    }
  /* PSImode operations are either .w or .l depending on the target.  */
  /* PSImode operations are either .w or .l depending on the target.  */
  if (code == '&')
  if (code == '&')
    {
    {
      if (TARGET_A16)
      if (TARGET_A16)
        fprintf (file, "w");
        fprintf (file, "w");
      else
      else
        fprintf (file, "l");
        fprintf (file, "l");
      return;
      return;
    }
    }
  /* Inverted conditionals.  */
  /* Inverted conditionals.  */
  if (code == 'C')
  if (code == 'C')
    {
    {
      switch (GET_CODE (x))
      switch (GET_CODE (x))
        {
        {
        case LE:
        case LE:
          fputs ("gt", file);
          fputs ("gt", file);
          break;
          break;
        case LEU:
        case LEU:
          fputs ("gtu", file);
          fputs ("gtu", file);
          break;
          break;
        case LT:
        case LT:
          fputs ("ge", file);
          fputs ("ge", file);
          break;
          break;
        case LTU:
        case LTU:
          fputs ("geu", file);
          fputs ("geu", file);
          break;
          break;
        case GT:
        case GT:
          fputs ("le", file);
          fputs ("le", file);
          break;
          break;
        case GTU:
        case GTU:
          fputs ("leu", file);
          fputs ("leu", file);
          break;
          break;
        case GE:
        case GE:
          fputs ("lt", file);
          fputs ("lt", file);
          break;
          break;
        case GEU:
        case GEU:
          fputs ("ltu", file);
          fputs ("ltu", file);
          break;
          break;
        case NE:
        case NE:
          fputs ("eq", file);
          fputs ("eq", file);
          break;
          break;
        case EQ:
        case EQ:
          fputs ("ne", file);
          fputs ("ne", file);
          break;
          break;
        default:
        default:
          gcc_unreachable ();
          gcc_unreachable ();
        }
        }
      return;
      return;
    }
    }
  /* Regular conditionals.  */
  /* Regular conditionals.  */
  if (code == 'c')
  if (code == 'c')
    {
    {
      switch (GET_CODE (x))
      switch (GET_CODE (x))
        {
        {
        case LE:
        case LE:
          fputs ("le", file);
          fputs ("le", file);
          break;
          break;
        case LEU:
        case LEU:
          fputs ("leu", file);
          fputs ("leu", file);
          break;
          break;
        case LT:
        case LT:
          fputs ("lt", file);
          fputs ("lt", file);
          break;
          break;
        case LTU:
        case LTU:
          fputs ("ltu", file);
          fputs ("ltu", file);
          break;
          break;
        case GT:
        case GT:
          fputs ("gt", file);
          fputs ("gt", file);
          break;
          break;
        case GTU:
        case GTU:
          fputs ("gtu", file);
          fputs ("gtu", file);
          break;
          break;
        case GE:
        case GE:
          fputs ("ge", file);
          fputs ("ge", file);
          break;
          break;
        case GEU:
        case GEU:
          fputs ("geu", file);
          fputs ("geu", file);
          break;
          break;
        case NE:
        case NE:
          fputs ("ne", file);
          fputs ("ne", file);
          break;
          break;
        case EQ:
        case EQ:
          fputs ("eq", file);
          fputs ("eq", file);
          break;
          break;
        default:
        default:
          gcc_unreachable ();
          gcc_unreachable ();
        }
        }
      return;
      return;
    }
    }
  /* Used in negsi2 to do HImode ops on the two parts of an SImode
  /* Used in negsi2 to do HImode ops on the two parts of an SImode
     operand.  */
     operand.  */
  if (code == 'h' && GET_MODE (x) == SImode)
  if (code == 'h' && GET_MODE (x) == SImode)
    {
    {
      x = m32c_subreg (HImode, x, SImode, 0);
      x = m32c_subreg (HImode, x, SImode, 0);
      code = 0;
      code = 0;
    }
    }
  if (code == 'H' && GET_MODE (x) == SImode)
  if (code == 'H' && GET_MODE (x) == SImode)
    {
    {
      x = m32c_subreg (HImode, x, SImode, 2);
      x = m32c_subreg (HImode, x, SImode, 2);
      code = 0;
      code = 0;
    }
    }
  if (code == 'h' && GET_MODE (x) == HImode)
  if (code == 'h' && GET_MODE (x) == HImode)
    {
    {
      x = m32c_subreg (QImode, x, HImode, 0);
      x = m32c_subreg (QImode, x, HImode, 0);
      code = 0;
      code = 0;
    }
    }
  if (code == 'H' && GET_MODE (x) == HImode)
  if (code == 'H' && GET_MODE (x) == HImode)
    {
    {
      /* We can't actually represent this as an rtx.  Do it here.  */
      /* We can't actually represent this as an rtx.  Do it here.  */
      if (GET_CODE (x) == REG)
      if (GET_CODE (x) == REG)
        {
        {
          switch (REGNO (x))
          switch (REGNO (x))
            {
            {
            case R0_REGNO:
            case R0_REGNO:
              fputs ("r0h", file);
              fputs ("r0h", file);
              return;
              return;
            case R1_REGNO:
            case R1_REGNO:
              fputs ("r1h", file);
              fputs ("r1h", file);
              return;
              return;
            default:
            default:
              gcc_unreachable();
              gcc_unreachable();
            }
            }
        }
        }
      /* This should be a MEM.  */
      /* This should be a MEM.  */
      x = m32c_subreg (QImode, x, HImode, 1);
      x = m32c_subreg (QImode, x, HImode, 1);
      code = 0;
      code = 0;
    }
    }
  /* This is for BMcond, which always wants word register names.  */
  /* This is for BMcond, which always wants word register names.  */
  if (code == 'h' && GET_MODE (x) == QImode)
  if (code == 'h' && GET_MODE (x) == QImode)
    {
    {
      if (GET_CODE (x) == REG)
      if (GET_CODE (x) == REG)
        x = gen_rtx_REG (HImode, REGNO (x));
        x = gen_rtx_REG (HImode, REGNO (x));
      code = 0;
      code = 0;
    }
    }
  /* 'x' and 'X' need to be ignored for non-immediates.  */
  /* 'x' and 'X' need to be ignored for non-immediates.  */
  if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
  if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
    code = 0;
    code = 0;
 
 
  encode_pattern (x);
  encode_pattern (x);
  force_sign = 0;
  force_sign = 0;
  for (i = 0; conversions[i].pattern; i++)
  for (i = 0; conversions[i].pattern; i++)
    if (conversions[i].code == code
    if (conversions[i].code == code
        && streq (conversions[i].pattern, pattern))
        && streq (conversions[i].pattern, pattern))
      {
      {
        for (j = 0; conversions[i].format[j]; j++)
        for (j = 0; conversions[i].format[j]; j++)
          /* backslash quotes the next character in the output pattern.  */
          /* backslash quotes the next character in the output pattern.  */
          if (conversions[i].format[j] == '\\')
          if (conversions[i].format[j] == '\\')
            {
            {
              fputc (conversions[i].format[j + 1], file);
              fputc (conversions[i].format[j + 1], file);
              j++;
              j++;
            }
            }
          /* Digits in the output pattern indicate that the
          /* Digits in the output pattern indicate that the
             corresponding RTX is to be output at that point.  */
             corresponding RTX is to be output at that point.  */
          else if (ISDIGIT (conversions[i].format[j]))
          else if (ISDIGIT (conversions[i].format[j]))
            {
            {
              rtx r = patternr[conversions[i].format[j] - '0'];
              rtx r = patternr[conversions[i].format[j] - '0'];
              switch (GET_CODE (r))
              switch (GET_CODE (r))
                {
                {
                case REG:
                case REG:
                  fprintf (file, "%s",
                  fprintf (file, "%s",
                           reg_name_with_mode (REGNO (r), GET_MODE (r)));
                           reg_name_with_mode (REGNO (r), GET_MODE (r)));
                  break;
                  break;
                case CONST_INT:
                case CONST_INT:
                  switch (code)
                  switch (code)
                    {
                    {
                    case 'b':
                    case 'b':
                    case 'B':
                    case 'B':
                      {
                      {
                        int v = INTVAL (r);
                        int v = INTVAL (r);
                        int i = (int) exact_log2 (v);
                        int i = (int) exact_log2 (v);
                        if (i == -1)
                        if (i == -1)
                          i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
                          i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
                        if (i == -1)
                        if (i == -1)
                          i = (int) exact_log2 ((v ^ 0xff) & 0xff);
                          i = (int) exact_log2 ((v ^ 0xff) & 0xff);
                        /* Bit position.  */
                        /* Bit position.  */
                        fprintf (file, "%d", i);
                        fprintf (file, "%d", i);
                      }
                      }
                      break;
                      break;
                    case 'x':
                    case 'x':
                      /* Unsigned byte.  */
                      /* Unsigned byte.  */
                      fprintf (file, HOST_WIDE_INT_PRINT_HEX,
                      fprintf (file, HOST_WIDE_INT_PRINT_HEX,
                               INTVAL (r) & 0xff);
                               INTVAL (r) & 0xff);
                      break;
                      break;
                    case 'X':
                    case 'X':
                      /* Unsigned word.  */
                      /* Unsigned word.  */
                      fprintf (file, HOST_WIDE_INT_PRINT_HEX,
                      fprintf (file, HOST_WIDE_INT_PRINT_HEX,
                               INTVAL (r) & 0xffff);
                               INTVAL (r) & 0xffff);
                      break;
                      break;
                    case 'p':
                    case 'p':
                      /* pushm and popm encode a register set into a single byte.  */
                      /* pushm and popm encode a register set into a single byte.  */
                      comma = "";
                      comma = "";
                      for (b = 7; b >= 0; b--)
                      for (b = 7; b >= 0; b--)
                        if (INTVAL (r) & (1 << b))
                        if (INTVAL (r) & (1 << b))
                          {
                          {
                            fprintf (file, "%s%s", comma, pushm_regs[b]);
                            fprintf (file, "%s%s", comma, pushm_regs[b]);
                            comma = ",";
                            comma = ",";
                          }
                          }
                      break;
                      break;
                    case 'm':
                    case 'm':
                      /* "Minus".  Output -X  */
                      /* "Minus".  Output -X  */
                      ival = (-INTVAL (r) & 0xffff);
                      ival = (-INTVAL (r) & 0xffff);
                      if (ival & 0x8000)
                      if (ival & 0x8000)
                        ival = ival - 0x10000;
                        ival = ival - 0x10000;
                      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
                      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
                      break;
                      break;
                    default:
                    default:
                      ival = INTVAL (r);
                      ival = INTVAL (r);
                      if (conversions[i].format[j + 1] == '[' && ival < 0)
                      if (conversions[i].format[j + 1] == '[' && ival < 0)
                        {
                        {
                          /* We can simulate negative displacements by
                          /* We can simulate negative displacements by
                             taking advantage of address space
                             taking advantage of address space
                             wrapping when the offset can span the
                             wrapping when the offset can span the
                             entire address range.  */
                             entire address range.  */
                          rtx base =
                          rtx base =
                            patternr[conversions[i].format[j + 2] - '0'];
                            patternr[conversions[i].format[j + 2] - '0'];
                          if (GET_CODE (base) == REG)
                          if (GET_CODE (base) == REG)
                            switch (REGNO (base))
                            switch (REGNO (base))
                              {
                              {
                              case A0_REGNO:
                              case A0_REGNO:
                              case A1_REGNO:
                              case A1_REGNO:
                                if (TARGET_A24)
                                if (TARGET_A24)
                                  ival = 0x1000000 + ival;
                                  ival = 0x1000000 + ival;
                                else
                                else
                                  ival = 0x10000 + ival;
                                  ival = 0x10000 + ival;
                                break;
                                break;
                              case SB_REGNO:
                              case SB_REGNO:
                                if (TARGET_A16)
                                if (TARGET_A16)
                                  ival = 0x10000 + ival;
                                  ival = 0x10000 + ival;
                                break;
                                break;
                              }
                              }
                        }
                        }
                      else if (code == 'd' && ival < 0 && j == 0)
                      else if (code == 'd' && ival < 0 && j == 0)
                        /* The "mova" opcode is used to do addition by
                        /* The "mova" opcode is used to do addition by
                           computing displacements, but again, we need
                           computing displacements, but again, we need
                           displacements to be unsigned *if* they're
                           displacements to be unsigned *if* they're
                           the only component of the displacement
                           the only component of the displacement
                           (i.e. no "symbol-4" type displacement).  */
                           (i.e. no "symbol-4" type displacement).  */
                        ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
                        ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
 
 
                      if (conversions[i].format[j] == '0')
                      if (conversions[i].format[j] == '0')
                        {
                        {
                          /* More conversions to unsigned.  */
                          /* More conversions to unsigned.  */
                          if (unsigned_const == 2)
                          if (unsigned_const == 2)
                            ival &= 0xffff;
                            ival &= 0xffff;
                          if (unsigned_const == 1)
                          if (unsigned_const == 1)
                            ival &= 0xff;
                            ival &= 0xff;
                        }
                        }
                      if (streq (conversions[i].pattern, "mi")
                      if (streq (conversions[i].pattern, "mi")
                          || streq (conversions[i].pattern, "mmi"))
                          || streq (conversions[i].pattern, "mmi"))
                        {
                        {
                          /* Integers used as addresses are unsigned.  */
                          /* Integers used as addresses are unsigned.  */
                          ival &= (TARGET_A24 ? 0xffffff : 0xffff);
                          ival &= (TARGET_A24 ? 0xffffff : 0xffff);
                        }
                        }
                      if (force_sign && ival >= 0)
                      if (force_sign && ival >= 0)
                        fputc ('+', file);
                        fputc ('+', file);
                      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
                      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
                      break;
                      break;
                    }
                    }
                  break;
                  break;
                case CONST_DOUBLE:
                case CONST_DOUBLE:
                  /* We don't have const_double constants.  If it
                  /* We don't have const_double constants.  If it
                     happens, make it obvious.  */
                     happens, make it obvious.  */
                  fprintf (file, "[const_double 0x%lx]",
                  fprintf (file, "[const_double 0x%lx]",
                           (unsigned long) CONST_DOUBLE_HIGH (r));
                           (unsigned long) CONST_DOUBLE_HIGH (r));
                  break;
                  break;
                case SYMBOL_REF:
                case SYMBOL_REF:
                  assemble_name (file, XSTR (r, 0));
                  assemble_name (file, XSTR (r, 0));
                  break;
                  break;
                case LABEL_REF:
                case LABEL_REF:
                  output_asm_label (r);
                  output_asm_label (r);
                  break;
                  break;
                default:
                default:
                  fprintf (stderr, "don't know how to print this operand:");
                  fprintf (stderr, "don't know how to print this operand:");
                  debug_rtx (r);
                  debug_rtx (r);
                  gcc_unreachable ();
                  gcc_unreachable ();
                }
                }
            }
            }
          else
          else
            {
            {
              if (conversions[i].format[j] == 'z')
              if (conversions[i].format[j] == 'z')
                {
                {
                  /* Some addressing modes *must* have a displacement,
                  /* Some addressing modes *must* have a displacement,
                     so insert a zero here if needed.  */
                     so insert a zero here if needed.  */
                  int k;
                  int k;
                  for (k = j + 1; conversions[i].format[k]; k++)
                  for (k = j + 1; conversions[i].format[k]; k++)
                    if (ISDIGIT (conversions[i].format[k]))
                    if (ISDIGIT (conversions[i].format[k]))
                      {
                      {
                        rtx reg = patternr[conversions[i].format[k] - '0'];
                        rtx reg = patternr[conversions[i].format[k] - '0'];
                        if (GET_CODE (reg) == REG
                        if (GET_CODE (reg) == REG
                            && (REGNO (reg) == SB_REGNO
                            && (REGNO (reg) == SB_REGNO
                                || REGNO (reg) == FB_REGNO
                                || REGNO (reg) == FB_REGNO
                                || REGNO (reg) == SP_REGNO))
                                || REGNO (reg) == SP_REGNO))
                          fputc ('0', file);
                          fputc ('0', file);
                      }
                      }
                  continue;
                  continue;
                }
                }
              /* Signed displacements off symbols need to have signs
              /* Signed displacements off symbols need to have signs
                 blended cleanly.  */
                 blended cleanly.  */
              if (conversions[i].format[j] == '+'
              if (conversions[i].format[j] == '+'
                  && (!code || code == 'D' || code == 'd')
                  && (!code || code == 'D' || code == 'd')
                  && ISDIGIT (conversions[i].format[j + 1])
                  && ISDIGIT (conversions[i].format[j + 1])
                  && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
                  && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
                      == CONST_INT))
                      == CONST_INT))
                {
                {
                  force_sign = 1;
                  force_sign = 1;
                  continue;
                  continue;
                }
                }
              fputc (conversions[i].format[j], file);
              fputc (conversions[i].format[j], file);
            }
            }
        break;
        break;
      }
      }
  if (!conversions[i].pattern)
  if (!conversions[i].pattern)
    {
    {
      fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
      fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
               pattern);
               pattern);
      debug_rtx (x);
      debug_rtx (x);
      fprintf (file, "[%c.%s]", code ? code : '-', pattern);
      fprintf (file, "[%c.%s]", code ? code : '-', pattern);
    }
    }
 
 
  return;
  return;
}
}
 
 
/* Implements PRINT_OPERAND_PUNCT_VALID_P.  See m32c_print_operand
/* Implements PRINT_OPERAND_PUNCT_VALID_P.  See m32c_print_operand
   above for descriptions of what these do.  */
   above for descriptions of what these do.  */
int
int
m32c_print_operand_punct_valid_p (int c)
m32c_print_operand_punct_valid_p (int c)
{
{
  if (c == '&' || c == '!')
  if (c == '&' || c == '!')
    return 1;
    return 1;
  return 0;
  return 0;
}
}
 
 
/* Implements PRINT_OPERAND_ADDRESS.  Nothing unusual here.  */
/* Implements PRINT_OPERAND_ADDRESS.  Nothing unusual here.  */
void
void
m32c_print_operand_address (FILE * stream, rtx address)
m32c_print_operand_address (FILE * stream, rtx address)
{
{
  if (GET_CODE (address) == MEM)
  if (GET_CODE (address) == MEM)
    address = XEXP (address, 0);
    address = XEXP (address, 0);
  else
  else
    /* cf: gcc.dg/asm-4.c.  */
    /* cf: gcc.dg/asm-4.c.  */
    gcc_assert (GET_CODE (address) == REG);
    gcc_assert (GET_CODE (address) == REG);
 
 
  m32c_print_operand (stream, address, 0);
  m32c_print_operand (stream, address, 0);
}
}
 
 
/* Implements ASM_OUTPUT_REG_PUSH.  Control registers are pushed
/* Implements ASM_OUTPUT_REG_PUSH.  Control registers are pushed
   differently than general registers.  */
   differently than general registers.  */
void
void
m32c_output_reg_push (FILE * s, int regno)
m32c_output_reg_push (FILE * s, int regno)
{
{
  if (regno == FLG_REGNO)
  if (regno == FLG_REGNO)
    fprintf (s, "\tpushc\tflg\n");
    fprintf (s, "\tpushc\tflg\n");
  else
  else
    fprintf (s, "\tpush.%c\t%s\n",
    fprintf (s, "\tpush.%c\t%s\n",
             " bwll"[reg_push_size (regno)], reg_names[regno]);
             " bwll"[reg_push_size (regno)], reg_names[regno]);
}
}
 
 
/* Likewise for ASM_OUTPUT_REG_POP.  */
/* Likewise for ASM_OUTPUT_REG_POP.  */
void
void
m32c_output_reg_pop (FILE * s, int regno)
m32c_output_reg_pop (FILE * s, int regno)
{
{
  if (regno == FLG_REGNO)
  if (regno == FLG_REGNO)
    fprintf (s, "\tpopc\tflg\n");
    fprintf (s, "\tpopc\tflg\n");
  else
  else
    fprintf (s, "\tpop.%c\t%s\n",
    fprintf (s, "\tpop.%c\t%s\n",
             " bwll"[reg_push_size (regno)], reg_names[regno]);
             " bwll"[reg_push_size (regno)], reg_names[regno]);
}
}
 
 
/* Defining target-specific uses of `__attribute__' */
/* Defining target-specific uses of `__attribute__' */
 
 
/* Used to simplify the logic below.  Find the attributes wherever
/* Used to simplify the logic below.  Find the attributes wherever
   they may be.  */
   they may be.  */
#define M32C_ATTRIBUTES(decl) \
#define M32C_ATTRIBUTES(decl) \
  (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
  (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
                : DECL_ATTRIBUTES (decl) \
                : DECL_ATTRIBUTES (decl) \
                  ? (DECL_ATTRIBUTES (decl)) \
                  ? (DECL_ATTRIBUTES (decl)) \
                  : TYPE_ATTRIBUTES (TREE_TYPE (decl))
                  : TYPE_ATTRIBUTES (TREE_TYPE (decl))
 
 
/* Returns TRUE if the given tree has the "interrupt" attribute.  */
/* Returns TRUE if the given tree has the "interrupt" attribute.  */
static int
static int
interrupt_p (tree node ATTRIBUTE_UNUSED)
interrupt_p (tree node ATTRIBUTE_UNUSED)
{
{
  tree list = M32C_ATTRIBUTES (node);
  tree list = M32C_ATTRIBUTES (node);
  while (list)
  while (list)
    {
    {
      if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
      if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
        return 1;
        return 1;
      list = TREE_CHAIN (list);
      list = TREE_CHAIN (list);
    }
    }
  return fast_interrupt_p (node);
  return fast_interrupt_p (node);
}
}
 
 
/* Returns TRUE if the given tree has the "bank_switch" attribute.  */
/* Returns TRUE if the given tree has the "bank_switch" attribute.  */
static int
static int
bank_switch_p (tree node ATTRIBUTE_UNUSED)
bank_switch_p (tree node ATTRIBUTE_UNUSED)
{
{
  tree list = M32C_ATTRIBUTES (node);
  tree list = M32C_ATTRIBUTES (node);
  while (list)
  while (list)
    {
    {
      if (is_attribute_p ("bank_switch", TREE_PURPOSE (list)))
      if (is_attribute_p ("bank_switch", TREE_PURPOSE (list)))
        return 1;
        return 1;
      list = TREE_CHAIN (list);
      list = TREE_CHAIN (list);
    }
    }
  return 0;
  return 0;
}
}
 
 
/* Returns TRUE if the given tree has the "fast_interrupt" attribute.  */
/* Returns TRUE if the given tree has the "fast_interrupt" attribute.  */
static int
static int
fast_interrupt_p (tree node ATTRIBUTE_UNUSED)
fast_interrupt_p (tree node ATTRIBUTE_UNUSED)
{
{
  tree list = M32C_ATTRIBUTES (node);
  tree list = M32C_ATTRIBUTES (node);
  while (list)
  while (list)
    {
    {
      if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list)))
      if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list)))
        return 1;
        return 1;
      list = TREE_CHAIN (list);
      list = TREE_CHAIN (list);
    }
    }
  return 0;
  return 0;
}
}
 
 
static tree
static tree
interrupt_handler (tree * node ATTRIBUTE_UNUSED,
interrupt_handler (tree * node ATTRIBUTE_UNUSED,
                   tree name ATTRIBUTE_UNUSED,
                   tree name ATTRIBUTE_UNUSED,
                   tree args ATTRIBUTE_UNUSED,
                   tree args ATTRIBUTE_UNUSED,
                   int flags ATTRIBUTE_UNUSED,
                   int flags ATTRIBUTE_UNUSED,
                   bool * no_add_attrs ATTRIBUTE_UNUSED)
                   bool * no_add_attrs ATTRIBUTE_UNUSED)
{
{
  return NULL_TREE;
  return NULL_TREE;
}
}
 
 
/* Returns TRUE if given tree has the "function_vector" attribute. */
/* Returns TRUE if given tree has the "function_vector" attribute. */
int
int
m32c_special_page_vector_p (tree func)
m32c_special_page_vector_p (tree func)
{
{
  tree list;
  tree list;
 
 
  if (TREE_CODE (func) != FUNCTION_DECL)
  if (TREE_CODE (func) != FUNCTION_DECL)
    return 0;
    return 0;
 
 
  list = M32C_ATTRIBUTES (func);
  list = M32C_ATTRIBUTES (func);
  while (list)
  while (list)
    {
    {
      if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
      if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
        return 1;
        return 1;
      list = TREE_CHAIN (list);
      list = TREE_CHAIN (list);
    }
    }
  return 0;
  return 0;
}
}
 
 
static tree
static tree
function_vector_handler (tree * node ATTRIBUTE_UNUSED,
function_vector_handler (tree * node ATTRIBUTE_UNUSED,
                         tree name ATTRIBUTE_UNUSED,
                         tree name ATTRIBUTE_UNUSED,
                         tree args ATTRIBUTE_UNUSED,
                         tree args ATTRIBUTE_UNUSED,
                         int flags ATTRIBUTE_UNUSED,
                         int flags ATTRIBUTE_UNUSED,
                         bool * no_add_attrs ATTRIBUTE_UNUSED)
                         bool * no_add_attrs ATTRIBUTE_UNUSED)
{
{
  if (TARGET_R8C)
  if (TARGET_R8C)
    {
    {
      /* The attribute is not supported for R8C target.  */
      /* The attribute is not supported for R8C target.  */
      warning (OPT_Wattributes,
      warning (OPT_Wattributes,
                "%qE attribute is not supported for R8C target",
                "%qE attribute is not supported for R8C target",
                name);
                name);
      *no_add_attrs = true;
      *no_add_attrs = true;
    }
    }
  else if (TREE_CODE (*node) != FUNCTION_DECL)
  else if (TREE_CODE (*node) != FUNCTION_DECL)
    {
    {
      /* The attribute must be applied to functions only.  */
      /* The attribute must be applied to functions only.  */
      warning (OPT_Wattributes,
      warning (OPT_Wattributes,
                "%qE attribute applies only to functions",
                "%qE attribute applies only to functions",
                name);
                name);
      *no_add_attrs = true;
      *no_add_attrs = true;
    }
    }
  else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
  else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
    {
    {
      /* The argument must be a constant integer.  */
      /* The argument must be a constant integer.  */
      warning (OPT_Wattributes,
      warning (OPT_Wattributes,
                "%qE attribute argument not an integer constant",
                "%qE attribute argument not an integer constant",
                name);
                name);
      *no_add_attrs = true;
      *no_add_attrs = true;
    }
    }
  else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
  else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
           || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
           || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
    {
    {
      /* The argument value must be between 18 to 255.  */
      /* The argument value must be between 18 to 255.  */
      warning (OPT_Wattributes,
      warning (OPT_Wattributes,
                "%qE attribute argument should be between 18 to 255",
                "%qE attribute argument should be between 18 to 255",
                name);
                name);
      *no_add_attrs = true;
      *no_add_attrs = true;
    }
    }
  return NULL_TREE;
  return NULL_TREE;
}
}
 
 
/* If the function is assigned the attribute 'function_vector', it
/* If the function is assigned the attribute 'function_vector', it
   returns the function vector number, otherwise returns zero.  */
   returns the function vector number, otherwise returns zero.  */
int
int
current_function_special_page_vector (rtx x)
current_function_special_page_vector (rtx x)
{
{
  int num;
  int num;
 
 
  if ((GET_CODE(x) == SYMBOL_REF)
  if ((GET_CODE(x) == SYMBOL_REF)
      && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
      && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
    {
    {
      tree list;
      tree list;
      tree t = SYMBOL_REF_DECL (x);
      tree t = SYMBOL_REF_DECL (x);
 
 
      if (TREE_CODE (t) != FUNCTION_DECL)
      if (TREE_CODE (t) != FUNCTION_DECL)
        return 0;
        return 0;
 
 
      list = M32C_ATTRIBUTES (t);
      list = M32C_ATTRIBUTES (t);
      while (list)
      while (list)
        {
        {
          if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
          if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
            {
            {
              num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
              num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
              return num;
              return num;
            }
            }
 
 
          list = TREE_CHAIN (list);
          list = TREE_CHAIN (list);
        }
        }
 
 
      return 0;
      return 0;
    }
    }
  else
  else
    return 0;
    return 0;
}
}
 
 
#undef TARGET_ATTRIBUTE_TABLE
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
static const struct attribute_spec m32c_attribute_table[] = {
static const struct attribute_spec m32c_attribute_table[] = {
  {"interrupt", 0, 0, false, false, false, interrupt_handler},
  {"interrupt", 0, 0, false, false, false, interrupt_handler},
  {"bank_switch", 0, 0, false, false, false, interrupt_handler},
  {"bank_switch", 0, 0, false, false, false, interrupt_handler},
  {"fast_interrupt", 0, 0, false, false, false, interrupt_handler},
  {"fast_interrupt", 0, 0, false, false, false, interrupt_handler},
  {"function_vector", 1, 1, true,  false, false, function_vector_handler},
  {"function_vector", 1, 1, true,  false, false, function_vector_handler},
  {0, 0, 0, 0, 0, 0, 0}
  {0, 0, 0, 0, 0, 0, 0}
};
};
 
 
#undef TARGET_COMP_TYPE_ATTRIBUTES
#undef TARGET_COMP_TYPE_ATTRIBUTES
#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
static int
static int
m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
                           const_tree type2 ATTRIBUTE_UNUSED)
                           const_tree type2 ATTRIBUTE_UNUSED)
{
{
  /* 0=incompatible 1=compatible 2=warning */
  /* 0=incompatible 1=compatible 2=warning */
  return 1;
  return 1;
}
}
 
 
#undef TARGET_INSERT_ATTRIBUTES
#undef TARGET_INSERT_ATTRIBUTES
#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
static void
static void
m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
                        tree * attr_ptr ATTRIBUTE_UNUSED)
                        tree * attr_ptr ATTRIBUTE_UNUSED)
{
{
  /* Nothing to do here.  */
  /* Nothing to do here.  */
}
}
 
 
/* Predicates */
/* Predicates */
 
 
/* This is a list of legal subregs of hard regs.  */
/* This is a list of legal subregs of hard regs.  */
static const struct {
static const struct {
  unsigned char outer_mode_size;
  unsigned char outer_mode_size;
  unsigned char inner_mode_size;
  unsigned char inner_mode_size;
  unsigned char byte_mask;
  unsigned char byte_mask;
  unsigned char legal_when;
  unsigned char legal_when;
  unsigned int regno;
  unsigned int regno;
} legal_subregs[] = {
} legal_subregs[] = {
  {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
  {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
  {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
  {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
  {1, 2, 0x01, 1, A0_REGNO},
  {1, 2, 0x01, 1, A0_REGNO},
  {1, 2, 0x01, 1, A1_REGNO},
  {1, 2, 0x01, 1, A1_REGNO},
 
 
  {1, 4, 0x01, 1, A0_REGNO},
  {1, 4, 0x01, 1, A0_REGNO},
  {1, 4, 0x01, 1, A1_REGNO},
  {1, 4, 0x01, 1, A1_REGNO},
 
 
  {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
  {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
  {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
  {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
  {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
  {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
  {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
  {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
  {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
  {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
 
 
  {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
  {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
};
};
 
 
/* Returns TRUE if OP is a subreg of a hard reg which we don't
/* Returns TRUE if OP is a subreg of a hard reg which we don't
   support.  */
   support.  */
bool
bool
m32c_illegal_subreg_p (rtx op)
m32c_illegal_subreg_p (rtx op)
{
{
  int offset;
  int offset;
  unsigned int i;
  unsigned int i;
  int src_mode, dest_mode;
  int src_mode, dest_mode;
 
 
  if (GET_CODE (op) != SUBREG)
  if (GET_CODE (op) != SUBREG)
    return false;
    return false;
 
 
  dest_mode = GET_MODE (op);
  dest_mode = GET_MODE (op);
  offset = SUBREG_BYTE (op);
  offset = SUBREG_BYTE (op);
  op = SUBREG_REG (op);
  op = SUBREG_REG (op);
  src_mode = GET_MODE (op);
  src_mode = GET_MODE (op);
 
 
  if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
  if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
    return false;
    return false;
  if (GET_CODE (op) != REG)
  if (GET_CODE (op) != REG)
    return false;
    return false;
  if (REGNO (op) >= MEM0_REGNO)
  if (REGNO (op) >= MEM0_REGNO)
    return false;
    return false;
 
 
  offset = (1 << offset);
  offset = (1 << offset);
 
 
  for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
  for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
    if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
    if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
        && legal_subregs[i].regno == REGNO (op)
        && legal_subregs[i].regno == REGNO (op)
        && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
        && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
        && legal_subregs[i].byte_mask & offset)
        && legal_subregs[i].byte_mask & offset)
      {
      {
        switch (legal_subregs[i].legal_when)
        switch (legal_subregs[i].legal_when)
          {
          {
          case 1:
          case 1:
            return false;
            return false;
          case 16:
          case 16:
            if (TARGET_A16)
            if (TARGET_A16)
              return false;
              return false;
            break;
            break;
          case 24:
          case 24:
            if (TARGET_A24)
            if (TARGET_A24)
              return false;
              return false;
            break;
            break;
          }
          }
      }
      }
  return true;
  return true;
}
}
 
 
/* Returns TRUE if we support a move between the first two operands.
/* Returns TRUE if we support a move between the first two operands.
   At the moment, we just want to discourage mem to mem moves until
   At the moment, we just want to discourage mem to mem moves until
   after reload, because reload has a hard time with our limited
   after reload, because reload has a hard time with our limited
   number of address registers, and we can get into a situation where
   number of address registers, and we can get into a situation where
   we need three of them when we only have two.  */
   we need three of them when we only have two.  */
bool
bool
m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
{
{
  rtx op0 = operands[0];
  rtx op0 = operands[0];
  rtx op1 = operands[1];
  rtx op1 = operands[1];
 
 
  if (TARGET_A24)
  if (TARGET_A24)
    return true;
    return true;
 
 
#define DEBUG_MOV_OK 0
#define DEBUG_MOV_OK 0
#if DEBUG_MOV_OK
#if DEBUG_MOV_OK
  fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
  fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
  debug_rtx (op0);
  debug_rtx (op0);
  debug_rtx (op1);
  debug_rtx (op1);
#endif
#endif
 
 
  if (GET_CODE (op0) == SUBREG)
  if (GET_CODE (op0) == SUBREG)
    op0 = XEXP (op0, 0);
    op0 = XEXP (op0, 0);
  if (GET_CODE (op1) == SUBREG)
  if (GET_CODE (op1) == SUBREG)
    op1 = XEXP (op1, 0);
    op1 = XEXP (op1, 0);
 
 
  if (GET_CODE (op0) == MEM
  if (GET_CODE (op0) == MEM
      && GET_CODE (op1) == MEM
      && GET_CODE (op1) == MEM
      && ! reload_completed)
      && ! reload_completed)
    {
    {
#if DEBUG_MOV_OK
#if DEBUG_MOV_OK
      fprintf (stderr, " - no, mem to mem\n");
      fprintf (stderr, " - no, mem to mem\n");
#endif
#endif
      return false;
      return false;
    }
    }
 
 
#if DEBUG_MOV_OK
#if DEBUG_MOV_OK
  fprintf (stderr, " - ok\n");
  fprintf (stderr, " - ok\n");
#endif
#endif
  return true;
  return true;
}
}
 
 
/* Returns TRUE if two consecutive HImode mov instructions, generated
/* Returns TRUE if two consecutive HImode mov instructions, generated
   for moving an immediate double data to a double data type variable
   for moving an immediate double data to a double data type variable
   location, can be combined into single SImode mov instruction.  */
   location, can be combined into single SImode mov instruction.  */
bool
bool
m32c_immd_dbl_mov (rtx * operands,
m32c_immd_dbl_mov (rtx * operands,
                   enum machine_mode mode ATTRIBUTE_UNUSED)
                   enum machine_mode mode ATTRIBUTE_UNUSED)
{
{
  int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
  int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
  const char *str1;
  const char *str1;
  const char *str2;
  const char *str2;
 
 
  if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
  if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
      && MEM_SCALAR_P (operands[0])
      && MEM_SCALAR_P (operands[0])
      && !MEM_IN_STRUCT_P (operands[0])
      && !MEM_IN_STRUCT_P (operands[0])
      && GET_CODE (XEXP (operands[2], 0)) == CONST
      && GET_CODE (XEXP (operands[2], 0)) == CONST
      && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
      && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
      && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
      && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
      && MEM_SCALAR_P (operands[2])
      && MEM_SCALAR_P (operands[2])
      && !MEM_IN_STRUCT_P (operands[2]))
      && !MEM_IN_STRUCT_P (operands[2]))
    flag = 1;
    flag = 1;
 
 
  else if (GET_CODE (XEXP (operands[0], 0)) == CONST
  else if (GET_CODE (XEXP (operands[0], 0)) == CONST
           && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
           && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
           && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
           && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
           && MEM_SCALAR_P (operands[0])
           && MEM_SCALAR_P (operands[0])
           && !MEM_IN_STRUCT_P (operands[0])
           && !MEM_IN_STRUCT_P (operands[0])
           && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
           && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
           && GET_CODE (XEXP (operands[2], 0)) == CONST
           && GET_CODE (XEXP (operands[2], 0)) == CONST
           && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
           && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
           && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
           && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
           && MEM_SCALAR_P (operands[2])
           && MEM_SCALAR_P (operands[2])
           && !MEM_IN_STRUCT_P (operands[2]))
           && !MEM_IN_STRUCT_P (operands[2]))
    flag = 2;
    flag = 2;
 
 
  else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
  else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
           &&  GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
           &&  GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
           &&  REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
           &&  REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
           &&  GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
           &&  GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
           &&  MEM_SCALAR_P (operands[0])
           &&  MEM_SCALAR_P (operands[0])
           &&  !MEM_IN_STRUCT_P (operands[0])
           &&  !MEM_IN_STRUCT_P (operands[0])
           &&  !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
           &&  !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
           &&  REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
           &&  REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
           &&  GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
           &&  GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
           &&  MEM_SCALAR_P (operands[2])
           &&  MEM_SCALAR_P (operands[2])
           &&  !MEM_IN_STRUCT_P (operands[2]))
           &&  !MEM_IN_STRUCT_P (operands[2]))
    flag = 3;
    flag = 3;
 
 
  else
  else
    return false;
    return false;
 
 
  switch (flag)
  switch (flag)
    {
    {
    case 1:
    case 1:
      str1 = XSTR (XEXP (operands[0], 0), 0);
      str1 = XSTR (XEXP (operands[0], 0), 0);
      str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
      str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
      if (strcmp (str1, str2) == 0)
      if (strcmp (str1, str2) == 0)
        okflag = 1;
        okflag = 1;
      else
      else
        okflag = 0;
        okflag = 0;
      break;
      break;
    case 2:
    case 2:
      str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
      str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
      str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
      str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
      if (strcmp(str1,str2) == 0)
      if (strcmp(str1,str2) == 0)
        okflag = 1;
        okflag = 1;
      else
      else
        okflag = 0;
        okflag = 0;
      break;
      break;
    case 3:
    case 3:
      offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
      offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
      offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
      offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
      offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
      offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
      if (((offset2-offset1) == 2) && offsetsign != 0)
      if (((offset2-offset1) == 2) && offsetsign != 0)
        okflag = 1;
        okflag = 1;
      else
      else
        okflag = 0;
        okflag = 0;
      break;
      break;
    default:
    default:
      okflag = 0;
      okflag = 0;
    }
    }
 
 
  if (okflag == 1)
  if (okflag == 1)
    {
    {
      HOST_WIDE_INT val;
      HOST_WIDE_INT val;
      operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
      operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
 
 
      val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
      val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
      operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
      operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
 
 
      return true;
      return true;
    }
    }
 
 
  return false;
  return false;
}
}
 
 
/* Expanders */
/* Expanders */
 
 
/* Subregs are non-orthogonal for us, because our registers are all
/* Subregs are non-orthogonal for us, because our registers are all
   different sizes.  */
   different sizes.  */
static rtx
static rtx
m32c_subreg (enum machine_mode outer,
m32c_subreg (enum machine_mode outer,
             rtx x, enum machine_mode inner, int byte)
             rtx x, enum machine_mode inner, int byte)
{
{
  int r, nr = -1;
  int r, nr = -1;
 
 
  /* Converting MEMs to different types that are the same size, we
  /* Converting MEMs to different types that are the same size, we
     just rewrite them.  */
     just rewrite them.  */
  if (GET_CODE (x) == SUBREG
  if (GET_CODE (x) == SUBREG
      && SUBREG_BYTE (x) == 0
      && SUBREG_BYTE (x) == 0
      && GET_CODE (SUBREG_REG (x)) == MEM
      && GET_CODE (SUBREG_REG (x)) == MEM
      && (GET_MODE_SIZE (GET_MODE (x))
      && (GET_MODE_SIZE (GET_MODE (x))
          == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
          == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
    {
    {
      rtx oldx = x;
      rtx oldx = x;
      x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
      x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
      MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
      MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
    }
    }
 
 
  /* Push/pop get done as smaller push/pops.  */
  /* Push/pop get done as smaller push/pops.  */
  if (GET_CODE (x) == MEM
  if (GET_CODE (x) == MEM
      && (GET_CODE (XEXP (x, 0)) == PRE_DEC
      && (GET_CODE (XEXP (x, 0)) == PRE_DEC
          || GET_CODE (XEXP (x, 0)) == POST_INC))
          || GET_CODE (XEXP (x, 0)) == POST_INC))
    return gen_rtx_MEM (outer, XEXP (x, 0));
    return gen_rtx_MEM (outer, XEXP (x, 0));
  if (GET_CODE (x) == SUBREG
  if (GET_CODE (x) == SUBREG
      && GET_CODE (XEXP (x, 0)) == MEM
      && GET_CODE (XEXP (x, 0)) == MEM
      && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
      && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
          || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
          || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
    return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
    return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
 
 
  if (GET_CODE (x) != REG)
  if (GET_CODE (x) != REG)
    return simplify_gen_subreg (outer, x, inner, byte);
    return simplify_gen_subreg (outer, x, inner, byte);
 
 
  r = REGNO (x);
  r = REGNO (x);
  if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
  if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
    return simplify_gen_subreg (outer, x, inner, byte);
    return simplify_gen_subreg (outer, x, inner, byte);
 
 
  if (IS_MEM_REGNO (r))
  if (IS_MEM_REGNO (r))
    return simplify_gen_subreg (outer, x, inner, byte);
    return simplify_gen_subreg (outer, x, inner, byte);
 
 
  /* This is where the complexities of our register layout are
  /* This is where the complexities of our register layout are
     described.  */
     described.  */
  if (byte == 0)
  if (byte == 0)
    nr = r;
    nr = r;
  else if (outer == HImode)
  else if (outer == HImode)
    {
    {
      if (r == R0_REGNO && byte == 2)
      if (r == R0_REGNO && byte == 2)
        nr = R2_REGNO;
        nr = R2_REGNO;
      else if (r == R0_REGNO && byte == 4)
      else if (r == R0_REGNO && byte == 4)
        nr = R1_REGNO;
        nr = R1_REGNO;
      else if (r == R0_REGNO && byte == 6)
      else if (r == R0_REGNO && byte == 6)
        nr = R3_REGNO;
        nr = R3_REGNO;
      else if (r == R1_REGNO && byte == 2)
      else if (r == R1_REGNO && byte == 2)
        nr = R3_REGNO;
        nr = R3_REGNO;
      else if (r == A0_REGNO && byte == 2)
      else if (r == A0_REGNO && byte == 2)
        nr = A1_REGNO;
        nr = A1_REGNO;
    }
    }
  else if (outer == SImode)
  else if (outer == SImode)
    {
    {
      if (r == R0_REGNO && byte == 0)
      if (r == R0_REGNO && byte == 0)
        nr = R0_REGNO;
        nr = R0_REGNO;
      else if (r == R0_REGNO && byte == 4)
      else if (r == R0_REGNO && byte == 4)
        nr = R1_REGNO;
        nr = R1_REGNO;
    }
    }
  if (nr == -1)
  if (nr == -1)
    {
    {
      fprintf (stderr, "m32c_subreg %s %s %d\n",
      fprintf (stderr, "m32c_subreg %s %s %d\n",
               mode_name[outer], mode_name[inner], byte);
               mode_name[outer], mode_name[inner], byte);
      debug_rtx (x);
      debug_rtx (x);
      gcc_unreachable ();
      gcc_unreachable ();
    }
    }
  return gen_rtx_REG (outer, nr);
  return gen_rtx_REG (outer, nr);
}
}
 
 
/* Used to emit move instructions.  We split some moves,
/* Used to emit move instructions.  We split some moves,
   and avoid mem-mem moves.  */
   and avoid mem-mem moves.  */
int
int
m32c_prepare_move (rtx * operands, enum machine_mode mode)
m32c_prepare_move (rtx * operands, enum machine_mode mode)
{
{
  if (TARGET_A16 && mode == PSImode)
  if (TARGET_A16 && mode == PSImode)
    return m32c_split_move (operands, mode, 1);
    return m32c_split_move (operands, mode, 1);
  if ((GET_CODE (operands[0]) == MEM)
  if ((GET_CODE (operands[0]) == MEM)
      && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
      && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
    {
    {
      rtx pmv = XEXP (operands[0], 0);
      rtx pmv = XEXP (operands[0], 0);
      rtx dest_reg = XEXP (pmv, 0);
      rtx dest_reg = XEXP (pmv, 0);
      rtx dest_mod = XEXP (pmv, 1);
      rtx dest_mod = XEXP (pmv, 1);
 
 
      emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
      emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
      operands[0] = gen_rtx_MEM (mode, dest_reg);
      operands[0] = gen_rtx_MEM (mode, dest_reg);
    }
    }
  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[1] = copy_to_mode_reg (mode, operands[1]);
    operands[1] = copy_to_mode_reg (mode, operands[1]);
  return 0;
  return 0;
}
}
 
 
#define DEBUG_SPLIT 0
#define DEBUG_SPLIT 0
 
 
/* Returns TRUE if the given PSImode move should be split.  We split
/* Returns TRUE if the given PSImode move should be split.  We split
   for all r8c/m16c moves, since it doesn't support them, and for
   for all r8c/m16c moves, since it doesn't support them, and for
   POP.L as we can only *push* SImode.  */
   POP.L as we can only *push* SImode.  */
int
int
m32c_split_psi_p (rtx * operands)
m32c_split_psi_p (rtx * operands)
{
{
#if DEBUG_SPLIT
#if DEBUG_SPLIT
  fprintf (stderr, "\nm32c_split_psi_p\n");
  fprintf (stderr, "\nm32c_split_psi_p\n");
  debug_rtx (operands[0]);
  debug_rtx (operands[0]);
  debug_rtx (operands[1]);
  debug_rtx (operands[1]);
#endif
#endif
  if (TARGET_A16)
  if (TARGET_A16)
    {
    {
#if DEBUG_SPLIT
#if DEBUG_SPLIT
      fprintf (stderr, "yes, A16\n");
      fprintf (stderr, "yes, A16\n");
#endif
#endif
      return 1;
      return 1;
    }
    }
  if (GET_CODE (operands[1]) == MEM
  if (GET_CODE (operands[1]) == MEM
      && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
      && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
    {
    {
#if DEBUG_SPLIT
#if DEBUG_SPLIT
      fprintf (stderr, "yes, pop.l\n");
      fprintf (stderr, "yes, pop.l\n");
#endif
#endif
      return 1;
      return 1;
    }
    }
#if DEBUG_SPLIT
#if DEBUG_SPLIT
  fprintf (stderr, "no, default\n");
  fprintf (stderr, "no, default\n");
#endif
#endif
  return 0;
  return 0;
}
}
 
 
/* Split the given move.  SPLIT_ALL is 0 if splitting is optional
/* Split the given move.  SPLIT_ALL is 0 if splitting is optional
   (define_expand), 1 if it is not optional (define_insn_and_split),
   (define_expand), 1 if it is not optional (define_insn_and_split),
   and 3 for define_split (alternate api). */
   and 3 for define_split (alternate api). */
int
int
m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
{
{
  rtx s[4], d[4];
  rtx s[4], d[4];
  int parts, si, di, rev = 0;
  int parts, si, di, rev = 0;
  int rv = 0, opi = 2;
  int rv = 0, opi = 2;
  enum machine_mode submode = HImode;
  enum machine_mode submode = HImode;
  rtx *ops, local_ops[10];
  rtx *ops, local_ops[10];
 
 
  /* define_split modifies the existing operands, but the other two
  /* define_split modifies the existing operands, but the other two
     emit new insns.  OPS is where we store the operand pairs, which
     emit new insns.  OPS is where we store the operand pairs, which
     we emit later.  */
     we emit later.  */
  if (split_all == 3)
  if (split_all == 3)
    ops = operands;
    ops = operands;
  else
  else
    ops = local_ops;
    ops = local_ops;
 
 
  /* Else HImode.  */
  /* Else HImode.  */
  if (mode == DImode)
  if (mode == DImode)
    submode = SImode;
    submode = SImode;
 
 
  /* Before splitting mem-mem moves, force one operand into a
  /* Before splitting mem-mem moves, force one operand into a
     register.  */
     register.  */
  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
  if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
    {
    {
#if DEBUG0
#if DEBUG0
      fprintf (stderr, "force_reg...\n");
      fprintf (stderr, "force_reg...\n");
      debug_rtx (operands[1]);
      debug_rtx (operands[1]);
#endif
#endif
      operands[1] = force_reg (mode, operands[1]);
      operands[1] = force_reg (mode, operands[1]);
#if DEBUG0
#if DEBUG0
      debug_rtx (operands[1]);
      debug_rtx (operands[1]);
#endif
#endif
    }
    }
 
 
  parts = 2;
  parts = 2;
 
 
#if DEBUG_SPLIT
#if DEBUG_SPLIT
  fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
  fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
           split_all);
           split_all);
  debug_rtx (operands[0]);
  debug_rtx (operands[0]);
  debug_rtx (operands[1]);
  debug_rtx (operands[1]);
#endif
#endif
 
 
  /* Note that split_all is not used to select the api after this
  /* Note that split_all is not used to select the api after this
     point, so it's safe to set it to 3 even with define_insn.  */
     point, so it's safe to set it to 3 even with define_insn.  */
  /* None of the chips can move SI operands to sp-relative addresses,
  /* None of the chips can move SI operands to sp-relative addresses,
     so we always split those.  */
     so we always split those.  */
  if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
  if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
    split_all = 3;
    split_all = 3;
 
 
  /* We don't need to split these.  */
  /* We don't need to split these.  */
  if (TARGET_A24
  if (TARGET_A24
      && split_all != 3
      && split_all != 3
      && (mode == SImode || mode == PSImode)
      && (mode == SImode || mode == PSImode)
      && !(GET_CODE (operands[1]) == MEM
      && !(GET_CODE (operands[1]) == MEM
           && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
           && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
    return 0;
    return 0;
 
 
  /* First, enumerate the subregs we'll be dealing with.  */
  /* First, enumerate the subregs we'll be dealing with.  */
  for (si = 0; si < parts; si++)
  for (si = 0; si < parts; si++)
    {
    {
      d[si] =
      d[si] =
        m32c_subreg (submode, operands[0], mode,
        m32c_subreg (submode, operands[0], mode,
                     si * GET_MODE_SIZE (submode));
                     si * GET_MODE_SIZE (submode));
      s[si] =
      s[si] =
        m32c_subreg (submode, operands[1], mode,
        m32c_subreg (submode, operands[1], mode,
                     si * GET_MODE_SIZE (submode));
                     si * GET_MODE_SIZE (submode));
    }
    }
 
 
  /* Split pushes by emitting a sequence of smaller pushes.  */
  /* Split pushes by emitting a sequence of smaller pushes.  */
  if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
  if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
    {
    {
      for (si = parts - 1; si >= 0; si--)
      for (si = parts - 1; si >= 0; si--)
        {
        {
          ops[opi++] = gen_rtx_MEM (submode,
          ops[opi++] = gen_rtx_MEM (submode,
                                    gen_rtx_PRE_DEC (Pmode,
                                    gen_rtx_PRE_DEC (Pmode,
                                                     gen_rtx_REG (Pmode,
                                                     gen_rtx_REG (Pmode,
                                                                  SP_REGNO)));
                                                                  SP_REGNO)));
          ops[opi++] = s[si];
          ops[opi++] = s[si];
        }
        }
 
 
      rv = 1;
      rv = 1;
    }
    }
  /* Likewise for pops.  */
  /* Likewise for pops.  */
  else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
  else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
    {
    {
      for (di = 0; di < parts; di++)
      for (di = 0; di < parts; di++)
        {
        {
          ops[opi++] = d[di];
          ops[opi++] = d[di];
          ops[opi++] = gen_rtx_MEM (submode,
          ops[opi++] = gen_rtx_MEM (submode,
                                    gen_rtx_POST_INC (Pmode,
                                    gen_rtx_POST_INC (Pmode,
                                                      gen_rtx_REG (Pmode,
                                                      gen_rtx_REG (Pmode,
                                                                   SP_REGNO)));
                                                                   SP_REGNO)));
        }
        }
      rv = 1;
      rv = 1;
    }
    }
  else if (split_all)
  else if (split_all)
    {
    {
      /* if d[di] == s[si] for any di < si, we'll early clobber. */
      /* if d[di] == s[si] for any di < si, we'll early clobber. */
      for (di = 0; di < parts - 1; di++)
      for (di = 0; di < parts - 1; di++)
        for (si = di + 1; si < parts; si++)
        for (si = di + 1; si < parts; si++)
          if (reg_mentioned_p (d[di], s[si]))
          if (reg_mentioned_p (d[di], s[si]))
            rev = 1;
            rev = 1;
 
 
      if (rev)
      if (rev)
        for (si = 0; si < parts; si++)
        for (si = 0; si < parts; si++)
          {
          {
            ops[opi++] = d[si];
            ops[opi++] = d[si];
            ops[opi++] = s[si];
            ops[opi++] = s[si];
          }
          }
      else
      else
        for (si = parts - 1; si >= 0; si--)
        for (si = parts - 1; si >= 0; si--)
          {
          {
            ops[opi++] = d[si];
            ops[opi++] = d[si];
            ops[opi++] = s[si];
            ops[opi++] = s[si];
          }
          }
      rv = 1;
      rv = 1;
    }
    }
  /* Now emit any moves we may have accumulated.  */
  /* Now emit any moves we may have accumulated.  */
  if (rv && split_all != 3)
  if (rv && split_all != 3)
    {
    {
      int i;
      int i;
      for (i = 2; i < opi; i += 2)
      for (i = 2; i < opi; i += 2)
        emit_move_insn (ops[i], ops[i + 1]);
        emit_move_insn (ops[i], ops[i + 1]);
    }
    }
  return rv;
  return rv;
}
}
 
 
/* The m32c has a number of opcodes that act like memcpy, strcmp, and
/* The m32c has a number of opcodes that act like memcpy, strcmp, and
   the like.  For the R8C they expect one of the addresses to be in
   the like.  For the R8C they expect one of the addresses to be in
   R1L:An so we need to arrange for that.  Otherwise, it's just a
   R1L:An so we need to arrange for that.  Otherwise, it's just a
   matter of picking out the operands we want and emitting the right
   matter of picking out the operands we want and emitting the right
   pattern for them.  All these expanders, which correspond to
   pattern for them.  All these expanders, which correspond to
   patterns in blkmov.md, must return nonzero if they expand the insn,
   patterns in blkmov.md, must return nonzero if they expand the insn,
   or zero if they should FAIL.  */
   or zero if they should FAIL.  */
 
 
/* This is a memset() opcode.  All operands are implied, so we need to
/* This is a memset() opcode.  All operands are implied, so we need to
   arrange for them to be in the right registers.  The opcode wants
   arrange for them to be in the right registers.  The opcode wants
   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1
   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1
   the count (HI), and $2 the value (QI).  */
   the count (HI), and $2 the value (QI).  */
int
int
m32c_expand_setmemhi(rtx *operands)
m32c_expand_setmemhi(rtx *operands)
{
{
  rtx desta, count, val;
  rtx desta, count, val;
  rtx desto, counto;
  rtx desto, counto;
 
 
  desta = XEXP (operands[0], 0);
  desta = XEXP (operands[0], 0);
  count = operands[1];
  count = operands[1];
  val = operands[2];
  val = operands[2];
 
 
  desto = gen_reg_rtx (Pmode);
  desto = gen_reg_rtx (Pmode);
  counto = gen_reg_rtx (HImode);
  counto = gen_reg_rtx (HImode);
 
 
  if (GET_CODE (desta) != REG
  if (GET_CODE (desta) != REG
      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
    desta = copy_to_mode_reg (Pmode, desta);
    desta = copy_to_mode_reg (Pmode, desta);
 
 
  /* This looks like an arbitrary restriction, but this is by far the
  /* This looks like an arbitrary restriction, but this is by far the
     most common case.  For counts 8..14 this actually results in
     most common case.  For counts 8..14 this actually results in
     smaller code with no speed penalty because the half-sized
     smaller code with no speed penalty because the half-sized
     constant can be loaded with a shorter opcode.  */
     constant can be loaded with a shorter opcode.  */
  if (GET_CODE (count) == CONST_INT
  if (GET_CODE (count) == CONST_INT
      && GET_CODE (val) == CONST_INT
      && GET_CODE (val) == CONST_INT
      && ! (INTVAL (count) & 1)
      && ! (INTVAL (count) & 1)
      && (INTVAL (count) > 1)
      && (INTVAL (count) > 1)
      && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
      && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
    {
    {
      unsigned v = INTVAL (val) & 0xff;
      unsigned v = INTVAL (val) & 0xff;
      v = v | (v << 8);
      v = v | (v << 8);
      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
      val = copy_to_mode_reg (HImode, GEN_INT (v));
      val = copy_to_mode_reg (HImode, GEN_INT (v));
      if (TARGET_A16)
      if (TARGET_A16)
        emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
        emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
      else
      else
        emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
        emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
      return 1;
      return 1;
    }
    }
 
 
  /* This is the generalized memset() case.  */
  /* This is the generalized memset() case.  */
  if (GET_CODE (val) != REG
  if (GET_CODE (val) != REG
      || REGNO (val) < FIRST_PSEUDO_REGISTER)
      || REGNO (val) < FIRST_PSEUDO_REGISTER)
    val = copy_to_mode_reg (QImode, val);
    val = copy_to_mode_reg (QImode, val);
 
 
  if (GET_CODE (count) != REG
  if (GET_CODE (count) != REG
      || REGNO (count) < FIRST_PSEUDO_REGISTER)
      || REGNO (count) < FIRST_PSEUDO_REGISTER)
    count = copy_to_mode_reg (HImode, count);
    count = copy_to_mode_reg (HImode, count);
 
 
  if (TARGET_A16)
  if (TARGET_A16)
    emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
    emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
  else
  else
    emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
    emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
 
 
  return 1;
  return 1;
}
}
 
 
/* This is a memcpy() opcode.  All operands are implied, so we need to
/* This is a memcpy() opcode.  All operands are implied, so we need to
   arrange for them to be in the right registers.  The opcode wants
   arrange for them to be in the right registers.  The opcode wants
   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1
   addresses, not [mem] syntax.  $0 is the destination (MEM:BLK), $1
   is the source (MEM:BLK), and $2 the count (HI).  */
   is the source (MEM:BLK), and $2 the count (HI).  */
int
int
m32c_expand_movmemhi(rtx *operands)
m32c_expand_movmemhi(rtx *operands)
{
{
  rtx desta, srca, count;
  rtx desta, srca, count;
  rtx desto, srco, counto;
  rtx desto, srco, counto;
 
 
  desta = XEXP (operands[0], 0);
  desta = XEXP (operands[0], 0);
  srca = XEXP (operands[1], 0);
  srca = XEXP (operands[1], 0);
  count = operands[2];
  count = operands[2];
 
 
  desto = gen_reg_rtx (Pmode);
  desto = gen_reg_rtx (Pmode);
  srco = gen_reg_rtx (Pmode);
  srco = gen_reg_rtx (Pmode);
  counto = gen_reg_rtx (HImode);
  counto = gen_reg_rtx (HImode);
 
 
  if (GET_CODE (desta) != REG
  if (GET_CODE (desta) != REG
      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
    desta = copy_to_mode_reg (Pmode, desta);
    desta = copy_to_mode_reg (Pmode, desta);
 
 
  if (GET_CODE (srca) != REG
  if (GET_CODE (srca) != REG
      || REGNO (srca) < FIRST_PSEUDO_REGISTER)
      || REGNO (srca) < FIRST_PSEUDO_REGISTER)
    srca = copy_to_mode_reg (Pmode, srca);
    srca = copy_to_mode_reg (Pmode, srca);
 
 
  /* Similar to setmem, but we don't need to check the value.  */
  /* Similar to setmem, but we don't need to check the value.  */
  if (GET_CODE (count) == CONST_INT
  if (GET_CODE (count) == CONST_INT
      && ! (INTVAL (count) & 1)
      && ! (INTVAL (count) & 1)
      && (INTVAL (count) > 1))
      && (INTVAL (count) > 1))
    {
    {
      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
      count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
      if (TARGET_A16)
      if (TARGET_A16)
        emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
        emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
      else
      else
        emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
        emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
      return 1;
      return 1;
    }
    }
 
 
  /* This is the generalized memset() case.  */
  /* This is the generalized memset() case.  */
  if (GET_CODE (count) != REG
  if (GET_CODE (count) != REG
      || REGNO (count) < FIRST_PSEUDO_REGISTER)
      || REGNO (count) < FIRST_PSEUDO_REGISTER)
    count = copy_to_mode_reg (HImode, count);
    count = copy_to_mode_reg (HImode, count);
 
 
  if (TARGET_A16)
  if (TARGET_A16)
    emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
    emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
  else
  else
    emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
    emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
 
 
  return 1;
  return 1;
}
}
 
 
/* This is a stpcpy() opcode.  $0 is the destination (MEM:BLK) after
/* This is a stpcpy() opcode.  $0 is the destination (MEM:BLK) after
   the copy, which should point to the NUL at the end of the string,
   the copy, which should point to the NUL at the end of the string,
   $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
   $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
   Since our opcode leaves the destination pointing *after* the NUL,
   Since our opcode leaves the destination pointing *after* the NUL,
   we must emit an adjustment.  */
   we must emit an adjustment.  */
int
int
m32c_expand_movstr(rtx *operands)
m32c_expand_movstr(rtx *operands)
{
{
  rtx desta, srca;
  rtx desta, srca;
  rtx desto, srco;
  rtx desto, srco;
 
 
  desta = XEXP (operands[1], 0);
  desta = XEXP (operands[1], 0);
  srca = XEXP (operands[2], 0);
  srca = XEXP (operands[2], 0);
 
 
  desto = gen_reg_rtx (Pmode);
  desto = gen_reg_rtx (Pmode);
  srco = gen_reg_rtx (Pmode);
  srco = gen_reg_rtx (Pmode);
 
 
  if (GET_CODE (desta) != REG
  if (GET_CODE (desta) != REG
      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
      || REGNO (desta) < FIRST_PSEUDO_REGISTER)
    desta = copy_to_mode_reg (Pmode, desta);
    desta = copy_to_mode_reg (Pmode, desta);
 
 
  if (GET_CODE (srca) != REG
  if (GET_CODE (srca) != REG
      || REGNO (srca) < FIRST_PSEUDO_REGISTER)
      || REGNO (srca) < FIRST_PSEUDO_REGISTER)
    srca = copy_to_mode_reg (Pmode, srca);
    srca = copy_to_mode_reg (Pmode, srca);
 
 
  emit_insn (gen_movstr_op (desto, srco, desta, srca));
  emit_insn (gen_movstr_op (desto, srco, desta, srca));
  /* desto ends up being a1, which allows this type of add through MOVA.  */
  /* desto ends up being a1, which allows this type of add through MOVA.  */
  emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
  emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
 
 
  return 1;
  return 1;
}
}
 
 
/* This is a strcmp() opcode.  $0 is the destination (HI) which holds
/* This is a strcmp() opcode.  $0 is the destination (HI) which holds
   <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
   <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
   $2 is the other (MEM:BLK).  We must do the comparison, and then
   $2 is the other (MEM:BLK).  We must do the comparison, and then
   convert the flags to a signed integer result.  */
   convert the flags to a signed integer result.  */
int
int
m32c_expand_cmpstr(rtx *operands)
m32c_expand_cmpstr(rtx *operands)
{
{
  rtx src1a, src2a;
  rtx src1a, src2a;
 
 
  src1a = XEXP (operands[1], 0);
  src1a = XEXP (operands[1], 0);
  src2a = XEXP (operands[2], 0);
  src2a = XEXP (operands[2], 0);
 
 
  if (GET_CODE (src1a) != REG
  if (GET_CODE (src1a) != REG
      || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
      || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
    src1a = copy_to_mode_reg (Pmode, src1a);
    src1a = copy_to_mode_reg (Pmode, src1a);
 
 
  if (GET_CODE (src2a) != REG
  if (GET_CODE (src2a) != REG
      || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
      || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
    src2a = copy_to_mode_reg (Pmode, src2a);
    src2a = copy_to_mode_reg (Pmode, src2a);
 
 
  emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
  emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
  emit_insn (gen_cond_to_int (operands[0]));
  emit_insn (gen_cond_to_int (operands[0]));
 
 
  return 1;
  return 1;
}
}
 
 
 
 
typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
 
 
static shift_gen_func
static shift_gen_func
shift_gen_func_for (int mode, int code)
shift_gen_func_for (int mode, int code)
{
{
#define GFF(m,c,f) if (mode == m && code == c) return f
#define GFF(m,c,f) if (mode == m && code == c) return f
  GFF(QImode,  ASHIFT,   gen_ashlqi3_i);
  GFF(QImode,  ASHIFT,   gen_ashlqi3_i);
  GFF(QImode,  ASHIFTRT, gen_ashrqi3_i);
  GFF(QImode,  ASHIFTRT, gen_ashrqi3_i);
  GFF(QImode,  LSHIFTRT, gen_lshrqi3_i);
  GFF(QImode,  LSHIFTRT, gen_lshrqi3_i);
  GFF(HImode,  ASHIFT,   gen_ashlhi3_i);
  GFF(HImode,  ASHIFT,   gen_ashlhi3_i);
  GFF(HImode,  ASHIFTRT, gen_ashrhi3_i);
  GFF(HImode,  ASHIFTRT, gen_ashrhi3_i);
  GFF(HImode,  LSHIFTRT, gen_lshrhi3_i);
  GFF(HImode,  LSHIFTRT, gen_lshrhi3_i);
  GFF(PSImode, ASHIFT,   gen_ashlpsi3_i);
  GFF(PSImode, ASHIFT,   gen_ashlpsi3_i);
  GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
  GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
  GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
  GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
  GFF(SImode,  ASHIFT,   TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
  GFF(SImode,  ASHIFT,   TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
  GFF(SImode,  ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
  GFF(SImode,  ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
  GFF(SImode,  LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
  GFF(SImode,  LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
#undef GFF
#undef GFF
  gcc_unreachable ();
  gcc_unreachable ();
}
}
 
 
/* The m32c only has one shift, but it takes a signed count.  GCC
/* The m32c only has one shift, but it takes a signed count.  GCC
   doesn't want this, so we fake it by negating any shift count when
   doesn't want this, so we fake it by negating any shift count when
   we're pretending to shift the other way.  Also, the shift count is
   we're pretending to shift the other way.  Also, the shift count is
   limited to -8..8.  It's slightly better to use two shifts for 9..15
   limited to -8..8.  It's slightly better to use two shifts for 9..15
   than to load the count into r1h, so we do that too.  */
   than to load the count into r1h, so we do that too.  */
int
int
m32c_prepare_shift (rtx * operands, int scale, int shift_code)
m32c_prepare_shift (rtx * operands, int scale, int shift_code)
{
{
  enum machine_mode mode = GET_MODE (operands[0]);
  enum machine_mode mode = GET_MODE (operands[0]);
  shift_gen_func func = shift_gen_func_for (mode, shift_code);
  shift_gen_func func = shift_gen_func_for (mode, shift_code);
  rtx temp;
  rtx temp;
 
 
  if (GET_CODE (operands[2]) == CONST_INT)
  if (GET_CODE (operands[2]) == CONST_INT)
    {
    {
      int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
      int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
      int count = INTVAL (operands[2]) * scale;
      int count = INTVAL (operands[2]) * scale;
 
 
      while (count > maxc)
      while (count > maxc)
        {
        {
          temp = gen_reg_rtx (mode);
          temp = gen_reg_rtx (mode);
          emit_insn (func (temp, operands[1], GEN_INT (maxc)));
          emit_insn (func (temp, operands[1], GEN_INT (maxc)));
          operands[1] = temp;
          operands[1] = temp;
          count -= maxc;
          count -= maxc;
        }
        }
      while (count < -maxc)
      while (count < -maxc)
        {
        {
          temp = gen_reg_rtx (mode);
          temp = gen_reg_rtx (mode);
          emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
          emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
          operands[1] = temp;
          operands[1] = temp;
          count += maxc;
          count += maxc;
        }
        }
      emit_insn (func (operands[0], operands[1], GEN_INT (count)));
      emit_insn (func (operands[0], operands[1], GEN_INT (count)));
      return 1;
      return 1;
    }
    }
 
 
  temp = gen_reg_rtx (QImode);
  temp = gen_reg_rtx (QImode);
  if (scale < 0)
  if (scale < 0)
    /* The pattern has a NEG that corresponds to this. */
    /* The pattern has a NEG that corresponds to this. */
    emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
    emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
  else if (TARGET_A16 && mode == SImode)
  else if (TARGET_A16 && mode == SImode)
    /* We do this because the code below may modify this, we don't
    /* We do this because the code below may modify this, we don't
       want to modify the origin of this value.  */
       want to modify the origin of this value.  */
    emit_move_insn (temp, operands[2]);
    emit_move_insn (temp, operands[2]);
  else
  else
    /* We'll only use it for the shift, no point emitting a move.  */
    /* We'll only use it for the shift, no point emitting a move.  */
    temp = operands[2];
    temp = operands[2];
 
 
  if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
  if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
    {
    {
      /* The m16c has a limit of -16..16 for SI shifts, even when the
      /* The m16c has a limit of -16..16 for SI shifts, even when the
         shift count is in a register.  Since there are so many targets
         shift count is in a register.  Since there are so many targets
         of these shifts, it's better to expand the RTL here than to
         of these shifts, it's better to expand the RTL here than to
         call a helper function.
         call a helper function.
 
 
         The resulting code looks something like this:
         The resulting code looks something like this:
 
 
                cmp.b   r1h,-16
                cmp.b   r1h,-16
                jge.b   1f
                jge.b   1f
                shl.l   -16,dest
                shl.l   -16,dest
                add.b   r1h,16
                add.b   r1h,16
        1f:     cmp.b   r1h,16
        1f:     cmp.b   r1h,16
                jle.b   1f
                jle.b   1f
                shl.l   16,dest
                shl.l   16,dest
                sub.b   r1h,16
                sub.b   r1h,16
        1f:     shl.l   r1h,dest
        1f:     shl.l   r1h,dest
 
 
         We take advantage of the fact that "negative" shifts are
         We take advantage of the fact that "negative" shifts are
         undefined to skip one of the comparisons.  */
         undefined to skip one of the comparisons.  */
 
 
      rtx count;
      rtx count;
      rtx label, lref, insn, tempvar;
      rtx label, lref, insn, tempvar;
 
 
      emit_move_insn (operands[0], operands[1]);
      emit_move_insn (operands[0], operands[1]);
 
 
      count = temp;
      count = temp;
      label = gen_label_rtx ();
      label = gen_label_rtx ();
      lref = gen_rtx_LABEL_REF (VOIDmode, label);
      lref = gen_rtx_LABEL_REF (VOIDmode, label);
      LABEL_NUSES (label) ++;
      LABEL_NUSES (label) ++;
 
 
      tempvar = gen_reg_rtx (mode);
      tempvar = gen_reg_rtx (mode);
 
 
      if (shift_code == ASHIFT)
      if (shift_code == ASHIFT)
        {
        {
          /* This is a left shift.  We only need check positive counts.  */
          /* This is a left shift.  We only need check positive counts.  */
          emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
          emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
                                          count, GEN_INT (16), label));
                                          count, GEN_INT (16), label));
          emit_insn (func (tempvar, operands[0], GEN_INT (8)));
          emit_insn (func (tempvar, operands[0], GEN_INT (8)));
          emit_insn (func (operands[0], tempvar, GEN_INT (8)));
          emit_insn (func (operands[0], tempvar, GEN_INT (8)));
          insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
          insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
          emit_label_after (label, insn);
          emit_label_after (label, insn);
        }
        }
      else
      else
        {
        {
          /* This is a right shift.  We only need check negative counts.  */
          /* This is a right shift.  We only need check negative counts.  */
          emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
          emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
                                          count, GEN_INT (-16), label));
                                          count, GEN_INT (-16), label));
          emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
          emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
          emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
          emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
          insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
          insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
          emit_label_after (label, insn);
          emit_label_after (label, insn);
        }
        }
      operands[1] = operands[0];
      operands[1] = operands[0];
      emit_insn (func (operands[0], operands[0], count));
      emit_insn (func (operands[0], operands[0], count));
      return 1;
      return 1;
    }
    }
 
 
  operands[2] = temp;
  operands[2] = temp;
  return 0;
  return 0;
}
}
 
 
/* The m32c has a limited range of operations that work on PSImode
/* The m32c has a limited range of operations that work on PSImode
   values; we have to expand to SI, do the math, and truncate back to
   values; we have to expand to SI, do the math, and truncate back to
   PSI.  Yes, this is expensive, but hopefully gcc will learn to avoid
   PSI.  Yes, this is expensive, but hopefully gcc will learn to avoid
   those cases.  */
   those cases.  */
void
void
m32c_expand_neg_mulpsi3 (rtx * operands)
m32c_expand_neg_mulpsi3 (rtx * operands)
{
{
  /* operands: a = b * i */
  /* operands: a = b * i */
  rtx temp1; /* b as SI */
  rtx temp1; /* b as SI */
  rtx scale /* i as SI */;
  rtx scale /* i as SI */;
  rtx temp2; /* a*b as SI */
  rtx temp2; /* a*b as SI */
 
 
  temp1 = gen_reg_rtx (SImode);
  temp1 = gen_reg_rtx (SImode);
  temp2 = gen_reg_rtx (SImode);
  temp2 = gen_reg_rtx (SImode);
  if (GET_CODE (operands[2]) != CONST_INT)
  if (GET_CODE (operands[2]) != CONST_INT)
    {
    {
      scale = gen_reg_rtx (SImode);
      scale = gen_reg_rtx (SImode);
      emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
      emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
    }
    }
  else
  else
    scale = copy_to_mode_reg (SImode, operands[2]);
    scale = copy_to_mode_reg (SImode, operands[2]);
 
 
  emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
  emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
  temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
  temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
  emit_insn (gen_truncsipsi2 (operands[0], temp2));
  emit_insn (gen_truncsipsi2 (operands[0], temp2));
}
}
 
 
/* Pattern Output Functions */
/* Pattern Output Functions */
 
 
int
int
m32c_expand_movcc (rtx *operands)
m32c_expand_movcc (rtx *operands)
{
{
  rtx rel = operands[1];
  rtx rel = operands[1];
  rtx cmp;
  rtx cmp;
 
 
  if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
  if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
    return 1;
    return 1;
  if (GET_CODE (operands[2]) != CONST_INT
  if (GET_CODE (operands[2]) != CONST_INT
      || GET_CODE (operands[3]) != CONST_INT)
      || GET_CODE (operands[3]) != CONST_INT)
    return 1;
    return 1;
  if (GET_CODE (rel) == NE)
  if (GET_CODE (rel) == NE)
    {
    {
      rtx tmp = operands[2];
      rtx tmp = operands[2];
      operands[2] = operands[3];
      operands[2] = operands[3];
      operands[3] = tmp;
      operands[3] = tmp;
      rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
      rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
    }
    }
 
 
  emit_move_insn (operands[0],
  emit_move_insn (operands[0],
                  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
                  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
                                        rel,
                                        rel,
                                        operands[2],
                                        operands[2],
                                        operands[3]));
                                        operands[3]));
  return 0;
  return 0;
}
}
 
 
/* Used for the "insv" pattern.  Return nonzero to fail, else done.  */
/* Used for the "insv" pattern.  Return nonzero to fail, else done.  */
int
int
m32c_expand_insv (rtx *operands)
m32c_expand_insv (rtx *operands)
{
{
  rtx op0, src0, p;
  rtx op0, src0, p;
  int mask;
  int mask;
 
 
  if (INTVAL (operands[1]) != 1)
  if (INTVAL (operands[1]) != 1)
    return 1;
    return 1;
 
 
  /* Our insv opcode (bset, bclr) can only insert a one-bit constant.  */
  /* Our insv opcode (bset, bclr) can only insert a one-bit constant.  */
  if (GET_CODE (operands[3]) != CONST_INT)
  if (GET_CODE (operands[3]) != CONST_INT)
    return 1;
    return 1;
  if (INTVAL (operands[3]) != 0
  if (INTVAL (operands[3]) != 0
      && INTVAL (operands[3]) != 1
      && INTVAL (operands[3]) != 1
      && INTVAL (operands[3]) != -1)
      && INTVAL (operands[3]) != -1)
    return 1;
    return 1;
 
 
  mask = 1 << INTVAL (operands[2]);
  mask = 1 << INTVAL (operands[2]);
 
 
  op0 = operands[0];
  op0 = operands[0];
  if (GET_CODE (op0) == SUBREG
  if (GET_CODE (op0) == SUBREG
      && SUBREG_BYTE (op0) == 0)
      && SUBREG_BYTE (op0) == 0)
    {
    {
      rtx sub = SUBREG_REG (op0);
      rtx sub = SUBREG_REG (op0);
      if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
      if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
        op0 = sub;
        op0 = sub;
    }
    }
 
 
  if (!can_create_pseudo_p ()
  if (!can_create_pseudo_p ()
      || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
      || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
    src0 = op0;
    src0 = op0;
  else
  else
    {
    {
      src0 = gen_reg_rtx (GET_MODE (op0));
      src0 = gen_reg_rtx (GET_MODE (op0));
      emit_move_insn (src0, op0);
      emit_move_insn (src0, op0);
    }
    }
 
 
  if (GET_MODE (op0) == HImode
  if (GET_MODE (op0) == HImode
      && INTVAL (operands[2]) >= 8
      && INTVAL (operands[2]) >= 8
      && GET_MODE (op0) == MEM)
      && GET_MODE (op0) == MEM)
    {
    {
      /* We are little endian.  */
      /* We are little endian.  */
      rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
      rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
      MEM_COPY_ATTRIBUTES (new_mem, op0);
      MEM_COPY_ATTRIBUTES (new_mem, op0);
      mask >>= 8;
      mask >>= 8;
    }
    }
 
 
  /* First, we generate a mask with the correct polarity.  If we are
  /* First, we generate a mask with the correct polarity.  If we are
     storing a zero, we want an AND mask, so invert it.  */
     storing a zero, we want an AND mask, so invert it.  */
  if (INTVAL (operands[3]) == 0)
  if (INTVAL (operands[3]) == 0)
    {
    {
      /* Storing a zero, use an AND mask */
      /* Storing a zero, use an AND mask */
      if (GET_MODE (op0) == HImode)
      if (GET_MODE (op0) == HImode)
        mask ^= 0xffff;
        mask ^= 0xffff;
      else
      else
        mask ^= 0xff;
        mask ^= 0xff;
    }
    }
  /* Now we need to properly sign-extend the mask in case we need to
  /* Now we need to properly sign-extend the mask in case we need to
     fall back to an AND or OR opcode.  */
     fall back to an AND or OR opcode.  */
  if (GET_MODE (op0) == HImode)
  if (GET_MODE (op0) == HImode)
    {
    {
      if (mask & 0x8000)
      if (mask & 0x8000)
        mask -= 0x10000;
        mask -= 0x10000;
    }
    }
  else
  else
    {
    {
      if (mask & 0x80)
      if (mask & 0x80)
        mask -= 0x100;
        mask -= 0x100;
    }
    }
 
 
  switch (  (INTVAL (operands[3]) ? 4 : 0)
  switch (  (INTVAL (operands[3]) ? 4 : 0)
          + ((GET_MODE (op0) == HImode) ? 2 : 0)
          + ((GET_MODE (op0) == HImode) ? 2 : 0)
          + (TARGET_A24 ? 1 : 0))
          + (TARGET_A24 ? 1 : 0))
    {
    {
    case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
    case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
    case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
    case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
    case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
    case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
    case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
    case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
    case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
    case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
    case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
    case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
    case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
    case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
    case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
    case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
    default: p = NULL_RTX; break; /* Not reached, but silences a warning.  */
    default: p = NULL_RTX; break; /* Not reached, but silences a warning.  */
    }
    }
 
 
  emit_insn (p);
  emit_insn (p);
  return 0;
  return 0;
}
}
 
 
const char *
const char *
m32c_scc_pattern(rtx *operands, RTX_CODE code)
m32c_scc_pattern(rtx *operands, RTX_CODE code)
{
{
  static char buf[30];
  static char buf[30];
  if (GET_CODE (operands[0]) == REG
  if (GET_CODE (operands[0]) == REG
      && REGNO (operands[0]) == R0_REGNO)
      && REGNO (operands[0]) == R0_REGNO)
    {
    {
      if (code == EQ)
      if (code == EQ)
        return "stzx\t#1,#0,r0l";
        return "stzx\t#1,#0,r0l";
      if (code == NE)
      if (code == NE)
        return "stzx\t#0,#1,r0l";
        return "stzx\t#0,#1,r0l";
    }
    }
  sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
  sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
  return buf;
  return buf;
}
}
 
 
/* Encode symbol attributes of a SYMBOL_REF into its
/* Encode symbol attributes of a SYMBOL_REF into its
   SYMBOL_REF_FLAGS. */
   SYMBOL_REF_FLAGS. */
static void
static void
m32c_encode_section_info (tree decl, rtx rtl, int first)
m32c_encode_section_info (tree decl, rtx rtl, int first)
{
{
  int extra_flags = 0;
  int extra_flags = 0;
 
 
  default_encode_section_info (decl, rtl, first);
  default_encode_section_info (decl, rtl, first);
  if (TREE_CODE (decl) == FUNCTION_DECL
  if (TREE_CODE (decl) == FUNCTION_DECL
      && m32c_special_page_vector_p (decl))
      && m32c_special_page_vector_p (decl))
 
 
    extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
    extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
 
 
  if (extra_flags)
  if (extra_flags)
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
}
}
 
 
/* Returns TRUE if the current function is a leaf, and thus we can
/* Returns TRUE if the current function is a leaf, and thus we can
   determine which registers an interrupt function really needs to
   determine which registers an interrupt function really needs to
   save.  The logic below is mostly about finding the insn sequence
   save.  The logic below is mostly about finding the insn sequence
   that's the function, versus any sequence that might be open for the
   that's the function, versus any sequence that might be open for the
   current insn.  */
   current insn.  */
static int
static int
m32c_leaf_function_p (void)
m32c_leaf_function_p (void)
{
{
  rtx saved_first, saved_last;
  rtx saved_first, saved_last;
  struct sequence_stack *seq;
  struct sequence_stack *seq;
  int rv;
  int rv;
 
 
  saved_first = crtl->emit.x_first_insn;
  saved_first = crtl->emit.x_first_insn;
  saved_last = crtl->emit.x_last_insn;
  saved_last = crtl->emit.x_last_insn;
  for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
  for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
    ;
    ;
  if (seq)
  if (seq)
    {
    {
      crtl->emit.x_first_insn = seq->first;
      crtl->emit.x_first_insn = seq->first;
      crtl->emit.x_last_insn = seq->last;
      crtl->emit.x_last_insn = seq->last;
    }
    }
 
 
  rv = leaf_function_p ();
  rv = leaf_function_p ();
 
 
  crtl->emit.x_first_insn = saved_first;
  crtl->emit.x_first_insn = saved_first;
  crtl->emit.x_last_insn = saved_last;
  crtl->emit.x_last_insn = saved_last;
  return rv;
  return rv;
}
}
 
 
/* Returns TRUE if the current function needs to use the ENTER/EXIT
/* Returns TRUE if the current function needs to use the ENTER/EXIT
   opcodes.  If the function doesn't need the frame base or stack
   opcodes.  If the function doesn't need the frame base or stack
   pointer, it can use the simpler RTS opcode.  */
   pointer, it can use the simpler RTS opcode.  */
static bool
static bool
m32c_function_needs_enter (void)
m32c_function_needs_enter (void)
{
{
  rtx insn;
  rtx insn;
  struct sequence_stack *seq;
  struct sequence_stack *seq;
  rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
  rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
  rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
  rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
 
 
  insn = get_insns ();
  insn = get_insns ();
  for (seq = crtl->emit.sequence_stack;
  for (seq = crtl->emit.sequence_stack;
       seq;
       seq;
       insn = seq->first, seq = seq->next);
       insn = seq->first, seq = seq->next);
 
 
  while (insn)
  while (insn)
    {
    {
      if (reg_mentioned_p (sp, insn))
      if (reg_mentioned_p (sp, insn))
        return true;
        return true;
      if (reg_mentioned_p (fb, insn))
      if (reg_mentioned_p (fb, insn))
        return true;
        return true;
      insn = NEXT_INSN (insn);
      insn = NEXT_INSN (insn);
    }
    }
  return false;
  return false;
}
}
 
 
/* Mark all the subexpressions of the PARALLEL rtx PAR as
/* Mark all the subexpressions of the PARALLEL rtx PAR as
   frame-related.  Return PAR.
   frame-related.  Return PAR.
 
 
   dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
   dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
   PARALLEL rtx other than the first if they do not have the
   PARALLEL rtx other than the first if they do not have the
   FRAME_RELATED flag set on them.  So this function is handy for
   FRAME_RELATED flag set on them.  So this function is handy for
   marking up 'enter' instructions.  */
   marking up 'enter' instructions.  */
static rtx
static rtx
m32c_all_frame_related (rtx par)
m32c_all_frame_related (rtx par)
{
{
  int len = XVECLEN (par, 0);
  int len = XVECLEN (par, 0);
  int i;
  int i;
 
 
  for (i = 0; i < len; i++)
  for (i = 0; i < len; i++)
    F (XVECEXP (par, 0, i));
    F (XVECEXP (par, 0, i));
 
 
  return par;
  return par;
}
}
 
 
/* Emits the prologue.  See the frame layout comment earlier in this
/* Emits the prologue.  See the frame layout comment earlier in this
   file.  We can reserve up to 256 bytes with the ENTER opcode, beyond
   file.  We can reserve up to 256 bytes with the ENTER opcode, beyond
   that we manually update sp.  */
   that we manually update sp.  */
void
void
m32c_emit_prologue (void)
m32c_emit_prologue (void)
{
{
  int frame_size, extra_frame_size = 0, reg_save_size;
  int frame_size, extra_frame_size = 0, reg_save_size;
  int complex_prologue = 0;
  int complex_prologue = 0;
 
 
  cfun->machine->is_leaf = m32c_leaf_function_p ();
  cfun->machine->is_leaf = m32c_leaf_function_p ();
  if (interrupt_p (cfun->decl))
  if (interrupt_p (cfun->decl))
    {
    {
      cfun->machine->is_interrupt = 1;
      cfun->machine->is_interrupt = 1;
      complex_prologue = 1;
      complex_prologue = 1;
    }
    }
  else if (bank_switch_p (cfun->decl))
  else if (bank_switch_p (cfun->decl))
    warning (OPT_Wattributes,
    warning (OPT_Wattributes,
             "%<bank_switch%> has no effect on non-interrupt functions");
             "%<bank_switch%> has no effect on non-interrupt functions");
 
 
  reg_save_size = m32c_pushm_popm (PP_justcount);
  reg_save_size = m32c_pushm_popm (PP_justcount);
 
 
  if (interrupt_p (cfun->decl))
  if (interrupt_p (cfun->decl))
    {
    {
      if (bank_switch_p (cfun->decl))
      if (bank_switch_p (cfun->decl))
        emit_insn (gen_fset_b ());
        emit_insn (gen_fset_b ());
      else if (cfun->machine->intr_pushm)
      else if (cfun->machine->intr_pushm)
        emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
        emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
    }
    }
 
 
  frame_size =
  frame_size =
    m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
    m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
  if (frame_size == 0
  if (frame_size == 0
      && !m32c_function_needs_enter ())
      && !m32c_function_needs_enter ())
    cfun->machine->use_rts = 1;
    cfun->machine->use_rts = 1;
 
 
  if (frame_size > 254)
  if (frame_size > 254)
    {
    {
      extra_frame_size = frame_size - 254;
      extra_frame_size = frame_size - 254;
      frame_size = 254;
      frame_size = 254;
    }
    }
  if (cfun->machine->use_rts == 0)
  if (cfun->machine->use_rts == 0)
    F (emit_insn (m32c_all_frame_related
    F (emit_insn (m32c_all_frame_related
                  (TARGET_A16
                  (TARGET_A16
                   ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
                   ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
                   : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
                   : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
 
 
  if (extra_frame_size)
  if (extra_frame_size)
    {
    {
      complex_prologue = 1;
      complex_prologue = 1;
      if (TARGET_A16)
      if (TARGET_A16)
        F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
        F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
                                  gen_rtx_REG (HImode, SP_REGNO),
                                  gen_rtx_REG (HImode, SP_REGNO),
                                  GEN_INT (-extra_frame_size))));
                                  GEN_INT (-extra_frame_size))));
      else
      else
        F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
        F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
                                   gen_rtx_REG (PSImode, SP_REGNO),
                                   gen_rtx_REG (PSImode, SP_REGNO),
                                   GEN_INT (-extra_frame_size))));
                                   GEN_INT (-extra_frame_size))));
    }
    }
 
 
  complex_prologue += m32c_pushm_popm (PP_pushm);
  complex_prologue += m32c_pushm_popm (PP_pushm);
 
 
  /* This just emits a comment into the .s file for debugging.  */
  /* This just emits a comment into the .s file for debugging.  */
  if (complex_prologue)
  if (complex_prologue)
    emit_insn (gen_prologue_end ());
    emit_insn (gen_prologue_end ());
}
}
 
 
/* Likewise, for the epilogue.  The only exception is that, for
/* Likewise, for the epilogue.  The only exception is that, for
   interrupts, we must manually unwind the frame as the REIT opcode
   interrupts, we must manually unwind the frame as the REIT opcode
   doesn't do that.  */
   doesn't do that.  */
void
void
m32c_emit_epilogue (void)
m32c_emit_epilogue (void)
{
{
  /* This just emits a comment into the .s file for debugging.  */
  /* This just emits a comment into the .s file for debugging.  */
  if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
  if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
    emit_insn (gen_epilogue_start ());
    emit_insn (gen_epilogue_start ());
 
 
  m32c_pushm_popm (PP_popm);
  m32c_pushm_popm (PP_popm);
 
 
  if (cfun->machine->is_interrupt)
  if (cfun->machine->is_interrupt)
    {
    {
      enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
      enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
 
 
      /* REIT clears B flag and restores $fp for us, but we still
      /* REIT clears B flag and restores $fp for us, but we still
         have to fix up the stack.  USE_RTS just means we didn't
         have to fix up the stack.  USE_RTS just means we didn't
         emit ENTER.  */
         emit ENTER.  */
      if (!cfun->machine->use_rts)
      if (!cfun->machine->use_rts)
        {
        {
          emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
          emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
                          gen_rtx_REG (spmode, FP_REGNO));
                          gen_rtx_REG (spmode, FP_REGNO));
          emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
          emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
                          gen_rtx_REG (spmode, A0_REGNO));
                          gen_rtx_REG (spmode, A0_REGNO));
          /* We can't just add this to the POPM because it would be in
          /* We can't just add this to the POPM because it would be in
             the wrong order, and wouldn't fix the stack if we're bank
             the wrong order, and wouldn't fix the stack if we're bank
             switching.  */
             switching.  */
          if (TARGET_A16)
          if (TARGET_A16)
            emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
            emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
          else
          else
            emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
            emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
        }
        }
      if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)
      if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)
        emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
        emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
 
 
      /* The FREIT (Fast REturn from InTerrupt) instruction should be
      /* The FREIT (Fast REturn from InTerrupt) instruction should be
         generated only for M32C/M32CM targets (generate the REIT
         generated only for M32C/M32CM targets (generate the REIT
         instruction otherwise).  */
         instruction otherwise).  */
      if (fast_interrupt_p (cfun->decl))
      if (fast_interrupt_p (cfun->decl))
        {
        {
          /* Check if fast_attribute is set for M32C or M32CM.  */
          /* Check if fast_attribute is set for M32C or M32CM.  */
          if (TARGET_A24)
          if (TARGET_A24)
            {
            {
              emit_jump_insn (gen_epilogue_freit ());
              emit_jump_insn (gen_epilogue_freit ());
            }
            }
          /* If fast_interrupt attribute is set for an R8C or M16C
          /* If fast_interrupt attribute is set for an R8C or M16C
             target ignore this attribute and generated REIT
             target ignore this attribute and generated REIT
             instruction.  */
             instruction.  */
          else
          else
            {
            {
              warning (OPT_Wattributes,
              warning (OPT_Wattributes,
                       "%<fast_interrupt%> attribute directive ignored");
                       "%<fast_interrupt%> attribute directive ignored");
              emit_jump_insn (gen_epilogue_reit_16 ());
              emit_jump_insn (gen_epilogue_reit_16 ());
            }
            }
        }
        }
      else if (TARGET_A16)
      else if (TARGET_A16)
        emit_jump_insn (gen_epilogue_reit_16 ());
        emit_jump_insn (gen_epilogue_reit_16 ());
      else
      else
        emit_jump_insn (gen_epilogue_reit_24 ());
        emit_jump_insn (gen_epilogue_reit_24 ());
    }
    }
  else if (cfun->machine->use_rts)
  else if (cfun->machine->use_rts)
    emit_jump_insn (gen_epilogue_rts ());
    emit_jump_insn (gen_epilogue_rts ());
  else if (TARGET_A16)
  else if (TARGET_A16)
    emit_jump_insn (gen_epilogue_exitd_16 ());
    emit_jump_insn (gen_epilogue_exitd_16 ());
  else
  else
    emit_jump_insn (gen_epilogue_exitd_24 ());
    emit_jump_insn (gen_epilogue_exitd_24 ());
  emit_barrier ();
  emit_barrier ();
}
}
 
 
void
void
m32c_emit_eh_epilogue (rtx ret_addr)
m32c_emit_eh_epilogue (rtx ret_addr)
{
{
  /* R0[R2] has the stack adjustment.  R1[R3] has the address to
  /* R0[R2] has the stack adjustment.  R1[R3] has the address to
     return to.  We have to fudge the stack, pop everything, pop SP
     return to.  We have to fudge the stack, pop everything, pop SP
     (fudged), and return (fudged).  This is actually easier to do in
     (fudged), and return (fudged).  This is actually easier to do in
     assembler, so punt to libgcc.  */
     assembler, so punt to libgcc.  */
  emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
  emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
  /*  emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
  /*  emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
  emit_barrier ();
  emit_barrier ();
}
}
 
 
/* Indicate which flags must be properly set for a given conditional.  */
/* Indicate which flags must be properly set for a given conditional.  */
static int
static int
flags_needed_for_conditional (rtx cond)
flags_needed_for_conditional (rtx cond)
{
{
  switch (GET_CODE (cond))
  switch (GET_CODE (cond))
    {
    {
    case LE:
    case LE:
    case GT:
    case GT:
      return FLAGS_OSZ;
      return FLAGS_OSZ;
    case LEU:
    case LEU:
    case GTU:
    case GTU:
      return FLAGS_ZC;
      return FLAGS_ZC;
    case LT:
    case LT:
    case GE:
    case GE:
      return FLAGS_OS;
      return FLAGS_OS;
    case LTU:
    case LTU:
    case GEU:
    case GEU:
      return FLAGS_C;
      return FLAGS_C;
    case EQ:
    case EQ:
    case NE:
    case NE:
      return FLAGS_Z;
      return FLAGS_Z;
    default:
    default:
      return FLAGS_N;
      return FLAGS_N;
    }
    }
}
}
 
 
#define DEBUG_CMP 0
#define DEBUG_CMP 0
 
 
/* Returns true if a compare insn is redundant because it would only
/* Returns true if a compare insn is redundant because it would only
   set flags that are already set correctly.  */
   set flags that are already set correctly.  */
static bool
static bool
m32c_compare_redundant (rtx cmp, rtx *operands)
m32c_compare_redundant (rtx cmp, rtx *operands)
{
{
  int flags_needed;
  int flags_needed;
  int pflags;
  int pflags;
  rtx prev, pp, next;
  rtx prev, pp, next;
  rtx op0, op1, op2;
  rtx op0, op1, op2;
#if DEBUG_CMP
#if DEBUG_CMP
  int prev_icode, i;
  int prev_icode, i;
#endif
#endif
 
 
  op0 = operands[0];
  op0 = operands[0];
  op1 = operands[1];
  op1 = operands[1];
  op2 = operands[2];
  op2 = operands[2];
 
 
#if DEBUG_CMP
#if DEBUG_CMP
  fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
  fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
  debug_rtx(cmp);
  debug_rtx(cmp);
  for (i=0; i<2; i++)
  for (i=0; i<2; i++)
    {
    {
      fprintf(stderr, "operands[%d] = ", i);
      fprintf(stderr, "operands[%d] = ", i);
      debug_rtx(operands[i]);
      debug_rtx(operands[i]);
    }
    }
#endif
#endif
 
 
  next = next_nonnote_insn (cmp);
  next = next_nonnote_insn (cmp);
  if (!next || !INSN_P (next))
  if (!next || !INSN_P (next))
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "compare not followed by insn\n");
      fprintf(stderr, "compare not followed by insn\n");
      debug_rtx(next);
      debug_rtx(next);
#endif
#endif
      return false;
      return false;
    }
    }
  if (GET_CODE (PATTERN (next)) == SET
  if (GET_CODE (PATTERN (next)) == SET
      && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
      && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
    {
    {
      next = XEXP (XEXP (PATTERN (next), 1), 0);
      next = XEXP (XEXP (PATTERN (next), 1), 0);
    }
    }
  else if (GET_CODE (PATTERN (next)) == SET)
  else if (GET_CODE (PATTERN (next)) == SET)
    {
    {
      /* If this is a conditional, flags_needed will be something
      /* If this is a conditional, flags_needed will be something
         other than FLAGS_N, which we test below.  */
         other than FLAGS_N, which we test below.  */
      next = XEXP (PATTERN (next), 1);
      next = XEXP (PATTERN (next), 1);
    }
    }
  else
  else
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "compare not followed by conditional\n");
      fprintf(stderr, "compare not followed by conditional\n");
      debug_rtx(next);
      debug_rtx(next);
#endif
#endif
      return false;
      return false;
    }
    }
#if DEBUG_CMP
#if DEBUG_CMP
  fprintf(stderr, "conditional is: ");
  fprintf(stderr, "conditional is: ");
  debug_rtx(next);
  debug_rtx(next);
#endif
#endif
 
 
  flags_needed = flags_needed_for_conditional (next);
  flags_needed = flags_needed_for_conditional (next);
  if (flags_needed == FLAGS_N)
  if (flags_needed == FLAGS_N)
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "compare not followed by conditional\n");
      fprintf(stderr, "compare not followed by conditional\n");
      debug_rtx(next);
      debug_rtx(next);
#endif
#endif
      return false;
      return false;
    }
    }
 
 
  /* Compare doesn't set overflow and carry the same way that
  /* Compare doesn't set overflow and carry the same way that
     arithmetic instructions do, so we can't replace those.  */
     arithmetic instructions do, so we can't replace those.  */
  if (flags_needed & FLAGS_OC)
  if (flags_needed & FLAGS_OC)
    return false;
    return false;
 
 
  prev = cmp;
  prev = cmp;
  do {
  do {
    prev = prev_nonnote_insn (prev);
    prev = prev_nonnote_insn (prev);
    if (!prev)
    if (!prev)
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "No previous insn.\n");
        fprintf(stderr, "No previous insn.\n");
#endif
#endif
        return false;
        return false;
      }
      }
    if (!INSN_P (prev))
    if (!INSN_P (prev))
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "Previous insn is a non-insn.\n");
        fprintf(stderr, "Previous insn is a non-insn.\n");
#endif
#endif
        return false;
        return false;
      }
      }
    pp = PATTERN (prev);
    pp = PATTERN (prev);
    if (GET_CODE (pp) != SET)
    if (GET_CODE (pp) != SET)
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "Previous insn is not a SET.\n");
        fprintf(stderr, "Previous insn is not a SET.\n");
#endif
#endif
        return false;
        return false;
      }
      }
    pflags = get_attr_flags (prev);
    pflags = get_attr_flags (prev);
 
 
    /* Looking up attributes of previous insns corrupted the recog
    /* Looking up attributes of previous insns corrupted the recog
       tables.  */
       tables.  */
    INSN_UID (cmp) = -1;
    INSN_UID (cmp) = -1;
    recog (PATTERN (cmp), cmp, 0);
    recog (PATTERN (cmp), cmp, 0);
 
 
    if (pflags == FLAGS_N
    if (pflags == FLAGS_N
        && reg_mentioned_p (op0, pp))
        && reg_mentioned_p (op0, pp))
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "intermediate non-flags insn uses op:\n");
        fprintf(stderr, "intermediate non-flags insn uses op:\n");
        debug_rtx(prev);
        debug_rtx(prev);
#endif
#endif
        return false;
        return false;
      }
      }
 
 
    /* Check for comparisons against memory - between volatiles and
    /* Check for comparisons against memory - between volatiles and
       aliases, we just can't risk this one.  */
       aliases, we just can't risk this one.  */
    if (GET_CODE (operands[0]) == MEM
    if (GET_CODE (operands[0]) == MEM
        || GET_CODE (operands[0]) == MEM)
        || GET_CODE (operands[0]) == MEM)
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "comparisons with memory:\n");
        fprintf(stderr, "comparisons with memory:\n");
        debug_rtx(prev);
        debug_rtx(prev);
#endif
#endif
        return false;
        return false;
      }
      }
 
 
    /* Check for PREV changing a register that's used to compute a
    /* Check for PREV changing a register that's used to compute a
       value in CMP, even if it doesn't otherwise change flags.  */
       value in CMP, even if it doesn't otherwise change flags.  */
    if (GET_CODE (operands[0]) == REG
    if (GET_CODE (operands[0]) == REG
        && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
        && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "sub-value affected, op0:\n");
        fprintf(stderr, "sub-value affected, op0:\n");
        debug_rtx(prev);
        debug_rtx(prev);
#endif
#endif
        return false;
        return false;
      }
      }
    if (GET_CODE (operands[1]) == REG
    if (GET_CODE (operands[1]) == REG
        && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
        && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
      {
      {
#if DEBUG_CMP
#if DEBUG_CMP
        fprintf(stderr, "sub-value affected, op1:\n");
        fprintf(stderr, "sub-value affected, op1:\n");
        debug_rtx(prev);
        debug_rtx(prev);
#endif
#endif
        return false;
        return false;
      }
      }
 
 
  } while (pflags == FLAGS_N);
  } while (pflags == FLAGS_N);
#if DEBUG_CMP
#if DEBUG_CMP
  fprintf(stderr, "previous flag-setting insn:\n");
  fprintf(stderr, "previous flag-setting insn:\n");
  debug_rtx(prev);
  debug_rtx(prev);
  debug_rtx(pp);
  debug_rtx(pp);
#endif
#endif
 
 
  if (GET_CODE (pp) == SET
  if (GET_CODE (pp) == SET
      && GET_CODE (XEXP (pp, 0)) == REG
      && GET_CODE (XEXP (pp, 0)) == REG
      && REGNO (XEXP (pp, 0)) == FLG_REGNO
      && REGNO (XEXP (pp, 0)) == FLG_REGNO
      && GET_CODE (XEXP (pp, 1)) == COMPARE)
      && GET_CODE (XEXP (pp, 1)) == COMPARE)
    {
    {
      /* Adjacent cbranches must have the same operands to be
      /* Adjacent cbranches must have the same operands to be
         redundant.  */
         redundant.  */
      rtx pop0 = XEXP (XEXP (pp, 1), 0);
      rtx pop0 = XEXP (XEXP (pp, 1), 0);
      rtx pop1 = XEXP (XEXP (pp, 1), 1);
      rtx pop1 = XEXP (XEXP (pp, 1), 1);
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "adjacent cbranches\n");
      fprintf(stderr, "adjacent cbranches\n");
      debug_rtx(pop0);
      debug_rtx(pop0);
      debug_rtx(pop1);
      debug_rtx(pop1);
#endif
#endif
      if (rtx_equal_p (op0, pop0)
      if (rtx_equal_p (op0, pop0)
          && rtx_equal_p (op1, pop1))
          && rtx_equal_p (op1, pop1))
        return true;
        return true;
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "prev cmp not same\n");
      fprintf(stderr, "prev cmp not same\n");
#endif
#endif
      return false;
      return false;
    }
    }
 
 
  /* Else the previous insn must be a SET, with either the source or
  /* Else the previous insn must be a SET, with either the source or
     dest equal to operands[0], and operands[1] must be zero.  */
     dest equal to operands[0], and operands[1] must be zero.  */
 
 
  if (!rtx_equal_p (op1, const0_rtx))
  if (!rtx_equal_p (op1, const0_rtx))
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "operands[1] not const0_rtx\n");
      fprintf(stderr, "operands[1] not const0_rtx\n");
#endif
#endif
      return false;
      return false;
    }
    }
  if (GET_CODE (pp) != SET)
  if (GET_CODE (pp) != SET)
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf (stderr, "pp not set\n");
      fprintf (stderr, "pp not set\n");
#endif
#endif
      return false;
      return false;
    }
    }
  if (!rtx_equal_p (op0, SET_SRC (pp))
  if (!rtx_equal_p (op0, SET_SRC (pp))
      && !rtx_equal_p (op0, SET_DEST (pp)))
      && !rtx_equal_p (op0, SET_DEST (pp)))
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "operands[0] not found in set\n");
      fprintf(stderr, "operands[0] not found in set\n");
#endif
#endif
      return false;
      return false;
    }
    }
 
 
#if DEBUG_CMP
#if DEBUG_CMP
  fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
  fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
#endif
#endif
  if ((pflags & flags_needed) == flags_needed)
  if ((pflags & flags_needed) == flags_needed)
    return true;
    return true;
 
 
  return false;
  return false;
}
}
 
 
/* Return the pattern for a compare.  This will be commented out if
/* Return the pattern for a compare.  This will be commented out if
   the compare is redundant, else a normal pattern is returned.  Thus,
   the compare is redundant, else a normal pattern is returned.  Thus,
   the assembler output says where the compare would have been.  */
   the assembler output says where the compare would have been.  */
char *
char *
m32c_output_compare (rtx insn, rtx *operands)
m32c_output_compare (rtx insn, rtx *operands)
{
{
  static char templ[] = ";cmp.b\t%1,%0";
  static char templ[] = ";cmp.b\t%1,%0";
  /*                             ^ 5  */
  /*                             ^ 5  */
 
 
  templ[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
  templ[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
  if (m32c_compare_redundant (insn, operands))
  if (m32c_compare_redundant (insn, operands))
    {
    {
#if DEBUG_CMP
#if DEBUG_CMP
      fprintf(stderr, "cbranch: cmp not needed\n");
      fprintf(stderr, "cbranch: cmp not needed\n");
#endif
#endif
      return templ;
      return templ;
    }
    }
 
 
#if DEBUG_CMP
#if DEBUG_CMP
  fprintf(stderr, "cbranch: cmp needed: `%s'\n", templ + 1);
  fprintf(stderr, "cbranch: cmp needed: `%s'\n", templ + 1);
#endif
#endif
  return templ + 1;
  return templ + 1;
}
}
 
 
#undef TARGET_ENCODE_SECTION_INFO
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
 
 
/* If the frame pointer isn't used, we detect it manually.  But the
/* If the frame pointer isn't used, we detect it manually.  But the
   stack pointer doesn't have as flexible addressing as the frame
   stack pointer doesn't have as flexible addressing as the frame
   pointer, so we always assume we have it.  */
   pointer, so we always assume we have it.  */
 
 
#undef TARGET_FRAME_POINTER_REQUIRED
#undef TARGET_FRAME_POINTER_REQUIRED
#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
 
 
/* The Global `targetm' Variable. */
/* The Global `targetm' Variable. */
 
 
struct gcc_target targetm = TARGET_INITIALIZER;
struct gcc_target targetm = TARGET_INITIALIZER;
 
 
#include "gt-m32c.h"
#include "gt-m32c.h"
 
 

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