;; Machine description for Moxie
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;; Machine description for Moxie
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;; Contributed by Anthony Green
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;; Contributed by Anthony Green
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; Moxie specific constraints, predicates and attributes
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;; Moxie specific constraints, predicates and attributes
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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(include "constraints.md")
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(include "constraints.md")
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(include "predicates.md")
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(include "predicates.md")
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; Most instructions are two bytes long.
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; Most instructions are two bytes long.
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(define_attr "length" "" (const_int 2))
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(define_attr "length" "" (const_int 2))
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; nop instruction
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;; nop instruction
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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(define_insn "nop"
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(define_insn "nop"
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[(const_int 0)]
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[(const_int 0)]
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""
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""
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"nop")
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"nop")
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; Arithmetic instructions
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;; Arithmetic instructions
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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(define_insn "addsi3"
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(plus:SI
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(plus:SI
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(match_operand:SI 1 "register_operand" "0,0,0")
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(match_operand:SI 1 "register_operand" "0,0,0")
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(match_operand:SI 2 "moxie_add_operand" "I,N,r")))]
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(match_operand:SI 2 "moxie_add_operand" "I,N,r")))]
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""
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""
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"@
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"@
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inc %0, %2
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inc %0, %2
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dec %0, -%2
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dec %0, -%2
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add.l %0, %2")
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add.l %0, %2")
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(define_insn "subsi3"
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(minus:SI
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(minus:SI
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(match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "moxie_sub_operand" "I,r")))]
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(match_operand:SI 2 "moxie_sub_operand" "I,r")))]
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""
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""
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"@
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"@
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dec %0, %2
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dec %0, %2
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sub.l %0, %2")
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sub.l %0, %2")
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(define_insn "mulsi3"
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(define_insn "mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mult:SI
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(mult:SI
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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"mul.l %0, %2")
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"mul.l %0, %2")
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(define_insn "divsi3"
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(define_insn "divsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(div:SI
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(div:SI
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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"div.l %0, %2")
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"div.l %0, %2")
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(define_insn "udivsi3"
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(define_insn "udivsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(udiv:SI
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(udiv:SI
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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"udiv.l %0, %2")
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"udiv.l %0, %2")
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(define_insn "modsi3"
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(define_insn "modsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mod:SI
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(mod:SI
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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"mod.l %0, %2")
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"mod.l %0, %2")
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(define_insn "umodsi3"
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(define_insn "umodsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(umod:SI
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(umod:SI
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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"umod.l %0, %2")
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"umod.l %0, %2")
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; Unary arithmetic instructions
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;; Unary arithmetic instructions
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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(define_insn "negsi2"
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "register_operand" "r")))]
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(neg:SI (match_operand:SI 1 "register_operand" "r")))]
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""
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""
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"neg %0, %1")
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"neg %0, %1")
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(define_insn "one_cmplsi2"
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(define_insn "one_cmplsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(not:SI (match_operand:SI 1 "register_operand" "r")))]
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(not:SI (match_operand:SI 1 "register_operand" "r")))]
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""
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""
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"not %0, %1")
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"not %0, %1")
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; Logical operators
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;; Logical operators
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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(define_insn "andsi3"
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(and:SI (match_operand:SI 1 "register_operand" "0")
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(and:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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{
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{
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return "and %0, %2";
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return "and %0, %2";
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})
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})
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(define_insn "xorsi3"
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(xor:SI (match_operand:SI 1 "register_operand" "0")
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(xor:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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{
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{
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return "xor %0, %2";
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return "xor %0, %2";
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})
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})
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(define_insn "iorsi3"
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(define_insn "iorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ior:SI (match_operand:SI 1 "register_operand" "0")
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(ior:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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{
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{
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return "or %0, %2";
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return "or %0, %2";
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})
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})
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; Shifters
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;; Shifters
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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(define_insn "ashlsi3"
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(define_insn "ashlsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0")
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(ashift:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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{
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{
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return "ashl %0, %2";
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return "ashl %0, %2";
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})
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})
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(define_insn "ashrsi3"
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(define_insn "ashrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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{
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{
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return "ashr %0, %2";
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return "ashr %0, %2";
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})
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})
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(define_insn "lshrsi3"
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(define_insn "lshrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "r")))]
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(match_operand:SI 2 "register_operand" "r")))]
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""
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""
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{
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{
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return "lshr %0, %2";
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return "lshr %0, %2";
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})
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})
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; Move instructions
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;; Move instructions
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;; -------------------------------------------------------------------------
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;; -------------------------------------------------------------------------
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;; SImode
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;; SImode
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;; Push a register onto the stack
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;; Push a register onto the stack
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(define_insn "movsi_push"
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(define_insn "movsi_push"
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[(set:SI (mem:SI (pre_dec:SI (reg:SI 1)))
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[(set:SI (mem:SI (pre_dec:SI (reg:SI 1)))
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(match_operand:SI 0 "register_operand" "r"))]
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(match_operand:SI 0 "register_operand" "r"))]
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""
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""
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"push $sp, %0")
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"push $sp, %0")
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;; Pop a register from the stack
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;; Pop a register from the stack
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(define_insn "movsi_pop"
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(define_insn "movsi_pop"
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[(set:SI (match_operand:SI 1 "register_operand" "=r")
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[(set:SI (match_operand:SI 1 "register_operand" "=r")
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(mem:SI (post_inc:SI (match_operand:SI 0 "register_operand" "r"))))]
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(mem:SI (post_inc:SI (match_operand:SI 0 "register_operand" "r"))))]
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""
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""
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"pop %0, %1")
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"pop %0, %1")
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(define_expand "movsi"
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(define_expand "movsi"
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[(set (match_operand:SI 0 "general_operand" "")
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[(set (match_operand:SI 0 "general_operand" "")
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(match_operand:SI 1 "general_operand" ""))]
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(match_operand:SI 1 "general_operand" ""))]
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""
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""
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"
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"
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{
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{
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/* If this is a store, force the value into a register. */
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/* If this is a store, force the value into a register. */
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if (! (reload_in_progress || reload_completed))
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if (! (reload_in_progress || reload_completed))
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{
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{
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if (MEM_P (operands[0]))
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if (MEM_P (operands[0]))
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{
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{
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operands[1] = force_reg (SImode, operands[1]);
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operands[1] = force_reg (SImode, operands[1]);
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if (MEM_P (XEXP (operands[0], 0)))
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if (MEM_P (XEXP (operands[0], 0)))
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operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
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operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
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}
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}
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else
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else
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if (MEM_P (operands[1])
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if (MEM_P (operands[1])
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&& MEM_P (XEXP (operands[1], 0)))
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&& MEM_P (XEXP (operands[1], 0)))
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operands[1] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[1], 0)));
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operands[1] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[1], 0)));
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}
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}
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}")
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}")
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(define_insn "*movsi"
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(define_insn "*movsi"
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[(set (match_operand:SI 0 "general_operand" "=r,r,r,W,A,r,r,B,r")
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[(set (match_operand:SI 0 "general_operand" "=r,r,r,W,A,r,r,B,r")
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(match_operand:SI 1 "moxie_general_movsrc_operand" "O,r,i,r,r,W,A,r,B"))]
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(match_operand:SI 1 "moxie_general_movsrc_operand" "O,r,i,r,r,W,A,r,B"))]
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"register_operand (operands[0], SImode)
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"register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode)"
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|| register_operand (operands[1], SImode)"
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"@
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"@
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xor %0, %0
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xor %0, %0
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mov %0, %1
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mov %0, %1
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ldi.l %0, %1
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ldi.l %0, %1
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st.l %0, %1
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st.l %0, %1
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sta.l %0, %1
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sta.l %0, %1
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ld.l %0, %1
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ld.l %0, %1
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lda.l %0, %1
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lda.l %0, %1
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sto.l %0, %1
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sto.l %0, %1
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ldo.l %0, %1"
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ldo.l %0, %1"
|
[(set_attr "length" "2,2,6,2,6,2,6,6,6")])
|
[(set_attr "length" "2,2,6,2,6,2,6,6,6")])
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|
|
(define_expand "movqi"
|
(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand" "")
|
[(set (match_operand:QI 0 "general_operand" "")
|
(match_operand:QI 1 "general_operand" ""))]
|
(match_operand:QI 1 "general_operand" ""))]
|
""
|
""
|
"
|
"
|
{
|
{
|
/* If this is a store, force the value into a register. */
|
/* If this is a store, force the value into a register. */
|
if (MEM_P (operands[0]))
|
if (MEM_P (operands[0]))
|
operands[1] = force_reg (QImode, operands[1]);
|
operands[1] = force_reg (QImode, operands[1]);
|
}")
|
}")
|
|
|
(define_insn "*movqi"
|
(define_insn "*movqi"
|
[(set (match_operand:QI 0 "general_operand" "=r,r,r,W,A,r,r,B,r")
|
[(set (match_operand:QI 0 "general_operand" "=r,r,r,W,A,r,r,B,r")
|
(match_operand:QI 1 "moxie_general_movsrc_operand" "O,r,i,r,r,W,A,r,B"))]
|
(match_operand:QI 1 "moxie_general_movsrc_operand" "O,r,i,r,r,W,A,r,B"))]
|
"register_operand (operands[0], QImode)
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"register_operand (operands[0], QImode)
|
|| register_operand (operands[1], QImode)"
|
|| register_operand (operands[1], QImode)"
|
"@
|
"@
|
xor %0, %0
|
xor %0, %0
|
mov %0, %1
|
mov %0, %1
|
ldi.b %0, %1
|
ldi.b %0, %1
|
st.b %0, %1
|
st.b %0, %1
|
sta.b %0, %1
|
sta.b %0, %1
|
ld.b %0, %1
|
ld.b %0, %1
|
lda.b %0, %1
|
lda.b %0, %1
|
sto.b %0, %1
|
sto.b %0, %1
|
ldo.b %0, %1"
|
ldo.b %0, %1"
|
[(set_attr "length" "2,2,6,2,6,2,6,6,6")])
|
[(set_attr "length" "2,2,6,2,6,2,6,6,6")])
|
|
|
(define_expand "movhi"
|
(define_expand "movhi"
|
[(set (match_operand:HI 0 "general_operand" "")
|
[(set (match_operand:HI 0 "general_operand" "")
|
(match_operand:HI 1 "general_operand" ""))]
|
(match_operand:HI 1 "general_operand" ""))]
|
""
|
""
|
"
|
"
|
{
|
{
|
/* If this is a store, force the value into a register. */
|
/* If this is a store, force the value into a register. */
|
if (MEM_P (operands[0]))
|
if (MEM_P (operands[0]))
|
operands[1] = force_reg (HImode, operands[1]);
|
operands[1] = force_reg (HImode, operands[1]);
|
}")
|
}")
|
|
|
(define_insn "*movhi"
|
(define_insn "*movhi"
|
[(set (match_operand:HI 0 "general_operand" "=r,r,r,W,A,r,r,B,r")
|
[(set (match_operand:HI 0 "general_operand" "=r,r,r,W,A,r,r,B,r")
|
(match_operand:HI 1 "moxie_general_movsrc_operand" "O,r,i,r,r,W,A,r,B"))]
|
(match_operand:HI 1 "moxie_general_movsrc_operand" "O,r,i,r,r,W,A,r,B"))]
|
"(register_operand (operands[0], HImode)
|
"(register_operand (operands[0], HImode)
|
|| register_operand (operands[1], HImode))"
|
|| register_operand (operands[1], HImode))"
|
"@
|
"@
|
xor %0, %0
|
xor %0, %0
|
mov %0, %1
|
mov %0, %1
|
ldi.s %0, %1
|
ldi.s %0, %1
|
st.s %0, %1
|
st.s %0, %1
|
sta.s %0, %1
|
sta.s %0, %1
|
ld.s %0, %1
|
ld.s %0, %1
|
lda.s %0, %1
|
lda.s %0, %1
|
sto.s %0, %1
|
sto.s %0, %1
|
ldo.s %0, %1"
|
ldo.s %0, %1"
|
[(set_attr "length" "2,2,6,2,6,2,6,6,6")])
|
[(set_attr "length" "2,2,6,2,6,2,6,6,6")])
|
|
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
;; Compare instructions
|
;; Compare instructions
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
|
|
(define_constants
|
(define_constants
|
[(CC_REG 11)])
|
[(CC_REG 11)])
|
|
|
(define_expand "cbranchsi4"
|
(define_expand "cbranchsi4"
|
[(set (reg:CC CC_REG)
|
[(set (reg:CC CC_REG)
|
(compare:CC
|
(compare:CC
|
(match_operand:SI 1 "general_operand" "")
|
(match_operand:SI 1 "general_operand" "")
|
(match_operand:SI 2 "general_operand" "")))
|
(match_operand:SI 2 "general_operand" "")))
|
(set (pc)
|
(set (pc)
|
(if_then_else (match_operator:CC 0 "comparison_operator"
|
(if_then_else (match_operator:CC 0 "comparison_operator"
|
[(reg:CC CC_REG) (const_int 0)])
|
[(reg:CC CC_REG) (const_int 0)])
|
(label_ref (match_operand 3 "" ""))
|
(label_ref (match_operand 3 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
"
|
"
|
/* Force the compare operands into registers. */
|
/* Force the compare operands into registers. */
|
if (GET_CODE (operands[1]) != REG)
|
if (GET_CODE (operands[1]) != REG)
|
operands[1] = force_reg (SImode, operands[1]);
|
operands[1] = force_reg (SImode, operands[1]);
|
if (GET_CODE (operands[2]) != REG)
|
if (GET_CODE (operands[2]) != REG)
|
operands[2] = force_reg (SImode, operands[2]);
|
operands[2] = force_reg (SImode, operands[2]);
|
")
|
")
|
|
|
(define_insn "*cmpsi"
|
(define_insn "*cmpsi"
|
[(set (reg:CC CC_REG)
|
[(set (reg:CC CC_REG)
|
(compare
|
(compare
|
(match_operand:SI 0 "register_operand" "r")
|
(match_operand:SI 0 "register_operand" "r")
|
(match_operand:SI 1 "register_operand" "r")))]
|
(match_operand:SI 1 "register_operand" "r")))]
|
""
|
""
|
"cmp %0, %1")
|
"cmp %0, %1")
|
|
|
|
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
;; Branch instructions
|
;; Branch instructions
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
|
|
(define_code_iterator cond [ne eq lt ltu gt gtu ge le geu leu])
|
(define_code_iterator cond [ne eq lt ltu gt gtu ge le geu leu])
|
(define_code_attr CC [(ne "ne") (eq "eq") (lt "lt") (ltu "ltu")
|
(define_code_attr CC [(ne "ne") (eq "eq") (lt "lt") (ltu "ltu")
|
(gt "gt") (gtu "gtu") (ge "ge") (le "le")
|
(gt "gt") (gtu "gtu") (ge "ge") (le "le")
|
(geu "geu") (leu "leu") ])
|
(geu "geu") (leu "leu") ])
|
(define_code_attr rCC [(ne "eq") (eq "ne") (lt "ge") (ltu "geu")
|
(define_code_attr rCC [(ne "eq") (eq "ne") (lt "ge") (ltu "geu")
|
(gt "le") (gtu "leu") (ge "lt") (le "gt")
|
(gt "le") (gtu "leu") (ge "lt") (le "gt")
|
(geu "ltu") (leu "gtu") ])
|
(geu "ltu") (leu "gtu") ])
|
|
|
(define_insn "*b"
|
(define_insn "*b"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (cond (reg:CC CC_REG)
|
(if_then_else (cond (reg:CC CC_REG)
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
{
|
{
|
if (get_attr_length (insn) == 2)
|
if (get_attr_length (insn) == 2)
|
return "b %l0";
|
return "b %l0";
|
else
|
else
|
return "b .+6\n\tjmpa %l0";
|
return "b .+6\n\tjmpa %l0";
|
}
|
}
|
[(set (attr "length")
|
[(set (attr "length")
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 1022))
|
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 1022))
|
(const_int 2) (const_int 8)))])
|
(const_int 2) (const_int 8)))])
|
|
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
;; Call and Jump instructions
|
;; Call and Jump instructions
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
|
|
(define_expand "call"
|
(define_expand "call"
|
[(call (match_operand:QI 0 "memory_operand" "")
|
[(call (match_operand:QI 0 "memory_operand" "")
|
(match_operand 1 "general_operand" ""))]
|
(match_operand 1 "general_operand" ""))]
|
""
|
""
|
{
|
{
|
gcc_assert (MEM_P (operands[0]));
|
gcc_assert (MEM_P (operands[0]));
|
})
|
})
|
|
|
(define_insn "*call"
|
(define_insn "*call"
|
[(call (mem:QI (match_operand:SI
|
[(call (mem:QI (match_operand:SI
|
0 "nonmemory_operand" "i,r"))
|
0 "nonmemory_operand" "i,r"))
|
(match_operand 1 "" ""))]
|
(match_operand 1 "" ""))]
|
""
|
""
|
"@
|
"@
|
jsra %0
|
jsra %0
|
jsr %0"
|
jsr %0"
|
[(set_attr "length" "6,2")])
|
[(set_attr "length" "6,2")])
|
|
|
(define_expand "call_value"
|
(define_expand "call_value"
|
[(set (match_operand 0 "" "")
|
[(set (match_operand 0 "" "")
|
(call (match_operand:QI 1 "memory_operand" "")
|
(call (match_operand:QI 1 "memory_operand" "")
|
(match_operand 2 "" "")))]
|
(match_operand 2 "" "")))]
|
""
|
""
|
{
|
{
|
gcc_assert (MEM_P (operands[1]));
|
gcc_assert (MEM_P (operands[1]));
|
})
|
})
|
|
|
(define_insn "*call_value"
|
(define_insn "*call_value"
|
[(set (match_operand 0 "register_operand" "=r")
|
[(set (match_operand 0 "register_operand" "=r")
|
(call (mem:QI (match_operand:SI
|
(call (mem:QI (match_operand:SI
|
1 "immediate_operand" "i"))
|
1 "immediate_operand" "i"))
|
(match_operand 2 "" "")))]
|
(match_operand 2 "" "")))]
|
""
|
""
|
"jsra %1"
|
"jsra %1"
|
[(set_attr "length" "6")])
|
[(set_attr "length" "6")])
|
|
|
(define_insn "*call_value_indirect"
|
(define_insn "*call_value_indirect"
|
[(set (match_operand 0 "register_operand" "=r")
|
[(set (match_operand 0 "register_operand" "=r")
|
(call (mem:QI (match_operand:SI
|
(call (mem:QI (match_operand:SI
|
1 "register_operand" "r"))
|
1 "register_operand" "r"))
|
(match_operand 2 "" "")))]
|
(match_operand 2 "" "")))]
|
""
|
""
|
"jsr %1")
|
"jsr %1")
|
|
|
(define_insn "indirect_jump"
|
(define_insn "indirect_jump"
|
[(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
|
[(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
|
""
|
""
|
"jmp %0")
|
"jmp %0")
|
|
|
(define_insn "jump"
|
(define_insn "jump"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
""
|
""
|
"jmpa %l0"
|
"jmpa %l0"
|
[(set_attr "length" "6")])
|
[(set_attr "length" "6")])
|
|
|
|
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
;; Prologue & Epilogue
|
;; Prologue & Epilogue
|
;; -------------------------------------------------------------------------
|
;; -------------------------------------------------------------------------
|
|
|
(define_expand "prologue"
|
(define_expand "prologue"
|
[(clobber (const_int 0))]
|
[(clobber (const_int 0))]
|
""
|
""
|
"
|
"
|
{
|
{
|
moxie_expand_prologue ();
|
moxie_expand_prologue ();
|
DONE;
|
DONE;
|
}
|
}
|
")
|
")
|
|
|
(define_expand "epilogue"
|
(define_expand "epilogue"
|
[(return)]
|
[(return)]
|
""
|
""
|
"
|
"
|
{
|
{
|
moxie_expand_epilogue ();
|
moxie_expand_epilogue ();
|
DONE;
|
DONE;
|
}
|
}
|
")
|
")
|
|
|
(define_insn "returner"
|
(define_insn "returner"
|
[(return)]
|
[(return)]
|
"reload_completed"
|
"reload_completed"
|
"ret")
|
"ret")
|
|
|
