;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
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;; Machine description for GNU compiler, OpenRISC 1000 family, OR32 ISA
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
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;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
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;; 2009, 2010 Free Software Foundation, Inc.
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;; 2009, 2010 Free Software Foundation, Inc.
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|
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;; Contributed by Damjan Lampret in 1999.
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;; Contributed by Damjan Lampret in 1999.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Major optimizations by Matjaz Breskvar in 2005.
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;; Floating point additions by Jungsook Yang
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;; Floating point additions by Jungsook Yang
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;; Julius Baxter in 2010
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;; Julius Baxter in 2010
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;; Updated for GCC 4.5 by Jeremy Bennett in 2010
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;; Updated for GCC 4.5 by Jeremy Bennett in 2010
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;; This file is part of GNU CC.
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;; This file is part of GNU CC.
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;; This program is free software; you can redistribute it and/or modify it
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;; This program is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by the Free
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;; under the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 3 of the License, or (at your option)
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;; Software Foundation; either version 3 of the License, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; This program is distributed in the hope that it will be useful, but WITHOUT
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;; This program is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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;; more details.
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;; more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License along
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;; You should have received a copy of the GNU General Public License along
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;; with this program. If not, see . */
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;; with this program. If not, see . */
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|
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(include "predicates.md")
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(include "predicates.md")
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|
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(define_attr "type"
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(define_attr "type"
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"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
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"unknown,load,store,move,extend,logic,add,mul,shift,compare,branch,jump,fp"
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(const_string "unknown"))
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(const_string "unknown"))
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|
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;; Number of machine instructions required to implement an insn.
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;; Number of machine instructions required to implement an insn.
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(define_attr "length" "" (const_int 1))
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(define_attr "length" "" (const_int 1))
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|
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;; Single delay slot after branch or jump instructions, wich may contain any
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;; Single delay slot after branch or jump instructions, wich may contain any
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;; instruction but another branch or jump.
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;; instruction but another branch or jump.
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(define_delay (eq_attr "type" "branch,jump")
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(define_delay (eq_attr "type" "branch,jump")
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[(and (eq_attr "type" "!branch,jump")
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[(and (eq_attr "type" "!branch,jump")
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(eq_attr "length" "1")) (nil) (nil)])
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(eq_attr "length" "1")) (nil) (nil)])
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|
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;; ALU is modelled as a single functional unit, which is reserved for varying
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;; ALU is modelled as a single functional unit, which is reserved for varying
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;; numbers of slots.
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;; numbers of slots.
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;;
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;;
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;; I think this is all incorrect for the OR1K. The latency says when the
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;; I think this is all incorrect for the OR1K. The latency says when the
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;; result will be ready, not how long the pipeline takes to execute.
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;; result will be ready, not how long the pipeline takes to execute.
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(define_cpu_unit "or32_alu")
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(define_cpu_unit "or32_alu")
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(define_insn_reservation "bit_unit" 3 (eq_attr "type" "shift") "or32_alu")
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(define_insn_reservation "bit_unit" 3 (eq_attr "type" "shift") "or32_alu")
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(define_insn_reservation "lsu_load" 3 (eq_attr "type" "load") "or32_alu*3")
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(define_insn_reservation "lsu_load" 3 (eq_attr "type" "load") "or32_alu*3")
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(define_insn_reservation "lsu_store" 2 (eq_attr "type" "store") "or32_alu")
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(define_insn_reservation "lsu_store" 2 (eq_attr "type" "store") "or32_alu")
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(define_insn_reservation "alu_unit" 2
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(define_insn_reservation "alu_unit" 2
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(eq_attr "type" "add,logic,extend,move,compare")
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(eq_attr "type" "add,logic,extend,move,compare")
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"or32_alu")
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"or32_alu")
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(define_insn_reservation "mul_unit" 16 (eq_attr "type" "mul") "or32_alu*16")
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(define_insn_reservation "mul_unit" 16 (eq_attr "type" "mul") "or32_alu*16")
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|
|
|
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;; Called after register allocation to add any instructions needed for the
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;; Called after register allocation to add any instructions needed for the
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;; prologue. Using a prologue insn is favored compared to putting all of the
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;; prologue. Using a prologue insn is favored compared to putting all of the
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;; instructions in output_function_prologue(), since it allows the scheduler
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;; instructions in output_function_prologue(), since it allows the scheduler
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;; to intermix instructions with the saves of the caller saved registers. In
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;; to intermix instructions with the saves of the caller saved registers. In
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;; some cases, it might be necessary to emit a barrier instruction as the last
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;; some cases, it might be necessary to emit a barrier instruction as the last
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;; insn to prevent such scheduling.
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;; insn to prevent such scheduling.
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|
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(define_expand "prologue"
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(define_expand "prologue"
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[(use (const_int 1))]
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[(use (const_int 1))]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_MASK_SCHED_LOGUE"
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{
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{
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or32_expand_prologue ();
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or32_expand_prologue ();
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DONE;
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DONE;
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})
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})
|
|
|
;; Called after register allocation to add any instructions needed for the
|
;; Called after register allocation to add any instructions needed for the
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;; epilogue. Using an epilogue insn is favored compared to putting all of the
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;; epilogue. Using an epilogue insn is favored compared to putting all of the
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;; instructions in output_function_epilogue(), since it allows the scheduler
|
;; instructions in output_function_epilogue(), since it allows the scheduler
|
;; to intermix instructions with the restores of the caller saved registers.
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;; to intermix instructions with the restores of the caller saved registers.
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;; In some cases, it might be necessary to emit a barrier instruction as the
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;; In some cases, it might be necessary to emit a barrier instruction as the
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;; first insn to prevent such scheduling.
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;; first insn to prevent such scheduling.
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(define_expand "epilogue"
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(define_expand "epilogue"
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[(use (const_int 2))]
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[(use (const_int 2))]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_MASK_SCHED_LOGUE"
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{
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{
|
or32_expand_epilogue (false);
|
or32_expand_epilogue (false);
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DONE;
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DONE;
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})
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})
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|
|
(define_expand "sibcall_epilogue"
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(define_expand "sibcall_epilogue"
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[(use (const_int 2))]
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[(use (const_int 2))]
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"TARGET_MASK_SCHED_LOGUE"
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"TARGET_MASK_SCHED_LOGUE"
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{
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{
|
or32_expand_epilogue (true);
|
or32_expand_epilogue (true);
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DONE;
|
DONE;
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})
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})
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|
|
(define_insn "return_internal"
|
(define_insn "return_internal"
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[(return)
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[(return)
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(use (match_operand 0 "pmode_register_operand" ""))]
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(use (match_operand 0 "pmode_register_operand" ""))]
|
"TARGET_MASK_SCHED_LOGUE"
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"TARGET_MASK_SCHED_LOGUE"
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"l.jr \t%0%("
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"l.jr \t%0%("
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[(set_attr "type" "jump")
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[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
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|
|
;;
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;;
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;; Sibcalls
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;; Sibcalls
|
;;
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;;
|
|
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(define_expand "sibcall"
|
(define_expand "sibcall"
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[(parallel [(call (match_operand 0 "" "")
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[(parallel [(call (match_operand 0 "" "")
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(match_operand 1 "" ""))
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(match_operand 1 "" ""))
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(use (match_operand 2 "" "")) ;; next_arg_reg
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(use (match_operand 2 "" "")) ;; next_arg_reg
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(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
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(use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
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"TARGET_MASK_SIBCALL"
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"TARGET_MASK_SIBCALL"
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"
|
"
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{
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{
|
or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
|
or32_expand_sibcall (0, XEXP (operands[0], 0), operands[1]);
|
DONE;
|
DONE;
|
}")
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}")
|
|
|
(define_expand "sibcall_value"
|
(define_expand "sibcall_value"
|
[(set (match_operand 0 "" "")
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[(set (match_operand 0 "" "")
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(call (match_operand:SI 1 "" "")
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(call (match_operand:SI 1 "" "")
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(match_operand 2 "" "")))]
|
(match_operand 2 "" "")))]
|
"TARGET_MASK_SIBCALL"
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"TARGET_MASK_SIBCALL"
|
"
|
"
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{
|
{
|
or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
|
or32_expand_sibcall (operands[0], XEXP (operands[1], 0), operands[2]);
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "sibcall_internal"
|
(define_insn "sibcall_internal"
|
[(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,r"))
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[(call (mem:SI (match_operand:SI 0 "sibcall_insn_operand" "s,r"))
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(match_operand 1 "" ""))
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(match_operand 1 "" ""))
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(use (reg:SI 9))]
|
(use (reg:SI 9))]
|
"TARGET_MASK_SIBCALL"
|
"TARGET_MASK_SIBCALL"
|
"@
|
"@
|
l.j \t%S0%(\t # sibcall s
|
l.j \t%S0%(\t # sibcall s
|
l.jr \t%0%(\t # sibcall r"
|
l.jr \t%0%(\t # sibcall r"
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[(set_attr "type" "jump,jump")])
|
[(set_attr "type" "jump,jump")])
|
|
|
|
|
|
|
;;
|
;;
|
;; movQI
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;; movQI
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;;
|
;;
|
|
|
(define_expand "movqi"
|
(define_expand "movqi"
|
[(set (match_operand:QI 0 "general_operand" "")
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[(set (match_operand:QI 0 "general_operand" "")
|
(match_operand:QI 1 "general_operand" ""))]
|
(match_operand:QI 1 "general_operand" ""))]
|
""
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""
|
"
|
"
|
if (can_create_pseudo_p())
|
if (can_create_pseudo_p())
|
{
|
{
|
if (GET_CODE (operands[1]) == CONST_INT)
|
if (GET_CODE (operands[1]) == CONST_INT)
|
{
|
{
|
rtx reg = gen_reg_rtx (SImode);
|
rtx reg = gen_reg_rtx (SImode);
|
|
|
emit_insn (gen_movsi (reg, operands[1]));
|
emit_insn (gen_movsi (reg, operands[1]));
|
operands[1] = gen_lowpart (QImode, reg);
|
operands[1] = gen_lowpart (QImode, reg);
|
}
|
}
|
if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
{
|
{
|
rtx reg = gen_reg_rtx (SImode);
|
rtx reg = gen_reg_rtx (SImode);
|
|
|
emit_insn (gen_rtx_SET (SImode, reg,
|
emit_insn (gen_rtx_SET (SImode, reg,
|
gen_rtx_ZERO_EXTEND (SImode,
|
gen_rtx_ZERO_EXTEND (SImode,
|
operands[1])));
|
operands[1])));
|
|
|
operands[1] = gen_lowpart (QImode, reg);
|
operands[1] = gen_lowpart (QImode, reg);
|
}
|
}
|
if (GET_CODE (operands[0]) != REG)
|
if (GET_CODE (operands[0]) != REG)
|
operands[1] = force_reg (QImode, operands[1]);
|
operands[1] = force_reg (QImode, operands[1]);
|
}
|
}
|
")
|
")
|
|
|
(define_insn "*movqi_internal"
|
(define_insn "*movqi_internal"
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
(match_operand:QI 1 "general_operand" "r,r,I,K,m"))]
|
(match_operand:QI 1 "general_operand" "r,r,I,K,m"))]
|
""
|
""
|
"@
|
"@
|
l.sb \t%0,%1\t # movqi
|
l.sb \t%0,%1\t # movqi
|
l.ori \t%0,%1,0\t # movqi: move reg to reg
|
l.ori \t%0,%1,0\t # movqi: move reg to reg
|
l.addi \t%0,r0,%1\t # movqi: move immediate
|
l.addi \t%0,r0,%1\t # movqi: move immediate
|
l.ori \t%0,r0,%1\t # movqi: move immediate
|
l.ori \t%0,r0,%1\t # movqi: move immediate
|
l.lbz \t%0,%1\t # movqi"
|
l.lbz \t%0,%1\t # movqi"
|
[(set_attr "type" "store,add,add,logic,load")])
|
[(set_attr "type" "store,add,add,logic,load")])
|
|
|
|
|
;;
|
;;
|
;; movHI
|
;; movHI
|
;;
|
;;
|
|
|
(define_expand "movhi"
|
(define_expand "movhi"
|
[(set (match_operand:HI 0 "general_operand" "")
|
[(set (match_operand:HI 0 "general_operand" "")
|
(match_operand:HI 1 "general_operand" ""))]
|
(match_operand:HI 1 "general_operand" ""))]
|
""
|
""
|
"
|
"
|
if (can_create_pseudo_p())
|
if (can_create_pseudo_p())
|
{
|
{
|
if (GET_CODE (operands[1]) == CONST_INT)
|
if (GET_CODE (operands[1]) == CONST_INT)
|
{
|
{
|
rtx reg = gen_reg_rtx (SImode);
|
rtx reg = gen_reg_rtx (SImode);
|
|
|
emit_insn (gen_movsi (reg, operands[1]));
|
emit_insn (gen_movsi (reg, operands[1]));
|
operands[1] = gen_lowpart (HImode, reg);
|
operands[1] = gen_lowpart (HImode, reg);
|
}
|
}
|
if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
if (GET_CODE (operands[1]) == MEM && optimize > 0)
|
{
|
{
|
rtx reg = gen_reg_rtx (SImode);
|
rtx reg = gen_reg_rtx (SImode);
|
|
|
emit_insn (gen_rtx_SET (SImode, reg,
|
emit_insn (gen_rtx_SET (SImode, reg,
|
gen_rtx_ZERO_EXTEND (SImode,
|
gen_rtx_ZERO_EXTEND (SImode,
|
operands[1])));
|
operands[1])));
|
operands[1] = gen_lowpart (HImode, reg);
|
operands[1] = gen_lowpart (HImode, reg);
|
}
|
}
|
if (GET_CODE (operands[0]) != REG)
|
if (GET_CODE (operands[0]) != REG)
|
operands[1] = force_reg (HImode, operands[1]);
|
operands[1] = force_reg (HImode, operands[1]);
|
}
|
}
|
")
|
")
|
|
|
(define_insn "*movhi_internal"
|
(define_insn "*movhi_internal"
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,r,r,r,r")
|
(match_operand:HI 1 "general_operand" "r,r,I,K,m"))]
|
(match_operand:HI 1 "general_operand" "r,r,I,K,m"))]
|
""
|
""
|
"@
|
"@
|
l.sh \t%0,%1\t # movhi
|
l.sh \t%0,%1\t # movhi
|
l.ori \t%0,%1,0\t # movhi: move reg to reg
|
l.ori \t%0,%1,0\t # movhi: move reg to reg
|
l.addi \t%0,r0,%1\t # movhi: move immediate
|
l.addi \t%0,r0,%1\t # movhi: move immediate
|
l.ori \t%0,r0,%1\t # movhi: move immediate
|
l.ori \t%0,r0,%1\t # movhi: move immediate
|
l.lhz \t%0,%1\t # movhi"
|
l.lhz \t%0,%1\t # movhi"
|
[(set_attr "type" "store,add,add,logic,load")])
|
[(set_attr "type" "store,add,add,logic,load")])
|
|
|
(define_expand "movsi"
|
(define_expand "movsi"
|
[(set (match_operand:SI 0 "general_operand" "")
|
[(set (match_operand:SI 0 "general_operand" "")
|
(match_operand:SI 1 "general_operand" ""))]
|
(match_operand:SI 1 "general_operand" ""))]
|
""
|
""
|
{
|
{
|
/* Working with CONST_INTs is easier, so convert
|
/* Working with CONST_INTs is easier, so convert
|
a double if needed. */
|
a double if needed. */
|
|
|
if (GET_CODE (operands[1]) == CONST_DOUBLE) {
|
if (GET_CODE (operands[1]) == CONST_DOUBLE) {
|
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
|
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
|
}
|
}
|
|
|
/* Handle sets of MEM first. */
|
/* Handle sets of MEM first. */
|
if (GET_CODE (operands[0]) == MEM)
|
if (GET_CODE (operands[0]) == MEM)
|
{
|
{
|
if (register_operand(operands[1], SImode)
|
if (register_operand(operands[1], SImode)
|
|| (operands[1] == const0_rtx))
|
|| (operands[1] == const0_rtx))
|
goto movsi_is_ok;
|
goto movsi_is_ok;
|
|
|
if (! reload_in_progress)
|
if (! reload_in_progress)
|
{
|
{
|
operands[0] = validize_mem (operands[0]);
|
operands[0] = validize_mem (operands[0]);
|
operands[1] = force_reg (SImode, operands[1]);
|
operands[1] = force_reg (SImode, operands[1]);
|
}
|
}
|
}
|
}
|
|
|
/* This makes sure we will not get rematched due to splittage. */
|
/* This makes sure we will not get rematched due to splittage. */
|
if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
|
if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
|
;
|
;
|
else if (CONSTANT_P (operands[1])
|
else if (CONSTANT_P (operands[1])
|
&& GET_CODE (operands[1]) != HIGH
|
&& GET_CODE (operands[1]) != HIGH
|
&& GET_CODE (operands[1]) != LO_SUM)
|
&& GET_CODE (operands[1]) != LO_SUM)
|
{
|
{
|
or32_emit_set_const32 (operands[0], operands[1]);
|
or32_emit_set_const32 (operands[0], operands[1]);
|
DONE;
|
DONE;
|
}
|
}
|
movsi_is_ok:
|
movsi_is_ok:
|
;
|
;
|
})
|
})
|
|
|
;;
|
;;
|
;; movSI
|
;; movSI
|
;;
|
;;
|
|
|
(define_insn "*movsi_insn"
|
(define_insn "*movsi_insn"
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
|
(match_operand:SI 1 "input_operand" "I,K,M,r,m,r"))]
|
(match_operand:SI 1 "input_operand" "I,K,M,r,m,r"))]
|
"(register_operand (operands[0], SImode)
|
"(register_operand (operands[0], SImode)
|
|| register_operand (operands[1], SImode)
|
|| register_operand (operands[1], SImode)
|
|| (operands[1] == const0_rtx))"
|
|| (operands[1] == const0_rtx))"
|
"@
|
"@
|
l.addi \t%0,r0,%1\t # move immediate I
|
l.addi \t%0,r0,%1\t # move immediate I
|
l.ori \t%0,r0,%1\t # move immediate K
|
l.ori \t%0,r0,%1\t # move immediate K
|
l.movhi \t%0,hi(%1)\t # move immediate M
|
l.movhi \t%0,hi(%1)\t # move immediate M
|
l.ori \t%0,%1,0\t # move reg to reg
|
l.ori \t%0,%1,0\t # move reg to reg
|
l.lwz \t%0,%1\t # SI load
|
l.lwz \t%0,%1\t # SI load
|
l.sw \t%0,%1\t # SI store"
|
l.sw \t%0,%1\t # SI store"
|
[(set_attr "type" "add,load,store,add,logic,move")
|
[(set_attr "type" "add,load,store,add,logic,move")
|
(set_attr "length" "1,1,1,1,1,1")])
|
(set_attr "length" "1,1,1,1,1,1")])
|
|
|
(define_insn "*movsi_lo_sum"
|
(define_insn "*movsi_lo_sum"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 2 "immediate_operand" "i")))]
|
(match_operand:SI 2 "immediate_operand" "i")))]
|
""
|
""
|
"l.ori \t%0,%1,lo(%2)"
|
"l.ori \t%0,%1,lo(%2)"
|
[(set_attr "type" "logic")
|
[(set_attr "type" "logic")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "*movsi_high"
|
(define_insn "*movsi_high"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
(high:SI (match_operand:SI 1 "immediate_operand" "i")))]
|
""
|
""
|
"l.movhi \t%0,hi(%1)"
|
"l.movhi \t%0,hi(%1)"
|
[(set_attr "type" "move")
|
[(set_attr "type" "move")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "movsi_insn_big"
|
(define_insn "movsi_insn_big"
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
(match_operand:SI 1 "immediate_operand" "i"))]
|
(match_operand:SI 1 "immediate_operand" "i"))]
|
"GET_CODE(operands[1]) != CONST_INT"
|
"GET_CODE(operands[1]) != CONST_INT"
|
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)"
|
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)"
|
[(set_attr "type" "move")
|
[(set_attr "type" "move")
|
(set_attr "length" "2")])
|
(set_attr "length" "2")])
|
|
|
|
|
;;
|
;;
|
;; Conditional Branches & Moves
|
;; Conditional Branches & Moves
|
;;
|
;;
|
|
|
(define_expand "addsicc"
|
(define_expand "addsicc"
|
[(match_operand:SI 0 "register_operand" "")
|
[(match_operand:SI 0 "register_operand" "")
|
(match_operand 1 "comparison_operator" "")
|
(match_operand 1 "comparison_operator" "")
|
(match_operand:SI 2 "register_operand" "")
|
(match_operand:SI 2 "register_operand" "")
|
(match_operand:SI 3 "register_operand" "")]
|
(match_operand:SI 3 "register_operand" "")]
|
""
|
""
|
"FAIL;")
|
"FAIL;")
|
|
|
(define_expand "addhicc"
|
(define_expand "addhicc"
|
[(match_operand:HI 0 "register_operand" "")
|
[(match_operand:HI 0 "register_operand" "")
|
(match_operand 1 "comparison_operator" "")
|
(match_operand 1 "comparison_operator" "")
|
(match_operand:HI 2 "register_operand" "")
|
(match_operand:HI 2 "register_operand" "")
|
(match_operand:HI 3 "register_operand" "")]
|
(match_operand:HI 3 "register_operand" "")]
|
""
|
""
|
"FAIL;")
|
"FAIL;")
|
|
|
(define_expand "addqicc"
|
(define_expand "addqicc"
|
[(match_operand:QI 0 "register_operand" "")
|
[(match_operand:QI 0 "register_operand" "")
|
(match_operand 1 "comparison_operator" "")
|
(match_operand 1 "comparison_operator" "")
|
(match_operand:QI 2 "register_operand" "")
|
(match_operand:QI 2 "register_operand" "")
|
(match_operand:QI 3 "register_operand" "")]
|
(match_operand:QI 3 "register_operand" "")]
|
""
|
""
|
"FAIL;")
|
"FAIL;")
|
|
|
|
|
;;
|
;;
|
;; conditional moves
|
;; conditional moves
|
;;
|
;;
|
|
|
(define_expand "movsicc"
|
(define_expand "movsicc"
|
[(set (match_operand:SI 0 "register_operand" "")
|
[(set (match_operand:SI 0 "register_operand" "")
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
(match_operand:SI 2 "register_operand" "")
|
(match_operand:SI 2 "register_operand" "")
|
(match_operand:SI 3 "register_operand" "")))]
|
(match_operand:SI 3 "register_operand" "")))]
|
"TARGET_MASK_CMOV"
|
"TARGET_MASK_CMOV"
|
"
|
"
|
{
|
{
|
if (or32_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
if (or32_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_expand "movhicc"
|
(define_expand "movhicc"
|
[(set (match_operand:HI 0 "register_operand" "")
|
[(set (match_operand:HI 0 "register_operand" "")
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
(match_operand:HI 2 "register_operand" "")
|
(match_operand:HI 2 "register_operand" "")
|
(match_operand:HI 3 "register_operand" "")))]
|
(match_operand:HI 3 "register_operand" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
FAIL;
|
FAIL;
|
}")
|
}")
|
|
|
(define_expand "movqicc"
|
(define_expand "movqicc"
|
[(set (match_operand:QI 0 "register_operand" "")
|
[(set (match_operand:QI 0 "register_operand" "")
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
(if_then_else:SI (match_operand 1 "comparison_operator" "")
|
(match_operand:QI 2 "register_operand" "")
|
(match_operand:QI 2 "register_operand" "")
|
(match_operand:QI 3 "register_operand" "")))]
|
(match_operand:QI 3 "register_operand" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
FAIL;
|
FAIL;
|
}")
|
}")
|
|
|
|
|
;; We use the BASE_REGS for the cmov input operands because, if rA is
|
;; We use the BASE_REGS for the cmov input operands because, if rA is
|
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
|
;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
|
;; because we may switch the operands and rB may end up being rA.
|
;; because we may switch the operands and rB may end up being rA.
|
|
|
(define_insn "cmov"
|
(define_insn "cmov"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(if_then_else:SI
|
(if_then_else:SI
|
(match_operator 1 "comparison_operator"
|
(match_operator 1 "comparison_operator"
|
[(match_operand 4 "cc_reg_operand" "")
|
[(match_operand 4 "cc_reg_operand" "")
|
(const_int 0)])
|
(const_int 0)])
|
(match_operand:SI 2 "register_operand" "r")
|
(match_operand:SI 2 "register_operand" "r")
|
(match_operand:SI 3 "register_operand" "r")))]
|
(match_operand:SI 3 "register_operand" "r")))]
|
"TARGET_MASK_CMOV"
|
"TARGET_MASK_CMOV"
|
"*
|
"*
|
return or32_output_cmov(operands);
|
return or32_output_cmov(operands);
|
")
|
")
|
|
|
;;
|
;;
|
;; ....................
|
;; ....................
|
;;
|
;;
|
;; COMPARISONS
|
;; COMPARISONS
|
;;
|
;;
|
;; ....................
|
;; ....................
|
|
|
;; Flow here is rather complex:
|
;; Flow here is rather complex:
|
;;
|
;;
|
;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
|
;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
|
;; arguments into the branch_cmp array, and the type into
|
;; arguments into the branch_cmp array, and the type into
|
;; branch_type. No RTL is generated.
|
;; branch_type. No RTL is generated.
|
;;
|
;;
|
;; 2) The appropriate branch define_expand is called, which then
|
;; 2) The appropriate branch define_expand is called, which then
|
;; creates the appropriate RTL for the comparison and branch.
|
;; creates the appropriate RTL for the comparison and branch.
|
;; Different CC modes are used, based on what type of branch is
|
;; Different CC modes are used, based on what type of branch is
|
;; done, so that we can constrain things appropriately. There
|
;; done, so that we can constrain things appropriately. There
|
;; are assumptions in the rest of GCC that break if we fold the
|
;; are assumptions in the rest of GCC that break if we fold the
|
;; operands into the branches for integer operations, and use cc0
|
;; operands into the branches for integer operations, and use cc0
|
;; for floating point, so we use the fp status register instead.
|
;; for floating point, so we use the fp status register instead.
|
;; If needed, an appropriate temporary is created to hold the
|
;; If needed, an appropriate temporary is created to hold the
|
;; of the integer compare.
|
;; of the integer compare.
|
|
|
;; Compare insns are next. Note that the RS/6000 has two types of compares,
|
;; Compare insns are next. Note that the RS/6000 has two types of compares,
|
;; signed & unsigned, and one type of branch.
|
;; signed & unsigned, and one type of branch.
|
;;
|
;;
|
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
|
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
|
;; insns, and branches. We store the operands of compares until we see
|
;; insns, and branches. We store the operands of compares until we see
|
;; how it is used.
|
;; how it is used.
|
|
|
;; JPB 31-Aug-10: cmpxx appears to be obsolete in GCC 4.5. Needs more
|
;; JPB 31-Aug-10: cmpxx appears to be obsolete in GCC 4.5. Needs more
|
;; investigation.
|
;; investigation.
|
|
|
;;(define_expand "cmpsi"
|
;;(define_expand "cmpsi"
|
;; [(set (reg:CC 32)
|
;; [(set (reg:CC 32)
|
;; (compare:CC (match_operand:SI 0 "register_operand" "")
|
;; (compare:CC (match_operand:SI 0 "register_operand" "")
|
;; (match_operand:SI 1 "nonmemory_operand" "")))]
|
;; (match_operand:SI 1 "nonmemory_operand" "")))]
|
;; ""
|
;; ""
|
;; {
|
;; {
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
;; operands[0] = force_reg (SImode, operands[0]);
|
;; operands[0] = force_reg (SImode, operands[0]);
|
;; or32_compare_op0 = operands[0];
|
;; or32_compare_op0 = operands[0];
|
;; or32_compare_op1 = operands[1];
|
;; or32_compare_op1 = operands[1];
|
;; DONE;
|
;; DONE;
|
;; })
|
;; })
|
|
|
;; (define_expand "cmpsf"
|
;; (define_expand "cmpsf"
|
;; [(set (reg:CC 32)
|
;; [(set (reg:CC 32)
|
;; (compare:CC (match_operand:SF 0 "register_operand" "")
|
;; (compare:CC (match_operand:SF 0 "register_operand" "")
|
;; (match_operand:SF 1 "register_operand" "")))]
|
;; (match_operand:SF 1 "register_operand" "")))]
|
;; "TARGET_HARD_FLOAT"
|
;; "TARGET_HARD_FLOAT"
|
;; {
|
;; {
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
|
;; operands[0] = force_reg (SFmode, operands[0]);
|
;; operands[0] = force_reg (SFmode, operands[0]);
|
;; or32_compare_op0 = operands[0];
|
;; or32_compare_op0 = operands[0];
|
;; or32_compare_op1 = operands[1];
|
;; or32_compare_op1 = operands[1];
|
;; DONE;
|
;; DONE;
|
;; })
|
;; })
|
|
|
(define_expand "cbranchsi4"
|
(define_expand "cbranchsi4"
|
[(match_operator 0 "comparison_operator"
|
[(match_operator 0 "comparison_operator"
|
[(match_operand:SI 1 "register_operand")
|
[(match_operand:SI 1 "register_operand")
|
(match_operand:SI 2 "nonmemory_operand")])
|
(match_operand:SI 2 "nonmemory_operand")])
|
(match_operand 3 "")]
|
(match_operand 3 "")]
|
""
|
""
|
{
|
{
|
or32_expand_conditional_branch (operands, SImode);
|
or32_expand_conditional_branch (operands, SImode);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "cbranchsf4"
|
(define_expand "cbranchsf4"
|
[(match_operator 0 "comparison_operator"
|
[(match_operator 0 "comparison_operator"
|
[(match_operand:SI 1 "register_operand")
|
[(match_operand:SI 1 "register_operand")
|
(match_operand:SI 2 "register_operand")])
|
(match_operand:SI 2 "register_operand")])
|
(match_operand 3 "")]
|
(match_operand 3 "")]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
{
|
{
|
or32_expand_conditional_branch (operands, SFmode);
|
or32_expand_conditional_branch (operands, SFmode);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
;;
|
;;
|
;; Setting a CCxx registers from comparision
|
;; Setting a CCxx registers from comparision
|
;;
|
;;
|
|
|
|
|
|
|
;; Here are the actual compare insns.
|
;; Here are the actual compare insns.
|
(define_insn "*cmpsi_eq"
|
(define_insn "*cmpsi_eq"
|
[(set (reg:CCEQ 32)
|
[(set (reg:CCEQ 32)
|
(compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCEQ (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfeqi\t%0,%1
|
l.sfeqi\t%0,%1
|
l.sfeq \t%0,%1")
|
l.sfeq \t%0,%1")
|
|
|
(define_insn "*cmpsi_ne"
|
(define_insn "*cmpsi_ne"
|
[(set (reg:CCNE 32)
|
[(set (reg:CCNE 32)
|
(compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCNE (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfnei\t%0,%1
|
l.sfnei\t%0,%1
|
l.sfne \t%0,%1")
|
l.sfne \t%0,%1")
|
|
|
(define_insn "*cmpsi_gt"
|
(define_insn "*cmpsi_gt"
|
[(set (reg:CCGT 32)
|
[(set (reg:CCGT 32)
|
(compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGT (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgtsi\t%0,%1
|
l.sfgtsi\t%0,%1
|
l.sfgts \t%0,%1")
|
l.sfgts \t%0,%1")
|
|
|
(define_insn "*cmpsi_gtu"
|
(define_insn "*cmpsi_gtu"
|
[(set (reg:CCGTU 32)
|
[(set (reg:CCGTU 32)
|
(compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGTU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgtui\t%0,%1
|
l.sfgtui\t%0,%1
|
l.sfgtu \t%0,%1")
|
l.sfgtu \t%0,%1")
|
|
|
(define_insn "*cmpsi_lt"
|
(define_insn "*cmpsi_lt"
|
[(set (reg:CCLT 32)
|
[(set (reg:CCLT 32)
|
(compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLT (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfltsi\t%0,%1
|
l.sfltsi\t%0,%1
|
l.sflts \t%0,%1")
|
l.sflts \t%0,%1")
|
|
|
(define_insn "*cmpsi_ltu"
|
(define_insn "*cmpsi_ltu"
|
[(set (reg:CCLTU 32)
|
[(set (reg:CCLTU 32)
|
(compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLTU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfltui\t%0,%1
|
l.sfltui\t%0,%1
|
l.sfltu \t%0,%1")
|
l.sfltu \t%0,%1")
|
|
|
(define_insn "*cmpsi_ge"
|
(define_insn "*cmpsi_ge"
|
[(set (reg:CCGE 32)
|
[(set (reg:CCGE 32)
|
(compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGE (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgesi\t%0,%1
|
l.sfgesi\t%0,%1
|
l.sfges \t%0,%1")
|
l.sfges \t%0,%1")
|
|
|
|
|
(define_insn "*cmpsi_geu"
|
(define_insn "*cmpsi_geu"
|
[(set (reg:CCGEU 32)
|
[(set (reg:CCGEU 32)
|
(compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCGEU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfgeui\t%0,%1
|
l.sfgeui\t%0,%1
|
l.sfgeu \t%0,%1")
|
l.sfgeu \t%0,%1")
|
|
|
|
|
(define_insn "*cmpsi_le"
|
(define_insn "*cmpsi_le"
|
[(set (reg:CCLE 32)
|
[(set (reg:CCLE 32)
|
(compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLE (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sflesi\t%0,%1
|
l.sflesi\t%0,%1
|
l.sfles \t%0,%1")
|
l.sfles \t%0,%1")
|
|
|
(define_insn "*cmpsi_leu"
|
(define_insn "*cmpsi_leu"
|
[(set (reg:CCLEU 32)
|
[(set (reg:CCLEU 32)
|
(compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
|
(compare:CCLEU (match_operand:SI 0 "register_operand" "r,r")
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
(match_operand:SI 1 "nonmemory_operand" "I,r")))]
|
""
|
""
|
"@
|
"@
|
l.sfleui\t%0,%1
|
l.sfleui\t%0,%1
|
l.sfleu \t%0,%1")
|
l.sfleu \t%0,%1")
|
|
|
;; Single precision floating point evaluation instructions
|
;; Single precision floating point evaluation instructions
|
(define_insn "*cmpsf_eq"
|
(define_insn "*cmpsf_eq"
|
[(set (reg:CCEQ 32)
|
[(set (reg:CCEQ 32)
|
(compare:CCEQ (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCEQ (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfeq.s\t%0,%1")
|
"lf.sfeq.s\t%0,%1")
|
|
|
(define_insn "*cmpsf_ne"
|
(define_insn "*cmpsf_ne"
|
[(set (reg:CCNE 32)
|
[(set (reg:CCNE 32)
|
(compare:CCNE (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCNE (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfne.s\t%0,%1")
|
"lf.sfne.s\t%0,%1")
|
|
|
|
|
(define_insn "*cmpsf_gt"
|
(define_insn "*cmpsf_gt"
|
[(set (reg:CCGT 32)
|
[(set (reg:CCGT 32)
|
(compare:CCGT (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCGT (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfgt.s\t%0,%1")
|
"lf.sfgt.s\t%0,%1")
|
|
|
(define_insn "*cmpsf_ge"
|
(define_insn "*cmpsf_ge"
|
[(set (reg:CCGE 32)
|
[(set (reg:CCGE 32)
|
(compare:CCGE (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCGE (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfge.s\t%0,%1")
|
"lf.sfge.s\t%0,%1")
|
|
|
|
|
(define_insn "*cmpsf_lt"
|
(define_insn "*cmpsf_lt"
|
[(set (reg:CCLT 32)
|
[(set (reg:CCLT 32)
|
(compare:CCLT (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCLT (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sflt.s\t%0,%1")
|
"lf.sflt.s\t%0,%1")
|
|
|
(define_insn "*cmpsf_le"
|
(define_insn "*cmpsf_le"
|
[(set (reg:CCLE 32)
|
[(set (reg:CCLE 32)
|
(compare:CCLE (match_operand:SF 0 "register_operand" "r,r")
|
(compare:CCLE (match_operand:SF 0 "register_operand" "r,r")
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
(match_operand:SF 1 "register_operand" "r,r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sfle.s\t%0,%1")
|
"lf.sfle.s\t%0,%1")
|
|
|
(define_insn "*bf"
|
(define_insn "*bf"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else (match_operator 1 "comparison_operator"
|
(if_then_else (match_operator 1 "comparison_operator"
|
[(match_operand 2
|
[(match_operand 2
|
"cc_reg_operand" "")
|
"cc_reg_operand" "")
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 0 "" ""))
|
(label_ref (match_operand 0 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
"*
|
"*
|
return or32_output_bf(operands);
|
return or32_output_bf(operands);
|
"
|
"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;;
|
;;
|
;;
|
;;
|
;;
|
;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;
|
;;
|
;;
|
;;
|
(define_insn "movdi"
|
(define_insn "movdi"
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m, r")
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m, r")
|
(match_operand:DI 1 "general_operand" " r, m, r, i"))]
|
(match_operand:DI 1 "general_operand" " r, m, r, i"))]
|
""
|
""
|
"*
|
"*
|
return or32_output_move_double (operands);
|
return or32_output_move_double (operands);
|
"
|
"
|
[(set_attr "length" "2,2,2,3")])
|
[(set_attr "length" "2,2,2,3")])
|
|
|
;; Moving double and single precision floating point values
|
;; Moving double and single precision floating point values
|
|
|
(define_insn "movdf"
|
(define_insn "movdf"
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r, r, m, r")
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r, r, m, r")
|
(match_operand:DF 1 "general_operand" " r, m, r, i"))]
|
(match_operand:DF 1 "general_operand" " r, m, r, i"))]
|
""
|
""
|
"*
|
"*
|
return or32_output_move_double (operands);
|
return or32_output_move_double (operands);
|
"
|
"
|
[(set_attr "length" "2,2,2,3")])
|
[(set_attr "length" "2,2,2,3")])
|
|
|
|
|
(define_insn "movsf"
|
(define_insn "movsf"
|
[(set (match_operand:SF 0 "general_operand" "=r,r,m")
|
[(set (match_operand:SF 0 "general_operand" "=r,r,m")
|
(match_operand:SF 1 "general_operand" "r,m,r"))]
|
(match_operand:SF 1 "general_operand" "r,m,r"))]
|
""
|
""
|
"@
|
"@
|
l.ori \t%0,%1,0\t # movsf
|
l.ori \t%0,%1,0\t # movsf
|
l.lwz \t%0,%1\t # movsf
|
l.lwz \t%0,%1\t # movsf
|
l.sw \t%0,%1\t # movsf"
|
l.sw \t%0,%1\t # movsf"
|
[(set_attr "type" "move,load,store")
|
[(set_attr "type" "move,load,store")
|
(set_attr "length" "1,1,1")])
|
(set_attr "length" "1,1,1")])
|
|
|
|
|
;;
|
;;
|
;; extendqisi2
|
;; extendqisi2
|
;;
|
;;
|
|
|
(define_expand "extendqisi2"
|
(define_expand "extendqisi2"
|
[(use (match_operand:SI 0 "register_operand" ""))
|
[(use (match_operand:SI 0 "register_operand" ""))
|
(use (match_operand:QI 1 "nonimmediate_operand" ""))]
|
(use (match_operand:QI 1 "nonimmediate_operand" ""))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (TARGET_MASK_SEXT)
|
if (TARGET_MASK_SEXT)
|
emit_insn (gen_extendqisi2_sext(operands[0], operands[1]));
|
emit_insn (gen_extendqisi2_sext(operands[0], operands[1]));
|
else {
|
else {
|
if ( GET_CODE(operands[1]) == MEM ) {
|
if ( GET_CODE(operands[1]) == MEM ) {
|
emit_insn (gen_extendqisi2_no_sext_mem(operands[0], operands[1]));
|
emit_insn (gen_extendqisi2_no_sext_mem(operands[0], operands[1]));
|
}
|
}
|
else {
|
else {
|
emit_insn (gen_extendqisi2_no_sext_reg(operands[0], operands[1]));
|
emit_insn (gen_extendqisi2_no_sext_reg(operands[0], operands[1]));
|
}
|
}
|
}
|
}
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "extendqisi2_sext"
|
(define_insn "extendqisi2_sext"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
"TARGET_MASK_SEXT"
|
"TARGET_MASK_SEXT"
|
"@
|
"@
|
l.extbs \t%0,%1\t # extendqisi2_has_signed_extend
|
l.extbs \t%0,%1\t # extendqisi2_has_signed_extend
|
l.lbs \t%0,%1\t # extendqisi2_has_signed_extend"
|
l.lbs \t%0,%1\t # extendqisi2_has_signed_extend"
|
[(set_attr "length" "1,1")
|
[(set_attr "length" "1,1")
|
(set_attr "type" "extend,load")])
|
(set_attr "type" "extend,load")])
|
|
|
(define_insn "extendqisi2_no_sext_mem"
|
(define_insn "extendqisi2_no_sext_mem"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
|
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
|
"!TARGET_MASK_SEXT"
|
"!TARGET_MASK_SEXT"
|
"l.lbs \t%0,%1\t # extendqisi2_no_sext_mem"
|
"l.lbs \t%0,%1\t # extendqisi2_no_sext_mem"
|
[(set_attr "length" "1")
|
[(set_attr "length" "1")
|
(set_attr "type" "load")])
|
(set_attr "type" "load")])
|
|
|
(define_expand "extendqisi2_no_sext_reg"
|
(define_expand "extendqisi2_no_sext_reg"
|
[(set (match_dup 2)
|
[(set (match_dup 2)
|
(ashift:SI (match_operand:QI 1 "register_operand" "")
|
(ashift:SI (match_operand:QI 1 "register_operand" "")
|
(const_int 24)))
|
(const_int 24)))
|
(set (match_operand:SI 0 "register_operand" "")
|
(set (match_operand:SI 0 "register_operand" "")
|
(ashiftrt:SI (match_dup 2)
|
(ashiftrt:SI (match_dup 2)
|
(const_int 24)))]
|
(const_int 24)))]
|
"!TARGET_MASK_SEXT"
|
"!TARGET_MASK_SEXT"
|
"
|
"
|
{
|
{
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
operands[2] = gen_reg_rtx (SImode); }")
|
operands[2] = gen_reg_rtx (SImode); }")
|
|
|
;;
|
;;
|
;; extendhisi2
|
;; extendhisi2
|
;;
|
;;
|
|
|
(define_expand "extendhisi2"
|
(define_expand "extendhisi2"
|
[(use (match_operand:SI 0 "register_operand" ""))
|
[(use (match_operand:SI 0 "register_operand" ""))
|
(use (match_operand:HI 1 "nonimmediate_operand" ""))]
|
(use (match_operand:HI 1 "nonimmediate_operand" ""))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (TARGET_MASK_SEXT)
|
if (TARGET_MASK_SEXT)
|
emit_insn (gen_extendhisi2_sext(operands[0], operands[1]));
|
emit_insn (gen_extendhisi2_sext(operands[0], operands[1]));
|
else {
|
else {
|
if ( GET_CODE(operands[1]) == MEM ) {
|
if ( GET_CODE(operands[1]) == MEM ) {
|
emit_insn (gen_extendhisi2_no_sext_mem(operands[0], operands[1]));
|
emit_insn (gen_extendhisi2_no_sext_mem(operands[0], operands[1]));
|
}
|
}
|
else {
|
else {
|
emit_insn (gen_extendhisi2_no_sext_reg(operands[0], operands[1]));
|
emit_insn (gen_extendhisi2_no_sext_reg(operands[0], operands[1]));
|
}
|
}
|
}
|
}
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "extendhisi2_sext"
|
(define_insn "extendhisi2_sext"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
"TARGET_MASK_SEXT"
|
"TARGET_MASK_SEXT"
|
"@
|
"@
|
l.exths \t%0,%1\t # extendhisi2_has_signed_extend
|
l.exths \t%0,%1\t # extendhisi2_has_signed_extend
|
l.lhs \t%0,%1\t # extendhisi2_has_signed_extend"
|
l.lhs \t%0,%1\t # extendhisi2_has_signed_extend"
|
[(set_attr "length" "1,1")
|
[(set_attr "length" "1,1")
|
(set_attr "type" "extend,load")])
|
(set_attr "type" "extend,load")])
|
|
|
(define_insn "extendhisi2_no_sext_mem"
|
(define_insn "extendhisi2_no_sext_mem"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
|
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
|
"!TARGET_MASK_SEXT"
|
"!TARGET_MASK_SEXT"
|
"l.lhs \t%0,%1\t # extendhisi2_no_sext_mem"
|
"l.lhs \t%0,%1\t # extendhisi2_no_sext_mem"
|
[(set_attr "length" "1")
|
[(set_attr "length" "1")
|
(set_attr "type" "load")])
|
(set_attr "type" "load")])
|
|
|
(define_expand "extendhisi2_no_sext_reg"
|
(define_expand "extendhisi2_no_sext_reg"
|
[(set (match_dup 2)
|
[(set (match_dup 2)
|
(ashift:SI (match_operand:HI 1 "register_operand" "")
|
(ashift:SI (match_operand:HI 1 "register_operand" "")
|
(const_int 16)))
|
(const_int 16)))
|
(set (match_operand:SI 0 "register_operand" "")
|
(set (match_operand:SI 0 "register_operand" "")
|
(ashiftrt:SI (match_dup 2)
|
(ashiftrt:SI (match_dup 2)
|
(const_int 16)))]
|
(const_int 16)))]
|
"!TARGET_MASK_SEXT"
|
"!TARGET_MASK_SEXT"
|
"
|
"
|
{
|
{
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
operands[1] = gen_lowpart (SImode, operands[1]);
|
operands[2] = gen_reg_rtx (SImode); }")
|
operands[2] = gen_reg_rtx (SImode); }")
|
|
|
|
|
;;
|
;;
|
;; zero_extend2
|
;; zero_extend2
|
;;
|
;;
|
|
|
(define_insn "zero_extendqisi2"
|
(define_insn "zero_extendqisi2"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
|
""
|
""
|
"@
|
"@
|
l.andi \t%0,%1,0xff\t # zero_extendqisi2
|
l.andi \t%0,%1,0xff\t # zero_extendqisi2
|
l.lbz \t%0,%1\t # zero_extendqisi2"
|
l.lbz \t%0,%1\t # zero_extendqisi2"
|
[(set_attr "type" "logic,load")
|
[(set_attr "type" "logic,load")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
|
|
(define_insn "zero_extendhisi2"
|
(define_insn "zero_extendhisi2"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
|
""
|
""
|
"@
|
"@
|
l.andi \t%0,%1,0xffff\t # zero_extendqisi2
|
l.andi \t%0,%1,0xffff\t # zero_extendqisi2
|
l.lhz \t%0,%1\t # zero_extendqisi2"
|
l.lhz \t%0,%1\t # zero_extendqisi2"
|
[(set_attr "type" "logic,load")
|
[(set_attr "type" "logic,load")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
;;
|
;;
|
;; Shift/rotate operations
|
;; Shift/rotate operations
|
;;
|
;;
|
|
|
(define_insn "ashlsi3"
|
(define_insn "ashlsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
|
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
""
|
""
|
"@
|
"@
|
l.sll \t%0,%1,%2
|
l.sll \t%0,%1,%2
|
l.slli \t%0,%1,%2"
|
l.slli \t%0,%1,%2"
|
[(set_attr "type" "shift,shift")
|
[(set_attr "type" "shift,shift")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "ashrsi3"
|
(define_insn "ashrsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
""
|
""
|
"@
|
"@
|
l.sra \t%0,%1,%2
|
l.sra \t%0,%1,%2
|
l.srai \t%0,%1,%2"
|
l.srai \t%0,%1,%2"
|
[(set_attr "type" "shift,shift")
|
[(set_attr "type" "shift,shift")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "lshrsi3"
|
(define_insn "lshrsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
""
|
""
|
"@
|
"@
|
l.srl \t%0,%1,%2
|
l.srl \t%0,%1,%2
|
l.srli \t%0,%1,%2"
|
l.srli \t%0,%1,%2"
|
[(set_attr "type" "shift,shift")
|
[(set_attr "type" "shift,shift")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "rotrsi3"
|
(define_insn "rotrsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
|
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,L")))]
|
"TARGET_MASK_ROR"
|
"TARGET_MASK_ROR"
|
"@
|
"@
|
l.ror \t%0,%1,%2
|
l.ror \t%0,%1,%2
|
l.rori \t%0,%1,%2"
|
l.rori \t%0,%1,%2"
|
[(set_attr "type" "shift,shift")
|
[(set_attr "type" "shift,shift")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
;;
|
;;
|
;; Logical bitwise operations
|
;; Logical bitwise operations
|
;;
|
;;
|
|
|
(define_insn "andsi3"
|
(define_insn "andsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(and:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
""
|
""
|
"@
|
"@
|
l.and \t%0,%1,%2
|
l.and \t%0,%1,%2
|
l.andi \t%0,%1,%2"
|
l.andi \t%0,%1,%2"
|
[(set_attr "type" "logic,logic")
|
[(set_attr "type" "logic,logic")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "iorsi3"
|
(define_insn "iorsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(ior:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(ior:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,K")))]
|
""
|
""
|
"@
|
"@
|
l.or \t%0,%1,%2
|
l.or \t%0,%1,%2
|
l.ori \t%0,%1,%2"
|
l.ori \t%0,%1,%2"
|
[(set_attr "type" "logic,logic")
|
[(set_attr "type" "logic,logic")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "xorsi3"
|
(define_insn "xorsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(xor:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(xor:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
""
|
""
|
"@
|
"@
|
l.xor \t%0,%1,%2
|
l.xor \t%0,%1,%2
|
l.xori \t%0,%1,%2"
|
l.xori \t%0,%1,%2"
|
[(set_attr "type" "logic,logic")
|
[(set_attr "type" "logic,logic")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "one_cmplqi2"
|
(define_insn "one_cmplqi2"
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
[(set (match_operand:QI 0 "register_operand" "=r")
|
(not:QI (match_operand:QI 1 "register_operand" "r")))]
|
(not:QI (match_operand:QI 1 "register_operand" "r")))]
|
""
|
""
|
"l.xori \t%0,%1,0x00ff"
|
"l.xori \t%0,%1,0x00ff"
|
[(set_attr "type" "logic")
|
[(set_attr "type" "logic")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "one_cmplsi2"
|
(define_insn "one_cmplsi2"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(not:SI (match_operand:SI 1 "register_operand" "r")))]
|
(not:SI (match_operand:SI 1 "register_operand" "r")))]
|
""
|
""
|
"l.xori \t%0,%1,0xffff"
|
"l.xori \t%0,%1,0xffff"
|
[(set_attr "type" "logic")
|
[(set_attr "type" "logic")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;;
|
;;
|
;; Arithmetic operations
|
;; Arithmetic operations
|
;;
|
;;
|
|
|
(define_insn "negsi2"
|
(define_insn "negsi2"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
|
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
|
""
|
""
|
"l.sub \t%0,r0,%1"
|
"l.sub \t%0,r0,%1"
|
[(set_attr "type" "add")
|
[(set_attr "type" "add")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "addsi3"
|
(define_insn "addsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(plus:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(plus:SI (match_operand:SI 1 "register_operand" "%r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
""
|
""
|
"@
|
"@
|
l.add \t%0,%1,%2
|
l.add \t%0,%1,%2
|
l.addi \t%0,%1,%2"
|
l.addi \t%0,%1,%2"
|
[(set_attr "type" "add,add")
|
[(set_attr "type" "add,add")
|
(set_attr "length" "1,1")])
|
(set_attr "length" "1,1")])
|
|
|
(define_insn "subsi3"
|
(define_insn "subsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
(minus:SI (match_operand:SI 1 "register_operand" "r,r")
|
(minus:SI (match_operand:SI 1 "register_operand" "r,r")
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
(match_operand:SI 2 "nonmemory_operand" "r,I")))]
|
""
|
""
|
"@
|
"@
|
l.sub \t%0,%1,%2
|
l.sub \t%0,%1,%2
|
l.addi \t%0,%1,%n2"
|
l.addi \t%0,%1,%n2"
|
[(set_attr "type" "add,add")]
|
[(set_attr "type" "add,add")]
|
)
|
)
|
|
|
;;
|
;;
|
;; mul and div
|
;; mul and div
|
;;
|
;;
|
|
|
(define_insn "mulsi3"
|
(define_insn "mulsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(mult:SI (match_operand:SI 1 "register_operand" "r")
|
(mult:SI (match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 2 "register_operand" "r")))]
|
(match_operand:SI 2 "register_operand" "r")))]
|
"TARGET_HARD_MUL"
|
"TARGET_HARD_MUL"
|
"l.mul \t%0,%1,%2"
|
"l.mul \t%0,%1,%2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "divsi3"
|
(define_insn "divsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(div:SI (match_operand:SI 1 "register_operand" "r")
|
(div:SI (match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 2 "register_operand" "r")))]
|
(match_operand:SI 2 "register_operand" "r")))]
|
"TARGET_HARD_DIV"
|
"TARGET_HARD_DIV"
|
"l.div \t%0,%1,%2"
|
"l.div \t%0,%1,%2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "udivsi3"
|
(define_insn "udivsi3"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(udiv:SI (match_operand:SI 1 "register_operand" "r")
|
(udiv:SI (match_operand:SI 1 "register_operand" "r")
|
(match_operand:SI 2 "register_operand" "r")))]
|
(match_operand:SI 2 "register_operand" "r")))]
|
"TARGET_HARD_DIV"
|
"TARGET_HARD_DIV"
|
"l.divu \t%0,%1,%2"
|
"l.divu \t%0,%1,%2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;;
|
;;
|
;; jumps
|
;; jumps
|
;;
|
;;
|
|
|
;; jump
|
;; jump
|
|
|
(define_expand "jump"
|
(define_expand "jump"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_jump_insn (gen_jump_internal (operands[0]));
|
emit_jump_insn (gen_jump_internal (operands[0]));
|
else
|
else
|
emit_jump_insn (gen_jump_aligned (operands[0]));
|
emit_jump_insn (gen_jump_aligned (operands[0]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "jump_internal"
|
(define_insn "jump_internal"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.j \t%l0%("
|
"l.j \t%l0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "jump_aligned"
|
(define_insn "jump_aligned"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.j \t%l0%("
|
".balignl 0x8,0x15000015,0x4\;l.j \t%l0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; indirect jump
|
;; indirect jump
|
|
|
(define_expand "indirect_jump"
|
(define_expand "indirect_jump"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_jump_insn (gen_indirect_jump_internal (operands[0]));
|
emit_jump_insn (gen_indirect_jump_internal (operands[0]));
|
else
|
else
|
emit_jump_insn (gen_indirect_jump_aligned (operands[0]));
|
emit_jump_insn (gen_indirect_jump_aligned (operands[0]));
|
DONE;
|
DONE;
|
|
|
}")
|
}")
|
|
|
(define_insn "indirect_jump_internal"
|
(define_insn "indirect_jump_internal"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.jr \t%0%("
|
"l.jr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "indirect_jump_aligned"
|
(define_insn "indirect_jump_aligned"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;;
|
;;
|
;; calls
|
;; calls
|
;;
|
;;
|
|
|
;; call
|
;; call
|
|
|
(define_expand "call"
|
(define_expand "call"
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_call_insn (gen_call_internal (operands[0], operands[1]));
|
emit_call_insn (gen_call_internal (operands[0], operands[1]));
|
else
|
else
|
emit_call_insn (gen_call_aligned (operands[0], operands[1]));
|
emit_call_insn (gen_call_aligned (operands[0], operands[1]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_internal"
|
(define_insn "call_internal"
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.jal \t%S0%("
|
"l.jal \t%S0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_aligned"
|
(define_insn "call_aligned"
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
[(parallel [(call (match_operand:SI 0 "sym_ref_mem_operand" "")
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S0%("
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; call value
|
;; call value
|
|
|
(define_expand "call_value"
|
(define_expand "call_value"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
|
emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2]));
|
else
|
else
|
emit_call_insn (gen_call_value_aligned (operands[0], operands[1], operands[2]));
|
emit_call_insn (gen_call_value_aligned (operands[0], operands[1], operands[2]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_value_internal"
|
(define_insn "call_value_internal"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.jal \t%S1%("
|
"l.jal \t%S1%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_value_aligned"
|
(define_insn "call_value_aligned"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(call (match_operand:SI 1 "sym_ref_mem_operand" "")
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S1%("
|
".balignl 0x8,0x15000015,0x4\;l.jal \t%S1%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; indirect call value
|
;; indirect call value
|
|
|
(define_expand "call_value_indirect"
|
(define_expand "call_value_indirect"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
|
emit_call_insn (gen_call_value_indirect_internal (operands[0], operands[1], operands[2]));
|
else
|
else
|
emit_call_insn (gen_call_value_indirect_aligned (operands[0], operands[1], operands[2]));
|
emit_call_insn (gen_call_value_indirect_aligned (operands[0], operands[1], operands[2]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_value_indirect_internal"
|
(define_insn "call_value_indirect_internal"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.jalr \t%1%("
|
"l.jalr \t%1%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_value_indirect_aligned"
|
(define_insn "call_value_indirect_aligned"
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
[(parallel [(set (match_operand 0 "register_operand" "=r")
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
(match_operand 2 "" "i")))
|
(match_operand 2 "" "i")))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%1%("
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%1%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; indirect call
|
;; indirect call
|
|
|
(define_expand "call_indirect"
|
(define_expand "call_indirect"
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
|
emit_call_insn (gen_call_indirect_internal (operands[0], operands[1]));
|
else
|
else
|
emit_call_insn (gen_call_indirect_aligned (operands[0], operands[1]));
|
emit_call_insn (gen_call_indirect_aligned (operands[0], operands[1]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "call_indirect_internal"
|
(define_insn "call_indirect_internal"
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.jalr \t%0%("
|
"l.jalr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "call_indirect_aligned"
|
(define_insn "call_indirect_aligned"
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
[(parallel [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
(match_operand 1 "" "i"))
|
(match_operand 1 "" "i"))
|
(clobber (reg:SI 9))])]
|
(clobber (reg:SI 9))])]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%0%("
|
".balignl 0x8,0x15000015,0x4\;l.jalr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; table jump
|
;; table jump
|
|
|
(define_expand "tablejump"
|
(define_expand "tablejump"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
""
|
""
|
"
|
"
|
{
|
{
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
if (!TARGET_MASK_ALIGNED_JUMPS)
|
emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
|
emit_jump_insn (gen_tablejump_internal (operands[0], operands[1]));
|
else
|
else
|
emit_jump_insn (gen_tablejump_aligned (operands[0], operands[1]));
|
emit_jump_insn (gen_tablejump_aligned (operands[0], operands[1]));
|
DONE;
|
DONE;
|
}")
|
}")
|
|
|
(define_insn "tablejump_internal"
|
(define_insn "tablejump_internal"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"!TARGET_MASK_ALIGNED_JUMPS"
|
"l.jr \t%0%("
|
"l.jr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "tablejump_aligned"
|
(define_insn "tablejump_aligned"
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
"TARGET_MASK_ALIGNED_JUMPS"
|
"TARGET_MASK_ALIGNED_JUMPS"
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
".balignl 0x8,0x15000015,0x4\;l.jr \t%0%("
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
|
|
;; no-op
|
;; no-op
|
|
|
(define_insn "nop"
|
(define_insn "nop"
|
[(const_int 0)]
|
[(const_int 0)]
|
""
|
""
|
"l.nop"
|
"l.nop"
|
[(set_attr "type" "logic")
|
[(set_attr "type" "logic")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;;
|
;;
|
;; floating point
|
;; floating point
|
;;
|
;;
|
|
|
;; floating point arithmetic
|
;; floating point arithmetic
|
|
|
(define_insn "addsf3"
|
(define_insn "addsf3"
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
(plus:SF (match_operand:SF 1 "register_operand" "r")
|
(plus:SF (match_operand:SF 1 "register_operand" "r")
|
(match_operand:SF 2 "register_operand" "r")))]
|
(match_operand:SF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.add.s\t%0,%1,%2"
|
"lf.add.s\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "adddf3"
|
(define_insn "adddf3"
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
(plus:DF (match_operand:DF 1 "register_operand" "r")
|
(plus:DF (match_operand:DF 1 "register_operand" "r")
|
(match_operand:DF 2 "register_operand" "r")))]
|
(match_operand:DF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"lf.add.d\t%0,%1,%2"
|
"lf.add.d\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "subsf3"
|
(define_insn "subsf3"
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
(minus:SF (match_operand:SF 1 "register_operand" "r")
|
(minus:SF (match_operand:SF 1 "register_operand" "r")
|
(match_operand:SF 2 "register_operand" "r")))]
|
(match_operand:SF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.sub.s\t%0,%1,%2"
|
"lf.sub.s\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "subdf3"
|
(define_insn "subdf3"
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
(minus:DF (match_operand:DF 1 "register_operand" "r")
|
(minus:DF (match_operand:DF 1 "register_operand" "r")
|
(match_operand:DF 2 "register_operand" "r")))]
|
(match_operand:DF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"lf.sub.d\t%0,%1,%2"
|
"lf.sub.d\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "mulsf3"
|
(define_insn "mulsf3"
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
(mult:SF (match_operand:SF 1 "register_operand" "r")
|
(mult:SF (match_operand:SF 1 "register_operand" "r")
|
(match_operand:SF 2 "register_operand" "r")))]
|
(match_operand:SF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.mul.s\t%0,%1,%2"
|
"lf.mul.s\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "muldf3"
|
(define_insn "muldf3"
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
(mult:DF (match_operand:DF 1 "register_operand" "r")
|
(mult:DF (match_operand:DF 1 "register_operand" "r")
|
(match_operand:DF 2 "register_operand" "r")))]
|
(match_operand:DF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"lf.mul.d\t%0,%1,%2"
|
"lf.mul.d\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "divsf3"
|
(define_insn "divsf3"
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
(div:SF (match_operand:SF 1 "register_operand" "r")
|
(div:SF (match_operand:SF 1 "register_operand" "r")
|
(match_operand:SF 2 "register_operand" "r")))]
|
(match_operand:SF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.div.s\t%0,%1,%2"
|
"lf.div.s\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
(define_insn "divdf3"
|
(define_insn "divdf3"
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
[(set (match_operand:DF 0 "register_operand" "=r")
|
(div:DF (match_operand:DF 1 "register_operand" "r")
|
(div:DF (match_operand:DF 1 "register_operand" "r")
|
(match_operand:DF 2 "register_operand" "r")))]
|
(match_operand:DF 2 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
"lf.div.d\t%0,%1,%2"
|
"lf.div.d\t%0,%1,%2"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; Conversion between fixed point and floating point.
|
;; Conversion between fixed point and floating point.
|
|
|
|
|
(define_insn "floatsisf2"
|
(define_insn "floatsisf2"
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
[(set (match_operand:SF 0 "register_operand" "=r")
|
(float:SF (match_operand:SI 1 "register_operand" "r")))]
|
(float:SF (match_operand:SI 1 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.itof.s\t%0, %1"
|
"lf.itof.s\t%0, %1"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
;; not working
|
;; not working
|
(define_insn "fixunssfsi2"
|
(define_insn "fixunssfsi2"
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
(fix:SI (match_operand:SF 1 "register_operand" "r")))]
|
(fix:SI (match_operand:SF 1 "register_operand" "r")))]
|
"TARGET_HARD_FLOAT"
|
"TARGET_HARD_FLOAT"
|
"lf.ftoi.s\t%0, %1"
|
"lf.ftoi.s\t%0, %1"
|
[(set_attr "type" "fp")
|
[(set_attr "type" "fp")
|
(set_attr "length" "1")])
|
(set_attr "length" "1")])
|
|
|
|
|
;; Local variables:
|
;; Local variables:
|
;; mode:emacs-lisp
|
;; mode:emacs-lisp
|
;; comment-start: ";; "
|
;; comment-start: ";; "
|
;; eval: (set-syntax-table (copy-sequence (syntax-table)))
|
;; eval: (set-syntax-table (copy-sequence (syntax-table)))
|
;; eval: (modify-syntax-entry ?[ "(]")
|
;; eval: (modify-syntax-entry ?[ "(]")
|
;; eval: (modify-syntax-entry ?] ")[")
|
;; eval: (modify-syntax-entry ?] ")[")
|
;; eval: (modify-syntax-entry ?{ "(}")
|
;; eval: (modify-syntax-entry ?{ "(}")
|
;; eval: (modify-syntax-entry ?} "){")
|
;; eval: (modify-syntax-entry ?} "){")
|
;; eval: (setq indent-tabs-mode t)
|
;; eval: (setq indent-tabs-mode t)
|
;; End:
|
;; End:
|
|
|