;; Scheduling description for IBM POWER7 processor.
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;; Scheduling description for IBM POWER7 processor.
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;; Copyright (C) 2009 Free Software Foundation, Inc.
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;;
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;;
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;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
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;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; option) any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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(define_automaton "power7iu,power7lsu,power7vsu,power7misc")
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(define_automaton "power7iu,power7lsu,power7vsu,power7misc")
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(define_cpu_unit "iu1_power7,iu2_power7" "power7iu")
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(define_cpu_unit "iu1_power7,iu2_power7" "power7iu")
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(define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu")
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(define_cpu_unit "lsu1_power7,lsu2_power7" "power7lsu")
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(define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu")
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(define_cpu_unit "vsu1_power7,vsu2_power7" "power7vsu")
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(define_cpu_unit "bpu_power7,cru_power7" "power7misc")
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(define_cpu_unit "bpu_power7,cru_power7" "power7misc")
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(define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7"
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(define_cpu_unit "du1_power7,du2_power7,du3_power7,du4_power7,du5_power7"
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"power7misc")
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"power7misc")
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(define_reservation "DU_power7"
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(define_reservation "DU_power7"
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"du1_power7|du2_power7|du3_power7|du4_power7")
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"du1_power7|du2_power7|du3_power7|du4_power7")
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(define_reservation "DU2F_power7"
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(define_reservation "DU2F_power7"
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"du1_power7+du2_power7")
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"du1_power7+du2_power7")
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(define_reservation "DU4_power7"
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(define_reservation "DU4_power7"
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"du1_power7+du2_power7+du3_power7+du4_power7")
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"du1_power7+du2_power7+du3_power7+du4_power7")
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(define_reservation "FXU_power7"
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(define_reservation "FXU_power7"
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"iu1_power7|iu2_power7")
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"iu1_power7|iu2_power7")
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(define_reservation "VSU_power7"
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(define_reservation "VSU_power7"
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"vsu1_power7|vsu2_power7")
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"vsu1_power7|vsu2_power7")
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(define_reservation "LSU_power7"
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(define_reservation "LSU_power7"
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"lsu1_power7|lsu2_power7")
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"lsu1_power7|lsu2_power7")
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; Dispatch slots are allocated in order conforming to program order.
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; Dispatch slots are allocated in order conforming to program order.
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(absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7")
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(absence_set "du1_power7" "du2_power7,du3_power7,du4_power7,du5_power7")
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(absence_set "du2_power7" "du3_power7,du4_power7,du5_power7")
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(absence_set "du2_power7" "du3_power7,du4_power7,du5_power7")
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(absence_set "du3_power7" "du4_power7,du5_power7")
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(absence_set "du3_power7" "du4_power7,du5_power7")
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(absence_set "du4_power7" "du5_power7")
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(absence_set "du4_power7" "du5_power7")
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; LS Unit
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; LS Unit
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(define_insn_reservation "power7-load" 2
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(define_insn_reservation "power7-load" 2
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(and (eq_attr "type" "load")
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7")
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"DU_power7,LSU_power7")
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(define_insn_reservation "power7-load-ext" 3
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(define_insn_reservation "power7-load-ext" 3
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(and (eq_attr "type" "load_ext")
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(and (eq_attr "type" "load_ext")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,LSU_power7,FXU_power7")
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"DU2F_power7,LSU_power7,FXU_power7")
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(define_insn_reservation "power7-load-update" 2
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(define_insn_reservation "power7-load-update" 2
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(and (eq_attr "type" "load_u")
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(and (eq_attr "type" "load_u")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,LSU_power7+FXU_power7")
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"DU2F_power7,LSU_power7+FXU_power7")
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(define_insn_reservation "power7-load-update-indexed" 3
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(define_insn_reservation "power7-load-update-indexed" 3
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(and (eq_attr "type" "load_ux")
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(and (eq_attr "type" "load_ux")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,FXU_power7,LSU_power7+FXU_power7")
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"DU4_power7,FXU_power7,LSU_power7+FXU_power7")
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(define_insn_reservation "power7-load-ext-update" 4
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(define_insn_reservation "power7-load-ext-update" 4
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(and (eq_attr "type" "load_ext_u")
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(and (eq_attr "type" "load_ext_u")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
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"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
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(define_insn_reservation "power7-load-ext-update-indexed" 4
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(define_insn_reservation "power7-load-ext-update-indexed" 4
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(and (eq_attr "type" "load_ext_ux")
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(and (eq_attr "type" "load_ext_ux")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
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"DU4_power7,FXU_power7,LSU_power7+FXU_power7,FXU_power7")
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(define_insn_reservation "power7-fpload" 3
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(define_insn_reservation "power7-fpload" 3
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(and (eq_attr "type" "fpload")
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7")
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"DU_power7,LSU_power7")
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(define_insn_reservation "power7-fpload-update" 3
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(define_insn_reservation "power7-fpload-update" 3
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(and (eq_attr "type" "fpload_u,fpload_ux")
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(and (eq_attr "type" "fpload_u,fpload_ux")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,LSU_power7+FXU_power7")
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"DU2F_power7,LSU_power7+FXU_power7")
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(define_insn_reservation "power7-store" 6 ; store-forwarding latency
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(define_insn_reservation "power7-store" 6 ; store-forwarding latency
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(and (eq_attr "type" "store")
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(and (eq_attr "type" "store")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7+FXU_power7")
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"DU_power7,LSU_power7+FXU_power7")
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(define_insn_reservation "power7-store-update" 6
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(define_insn_reservation "power7-store-update" 6
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(and (eq_attr "type" "store_u")
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(and (eq_attr "type" "store_u")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
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"DU2F_power7,LSU_power7+FXU_power7,FXU_power7")
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(define_insn_reservation "power7-store-update-indexed" 6
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(define_insn_reservation "power7-store-update-indexed" 6
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(and (eq_attr "type" "store_ux")
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(and (eq_attr "type" "store_ux")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,LSU_power7+FXU_power7,FXU_power7")
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"DU4_power7,LSU_power7+FXU_power7,FXU_power7")
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(define_insn_reservation "power7-fpstore" 6
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(define_insn_reservation "power7-fpstore" 6
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(and (eq_attr "type" "fpstore")
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7+VSU_power7")
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"DU_power7,LSU_power7+VSU_power7")
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(define_insn_reservation "power7-fpstore-update" 6
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(define_insn_reservation "power7-fpstore-update" 6
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(and (eq_attr "type" "fpstore_u,fpstore_ux")
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(and (eq_attr "type" "fpstore_u,fpstore_ux")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7+VSU_power7+FXU_power7")
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"DU_power7,LSU_power7+VSU_power7+FXU_power7")
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(define_insn_reservation "power7-larx" 3
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(define_insn_reservation "power7-larx" 3
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(and (eq_attr "type" "load_l")
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(and (eq_attr "type" "load_l")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,LSU_power7")
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"DU4_power7,LSU_power7")
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(define_insn_reservation "power7-stcx" 10
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(define_insn_reservation "power7-stcx" 10
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(and (eq_attr "type" "store_c")
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(and (eq_attr "type" "store_c")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,LSU_power7")
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"DU4_power7,LSU_power7")
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(define_insn_reservation "power7-vecload" 3
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(define_insn_reservation "power7-vecload" 3
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(and (eq_attr "type" "vecload")
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(and (eq_attr "type" "vecload")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7")
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"DU_power7,LSU_power7")
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(define_insn_reservation "power7-vecstore" 6
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(define_insn_reservation "power7-vecstore" 6
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(and (eq_attr "type" "vecstore")
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(and (eq_attr "type" "vecstore")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,LSU_power7+VSU_power7")
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"DU_power7,LSU_power7+VSU_power7")
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(define_insn_reservation "power7-sync" 11
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(define_insn_reservation "power7-sync" 11
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(and (eq_attr "type" "sync")
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(and (eq_attr "type" "sync")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,LSU_power7")
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"DU4_power7,LSU_power7")
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; FX Unit
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; FX Unit
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(define_insn_reservation "power7-integer" 1
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(define_insn_reservation "power7-integer" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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var_shift_rotate,exts,isel")
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var_shift_rotate,exts,isel")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,FXU_power7")
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"DU_power7,FXU_power7")
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(define_insn_reservation "power7-cntlz" 2
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(define_insn_reservation "power7-cntlz" 2
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(and (eq_attr "type" "cntlz")
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(and (eq_attr "type" "cntlz")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,FXU_power7")
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"DU_power7,FXU_power7")
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(define_insn_reservation "power7-two" 2
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(define_insn_reservation "power7-two" 2
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(and (eq_attr "type" "two")
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7+DU_power7,FXU_power7,FXU_power7")
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"DU_power7+DU_power7,FXU_power7,FXU_power7")
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(define_insn_reservation "power7-three" 3
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(define_insn_reservation "power7-three" 3
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(and (eq_attr "type" "three")
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
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"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
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(define_insn_reservation "power7-cmp" 1
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(define_insn_reservation "power7-cmp" 1
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(and (eq_attr "type" "cmp,fast_compare")
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(and (eq_attr "type" "cmp,fast_compare")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,FXU_power7")
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"DU_power7,FXU_power7")
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(define_insn_reservation "power7-compare" 2
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(define_insn_reservation "power7-compare" 2
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(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
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(and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,FXU_power7,FXU_power7")
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"DU2F_power7,FXU_power7,FXU_power7")
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(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
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(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
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(define_insn_reservation "power7-mul" 4
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(define_insn_reservation "power7-mul" 4
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(and (eq_attr "type" "imul,imul2,imul3,lmul")
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(and (eq_attr "type" "imul,imul2,imul3,lmul")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU_power7,FXU_power7")
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"DU_power7,FXU_power7")
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(define_insn_reservation "power7-mul-compare" 5
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(define_insn_reservation "power7-mul-compare" 5
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(and (eq_attr "type" "imul_compare,lmul_compare")
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(and (eq_attr "type" "imul_compare,lmul_compare")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
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"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
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(define_insn_reservation "power7-idiv" 36
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(define_insn_reservation "power7-idiv" 36
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(and (eq_attr "type" "idiv")
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,iu1_power7*36|iu2_power7*36")
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"DU2F_power7,iu1_power7*36|iu2_power7*36")
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(define_insn_reservation "power7-ldiv" 68
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(define_insn_reservation "power7-ldiv" 68
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(and (eq_attr "type" "ldiv")
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU2F_power7,iu1_power7*68|iu2_power7*68")
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"DU2F_power7,iu1_power7*68|iu2_power7*68")
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(define_insn_reservation "power7-isync" 1 ;
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(define_insn_reservation "power7-isync" 1 ;
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(and (eq_attr "type" "isync")
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(and (eq_attr "type" "isync")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"DU4_power7,FXU_power7")
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"DU4_power7,FXU_power7")
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; CR Unit
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; CR Unit
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(define_insn_reservation "power7-mtjmpr" 4
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(define_insn_reservation "power7-mtjmpr" 4
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(and (eq_attr "type" "mtjmpr")
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"du1_power7,FXU_power7")
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"du1_power7,FXU_power7")
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(define_insn_reservation "power7-mfjmpr" 5
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(define_insn_reservation "power7-mfjmpr" 5
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(and (eq_attr "type" "mfjmpr")
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"du1_power7,cru_power7+FXU_power7")
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"du1_power7,cru_power7+FXU_power7")
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(define_insn_reservation "power7-crlogical" 3
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(define_insn_reservation "power7-crlogical" 3
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(and (eq_attr "type" "cr_logical")
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(and (eq_attr "type" "cr_logical")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"du1_power7,cru_power7")
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"du1_power7,cru_power7")
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(define_insn_reservation "power7-delayedcr" 3
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(define_insn_reservation "power7-delayedcr" 3
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(and (eq_attr "type" "delayed_cr")
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(and (eq_attr "type" "delayed_cr")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"du1_power7,cru_power7")
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"du1_power7,cru_power7")
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|
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(define_insn_reservation "power7-mfcr" 6
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(define_insn_reservation "power7-mfcr" 6
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(and (eq_attr "type" "mfcr")
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"du1_power7,cru_power7")
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"du1_power7,cru_power7")
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|
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(define_insn_reservation "power7-mfcrf" 3
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(define_insn_reservation "power7-mfcrf" 3
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(and (eq_attr "type" "mfcrf")
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(and (eq_attr "type" "mfcrf")
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(eq_attr "cpu" "power7"))
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(eq_attr "cpu" "power7"))
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"du1_power7,cru_power7")
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"du1_power7,cru_power7")
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|
|
(define_insn_reservation "power7-mtcr" 3
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(define_insn_reservation "power7-mtcr" 3
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(and (eq_attr "type" "mtcr")
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU4_power7,cru_power7+FXU_power7")
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"DU4_power7,cru_power7+FXU_power7")
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|
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; BR Unit
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; BR Unit
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; Branches take dispatch Slot 4. The presence_sets prevent other insn from
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; Branches take dispatch Slot 4. The presence_sets prevent other insn from
|
; grabbing previous dispatch slots once this is assigned.
|
; grabbing previous dispatch slots once this is assigned.
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(define_insn_reservation "power7-branch" 3
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(define_insn_reservation "power7-branch" 3
|
(and (eq_attr "type" "jmpreg,branch")
|
(and (eq_attr "type" "jmpreg,branch")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"(du5_power7\
|
"(du5_power7\
|
|du4_power7+du5_power7\
|
|du4_power7+du5_power7\
|
|du3_power7+du4_power7+du5_power7\
|
|du3_power7+du4_power7+du5_power7\
|
|du2_power7+du3_power7+du4_power7+du5_power7\
|
|du2_power7+du3_power7+du4_power7+du5_power7\
|
|du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")
|
|du1_power7+du2_power7+du3_power7+du4_power7+du5_power7),bpu_power7")
|
|
|
|
|
; VS Unit (includes FP/VSX/VMX/DFP)
|
; VS Unit (includes FP/VSX/VMX/DFP)
|
(define_insn_reservation "power7-fp" 6
|
(define_insn_reservation "power7-fp" 6
|
(and (eq_attr "type" "fp,dmul")
|
(and (eq_attr "type" "fp,dmul")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU_power7,VSU_power7")
|
"DU_power7,VSU_power7")
|
|
|
(define_bypass 8 "power7-fp" "power7-branch")
|
(define_bypass 8 "power7-fp" "power7-branch")
|
|
|
(define_insn_reservation "power7-fpcompare" 4
|
(define_insn_reservation "power7-fpcompare" 4
|
(and (eq_attr "type" "fpcompare")
|
(and (eq_attr "type" "fpcompare")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU_power7,VSU_power7")
|
"DU_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-sdiv" 26
|
(define_insn_reservation "power7-sdiv" 26
|
(and (eq_attr "type" "sdiv")
|
(and (eq_attr "type" "sdiv")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU_power7,VSU_power7")
|
"DU_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-ddiv" 32
|
(define_insn_reservation "power7-ddiv" 32
|
(and (eq_attr "type" "ddiv")
|
(and (eq_attr "type" "ddiv")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU_power7,VSU_power7")
|
"DU_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-sqrt" 31
|
(define_insn_reservation "power7-sqrt" 31
|
(and (eq_attr "type" "ssqrt")
|
(and (eq_attr "type" "ssqrt")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU_power7,VSU_power7")
|
"DU_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-dsqrt" 43
|
(define_insn_reservation "power7-dsqrt" 43
|
(and (eq_attr "type" "dsqrt")
|
(and (eq_attr "type" "dsqrt")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"DU_power7,VSU_power7")
|
"DU_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-vecsimple" 2
|
(define_insn_reservation "power7-vecsimple" 2
|
(and (eq_attr "type" "vecsimple")
|
(and (eq_attr "type" "vecsimple")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"du1_power7,VSU_power7")
|
"du1_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-veccmp" 7
|
(define_insn_reservation "power7-veccmp" 7
|
(and (eq_attr "type" "veccmp")
|
(and (eq_attr "type" "veccmp")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"du1_power7,VSU_power7")
|
"du1_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-vecfloat" 7
|
(define_insn_reservation "power7-vecfloat" 7
|
(and (eq_attr "type" "vecfloat")
|
(and (eq_attr "type" "vecfloat")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"du1_power7,VSU_power7")
|
"du1_power7,VSU_power7")
|
|
|
(define_bypass 6 "power7-vecfloat" "power7-vecfloat")
|
(define_bypass 6 "power7-vecfloat" "power7-vecfloat")
|
|
|
(define_insn_reservation "power7-veccomplex" 7
|
(define_insn_reservation "power7-veccomplex" 7
|
(and (eq_attr "type" "veccomplex")
|
(and (eq_attr "type" "veccomplex")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"du1_power7,VSU_power7")
|
"du1_power7,VSU_power7")
|
|
|
(define_insn_reservation "power7-vecperm" 3
|
(define_insn_reservation "power7-vecperm" 3
|
(and (eq_attr "type" "vecperm")
|
(and (eq_attr "type" "vecperm")
|
(eq_attr "cpu" "power7"))
|
(eq_attr "cpu" "power7"))
|
"du2_power7,VSU_power7")
|
"du2_power7,VSU_power7")
|
|
|
