;; Predicate definitions for Renesas RX.
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;; Predicate definitions for Renesas RX.
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;; Contributed by Red Hat.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; Check that the operand is suitable for a call insn.
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;; Check that the operand is suitable for a call insn.
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;; Only registers and symbol refs are allowed.
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;; Only registers and symbol refs are allowed.
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(define_predicate "rx_call_operand"
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(define_predicate "rx_call_operand"
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(match_code "symbol_ref,reg")
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(match_code "symbol_ref,reg")
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)
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)
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;; For sibcall operations we can only use a symbolic address.
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;; For sibcall operations we can only use a symbolic address.
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(define_predicate "rx_symbolic_call_operand"
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(define_predicate "rx_symbolic_call_operand"
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(match_code "symbol_ref")
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(match_code "symbol_ref")
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)
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)
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;; Check that the operand is suitable for a shift insn
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;; Check that the operand is suitable for a shift insn
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;; Only small integers or a value in a register are permitted.
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;; Only small integers or a value in a register are permitted.
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(define_predicate "rx_shift_operand"
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(define_predicate "rx_shift_operand"
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(match_code "const_int,reg")
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(match_code "const_int,reg")
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{
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{
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if (CONST_INT_P (op))
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if (CONST_INT_P (op))
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return IN_RANGE (INTVAL (op), 0, 31);
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return IN_RANGE (INTVAL (op), 0, 31);
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return true;
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return true;
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}
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}
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)
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)
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(define_predicate "rx_constshift_operand"
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(define_predicate "rx_constshift_operand"
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(match_code "const_int")
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(match_code "const_int")
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{
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{
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return IN_RANGE (INTVAL (op), 0, 31);
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return IN_RANGE (INTVAL (op), 0, 31);
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}
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}
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)
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)
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;; Check that the operand is suitable as the source operand
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;; Check that the operand is suitable as the source operand
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;; for a logic or arithmeitc instruction. Registers, integers
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;; for a logic or arithmeitc instruction. Registers, integers
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;; and a restricted subset of memory addresses are allowed.
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;; and a restricted subset of memory addresses are allowed.
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(define_predicate "rx_source_operand"
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(define_predicate "rx_source_operand"
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(match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem")
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(match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem")
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{
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{
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if (CONSTANT_P (op))
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if (CONSTANT_P (op))
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return rx_is_legitimate_constant (op);
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return rx_is_legitimate_constant (op);
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if (! MEM_P (op))
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if (! MEM_P (op))
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return true;
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return true;
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/* Do not allow size conversions whilst accessing memory. */
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/* Do not allow size conversions whilst accessing memory. */
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if (GET_MODE (op) != mode)
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if (GET_MODE (op) != mode)
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return false;
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return false;
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return rx_is_restricted_memory_address (XEXP (op, 0), mode);
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return rx_is_restricted_memory_address (XEXP (op, 0), mode);
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}
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}
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)
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)
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;; Check that the operand is suitable as the source operand
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;; Check that the operand is suitable as the source operand
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;; for a comparison instruction. This is the same as
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;; for a comparison instruction. This is the same as
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;; rx_source_operand except that SUBREGs are allowed but
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;; rx_source_operand except that SUBREGs are allowed but
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;; CONST_INTs are not.
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;; CONST_INTs are not.
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(define_predicate "rx_compare_operand"
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(define_predicate "rx_compare_operand"
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(match_code "subreg,reg,mem")
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(match_code "subreg,reg,mem")
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{
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{
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if (GET_CODE (op) == SUBREG)
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if (GET_CODE (op) == SUBREG)
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return REG_P (XEXP (op, 0));
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return REG_P (XEXP (op, 0));
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if (! MEM_P (op))
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if (! MEM_P (op))
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return true;
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return true;
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return rx_is_restricted_memory_address (XEXP (op, 0), mode);
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return rx_is_restricted_memory_address (XEXP (op, 0), mode);
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}
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}
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)
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)
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;; Return true if OP is a store multiple operation. This looks like:
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;; Return true if OP is a store multiple operation. This looks like:
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;;
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;;
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;; [(set (SP) (MINUS (SP) (INT)))
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;; [(set (SP) (MINUS (SP) (INT)))
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;; (set (MEM (SP)) (REG))
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;; (set (MEM (SP)) (REG))
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;; (set (MEM (MINUS (SP) (INT))) (REG)) {optionally repeated}
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;; (set (MEM (MINUS (SP) (INT))) (REG)) {optionally repeated}
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;; ]
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;; ]
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(define_special_predicate "rx_store_multiple_vector"
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(define_special_predicate "rx_store_multiple_vector"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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unsigned int src_regno;
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unsigned int src_regno;
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rtx element;
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rtx element;
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int i;
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int i;
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/* Perform a quick check so we don't blow up below. */
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/* Perform a quick check so we don't blow up below. */
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if (count <= 2)
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if (count <= 2)
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return false;
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return false;
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/* Check that the first element of the vector is the stack adjust. */
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/* Check that the first element of the vector is the stack adjust. */
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element = XVECEXP (op, 0, 0);
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element = XVECEXP (op, 0, 0);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| REGNO (SET_DEST (element)) != SP_REG
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|| REGNO (SET_DEST (element)) != SP_REG
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|| GET_CODE (SET_SRC (element)) != MINUS
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|| GET_CODE (SET_SRC (element)) != MINUS
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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return false;
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return false;
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/* Check that the next element is the first push. */
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/* Check that the next element is the first push. */
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element = XVECEXP (op, 0, 1);
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element = XVECEXP (op, 0, 1);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_SRC (element))
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|| ! REG_P (SET_SRC (element))
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|| GET_MODE (SET_SRC (element)) != SImode
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|| GET_MODE (SET_SRC (element)) != SImode
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|| ! MEM_P (SET_DEST (element))
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|| ! MEM_P (SET_DEST (element))
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|| GET_MODE (SET_DEST (element)) != SImode
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|| GET_MODE (SET_DEST (element)) != SImode
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|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
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|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
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|| ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
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|| ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
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|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
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|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
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|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
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!= GET_MODE_SIZE (SImode))
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!= GET_MODE_SIZE (SImode))
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return false;
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return false;
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src_regno = REGNO (SET_SRC (element));
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src_regno = REGNO (SET_SRC (element));
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/* Check that the remaining elements use SP-
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/* Check that the remaining elements use SP-
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addressing and decreasing register numbers. */
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addressing and decreasing register numbers. */
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for (i = 2; i < count; i++)
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for (i = 2; i < count; i++)
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{
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{
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element = XVECEXP (op, 0, i);
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element = XVECEXP (op, 0, i);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_SRC (element))
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|| ! REG_P (SET_SRC (element))
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|| GET_MODE (SET_SRC (element)) != SImode
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|| GET_MODE (SET_SRC (element)) != SImode
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|| REGNO (SET_SRC (element)) != src_regno - (i - 1)
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|| REGNO (SET_SRC (element)) != src_regno - (i - 1)
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|| ! MEM_P (SET_DEST (element))
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|| ! MEM_P (SET_DEST (element))
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|| GET_MODE (SET_DEST (element)) != SImode
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|| GET_MODE (SET_DEST (element)) != SImode
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|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
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|| GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
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|| ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
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|| ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
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|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
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|| REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
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|| ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
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!= i * GET_MODE_SIZE (SImode))
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!= i * GET_MODE_SIZE (SImode))
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return false;
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return false;
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}
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}
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return true;
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return true;
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})
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})
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;; Return true if OP is a load multiple operation.
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;; Return true if OP is a load multiple operation.
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;; This looks like:
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;; This looks like:
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;; [(set (SP) (PLUS (SP) (INT)))
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;; [(set (SP) (PLUS (SP) (INT)))
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;; (set (REG) (MEM (SP)))
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;; (set (REG) (MEM (SP)))
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;; (set (REG) (MEM (PLUS (SP) (INT)))) {optionally repeated}
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;; (set (REG) (MEM (PLUS (SP) (INT)))) {optionally repeated}
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;; ]
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;; ]
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(define_special_predicate "rx_load_multiple_vector"
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(define_special_predicate "rx_load_multiple_vector"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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unsigned int dest_regno;
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unsigned int dest_regno;
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rtx element;
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rtx element;
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int i;
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int i;
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/* Perform a quick check so we don't blow up below. */
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/* Perform a quick check so we don't blow up below. */
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if (count <= 2)
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if (count <= 2)
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return false;
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return false;
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/* Check that the first element of the vector is the stack adjust. */
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/* Check that the first element of the vector is the stack adjust. */
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element = XVECEXP (op, 0, 0);
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element = XVECEXP (op, 0, 0);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| REGNO (SET_DEST (element)) != SP_REG
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|| REGNO (SET_DEST (element)) != SP_REG
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|| GET_CODE (SET_SRC (element)) != PLUS
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|| GET_CODE (SET_SRC (element)) != PLUS
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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return false;
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return false;
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/* Check that the next element is the first push. */
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/* Check that the next element is the first push. */
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element = XVECEXP (op, 0, 1);
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element = XVECEXP (op, 0, 1);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| ! MEM_P (SET_SRC (element))
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|| ! MEM_P (SET_SRC (element))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
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return false;
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return false;
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dest_regno = REGNO (SET_DEST (element));
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dest_regno = REGNO (SET_DEST (element));
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/* Check that the remaining elements use SP+
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/* Check that the remaining elements use SP+
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addressing and incremental register numbers. */
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addressing and incremental register numbers. */
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for (i = 2; i < count; i++)
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for (i = 2; i < count; i++)
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{
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{
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element = XVECEXP (op, 0, i);
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element = XVECEXP (op, 0, i);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| GET_MODE (SET_DEST (element)) != SImode
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|| GET_MODE (SET_DEST (element)) != SImode
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|| REGNO (SET_DEST (element)) != dest_regno + (i - 1)
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|| REGNO (SET_DEST (element)) != dest_regno + (i - 1)
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|| ! MEM_P (SET_SRC (element))
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|| ! MEM_P (SET_SRC (element))
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|| GET_MODE (SET_SRC (element)) != SImode
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|| GET_MODE (SET_SRC (element)) != SImode
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|| GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
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|| GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
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|| ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
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|| ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
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|| REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
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|| REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
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|| ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
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!= (i - 1) * GET_MODE_SIZE (SImode))
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!= (i - 1) * GET_MODE_SIZE (SImode))
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return false;
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return false;
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}
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}
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return true;
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return true;
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})
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})
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;; Return true if OP is a pop-and-return load multiple operation.
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;; Return true if OP is a pop-and-return load multiple operation.
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;; This looks like:
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;; This looks like:
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;; [(set (SP) (PLUS (SP) (INT)))
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;; [(set (SP) (PLUS (SP) (INT)))
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;; (set (REG) (MEM (SP)))
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;; (set (REG) (MEM (SP)))
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;; (set (REG) (MEM (PLUS (SP) (INT)))) {optional and possibly repeated}
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;; (set (REG) (MEM (PLUS (SP) (INT)))) {optional and possibly repeated}
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;; (return)
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;; (return)
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;; ]
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;; ]
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(define_special_predicate "rx_rtsd_vector"
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(define_special_predicate "rx_rtsd_vector"
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(match_code "parallel")
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(match_code "parallel")
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{
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{
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int count = XVECLEN (op, 0);
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int count = XVECLEN (op, 0);
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unsigned int dest_regno;
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unsigned int dest_regno;
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rtx element;
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rtx element;
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int i;
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int i;
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|
|
/* Perform a quick check so we don't blow up below. */
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/* Perform a quick check so we don't blow up below. */
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if (count <= 2)
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if (count <= 2)
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return false;
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return false;
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/* Check that the first element of the vector is the stack adjust. */
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/* Check that the first element of the vector is the stack adjust. */
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element = XVECEXP (op, 0, 0);
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element = XVECEXP (op, 0, 0);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| REGNO (SET_DEST (element)) != SP_REG
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|| REGNO (SET_DEST (element)) != SP_REG
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|| GET_CODE (SET_SRC (element)) != PLUS
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|| GET_CODE (SET_SRC (element)) != PLUS
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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|| ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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return false;
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return false;
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|
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/* Check that the next element is the first push. */
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/* Check that the next element is the first push. */
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element = XVECEXP (op, 0, 1);
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element = XVECEXP (op, 0, 1);
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if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| ! MEM_P (SET_SRC (element))
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|| ! MEM_P (SET_SRC (element))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| ! REG_P (XEXP (SET_SRC (element), 0))
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
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|| REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
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return false;
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return false;
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|
|
dest_regno = REGNO (SET_DEST (element));
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dest_regno = REGNO (SET_DEST (element));
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|
|
/* Check that the remaining elements, if any, and except
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/* Check that the remaining elements, if any, and except
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for the last one, use SP+ addressing and incremental
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for the last one, use SP+ addressing and incremental
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register numbers. */
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register numbers. */
|
for (i = 2; i < count - 1; i++)
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for (i = 2; i < count - 1; i++)
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{
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{
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element = XVECEXP (op, 0, i);
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element = XVECEXP (op, 0, i);
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|
|
if ( ! SET_P (element)
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if ( ! SET_P (element)
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|| ! REG_P (SET_DEST (element))
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|| ! REG_P (SET_DEST (element))
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|| GET_MODE (SET_DEST (element)) != SImode
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|| GET_MODE (SET_DEST (element)) != SImode
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|| REGNO (SET_DEST (element)) != dest_regno + (i - 1)
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|| REGNO (SET_DEST (element)) != dest_regno + (i - 1)
|
|| ! MEM_P (SET_SRC (element))
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|| ! MEM_P (SET_SRC (element))
|
|| GET_MODE (SET_SRC (element)) != SImode
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|| GET_MODE (SET_SRC (element)) != SImode
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|| GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
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|| GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
|
|| ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
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|| ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
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|| REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
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|| REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
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|| ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
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|| ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
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|| INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
|
|| INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
|
!= (i - 1) * GET_MODE_SIZE (SImode))
|
!= (i - 1) * GET_MODE_SIZE (SImode))
|
return false;
|
return false;
|
}
|
}
|
|
|
/* The last element must be a RETURN. */
|
/* The last element must be a RETURN. */
|
element = XVECEXP (op, 0, count - 1);
|
element = XVECEXP (op, 0, count - 1);
|
return GET_CODE (element) == RETURN;
|
return GET_CODE (element) == RETURN;
|
})
|
})
|
|
|
