;; Machine description for Sunplus S+CORE
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;; Machine description for Sunplus S+CORE
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;; Copyright (C) 2005, 2007
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;; Copyright (C) 2005, 2007
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;; Free Software Foundation, Inc.
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;; Free Software Foundation, Inc.
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;; Contributed by Sunnorth.
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;; Contributed by Sunnorth.
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;; This file is part of GCC.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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; branch conditional branch
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; branch conditional branch
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; jump unconditional jump
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; jump unconditional jump
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; call unconditional call
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; call unconditional call
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; load load instruction(s)
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; load load instruction(s)
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; store store instruction(s)
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; store store instruction(s)
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; cmp integer compare
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; cmp integer compare
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; arith integer arithmetic instruction
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; arith integer arithmetic instruction
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; move data movement within same register set
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; move data movement within same register set
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; const load constant
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; const load constant
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; nop no operation
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; nop no operation
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; mul integer multiply
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; mul integer multiply
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; div integer divide
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; div integer divide
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; cndmv conditional moves
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; cndmv conditional moves
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; fce transfer from hi/lo registers
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; fce transfer from hi/lo registers
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; tce transfer to hi/lo registers
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; tce transfer to hi/lo registers
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; fsr transfer from special registers
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; fsr transfer from special registers
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; tsr transfer to special registers
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; tsr transfer to special registers
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(define_constants
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(define_constants
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[(CC_REGNUM 33)
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[(CC_REGNUM 33)
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(T_REGNUM 34)
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(T_REGNUM 34)
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(RA_REGNUM 3)
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(RA_REGNUM 3)
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(SP_REGNUM 0)
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(SP_REGNUM 0)
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(AT_REGNUM 1)
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(AT_REGNUM 1)
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(FP_REGNUM 2)
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(FP_REGNUM 2)
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(RT_REGNUM 4)
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(RT_REGNUM 4)
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(GP_REGNUM 28)
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(GP_REGNUM 28)
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(EH_REGNUM 29)
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(EH_REGNUM 29)
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(HI_REGNUM 48)
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(HI_REGNUM 48)
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(LO_REGNUM 49)
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(LO_REGNUM 49)
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(CN_REGNUM 50)
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(CN_REGNUM 50)
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(LC_REGNUM 51)
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(LC_REGNUM 51)
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(SC_REGNUM 52)])
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(SC_REGNUM 52)])
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(define_constants
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(define_constants
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[(BITTST 0)
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[(BITTST 0)
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(CPLOAD 1)
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(CPLOAD 1)
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(CPRESTORE 2)
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(CPRESTORE 2)
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(SCB 3)
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(SCB 3)
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(SCW 4)
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(SCW 4)
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(SCE 5)
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(SCE 5)
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(SCLC 6)
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(SCLC 6)
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(LCB 7)
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(LCB 7)
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(LCW 8)
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(LCW 8)
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(LCE 9)
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(LCE 9)
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(SFFS 10)])
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(SFFS 10)])
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(define_attr "type"
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(define_attr "type"
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"unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr"
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"unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr"
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(const_string "unknown"))
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(const_string "unknown"))
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(define_attr "mode" "unknown,QI,HI,SI,DI"
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(define_attr "mode" "unknown,QI,HI,SI,DI"
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(const_string "unknown"))
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(const_string "unknown"))
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(define_attr "length" "" (const_int 4))
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(define_attr "length" "" (const_int 4))
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(define_attr "up_c" "yes,no"
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(define_attr "up_c" "yes,no"
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(const_string "no"))
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(const_string "no"))
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(include "score-generic.md")
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(include "score-generic.md")
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(include "predicates.md")
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(include "predicates.md")
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(define_expand "movqi"
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(define_expand "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand")
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[(set (match_operand:QI 0 "nonimmediate_operand")
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(match_operand:QI 1 "general_operand"))]
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(match_operand:QI 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], QImode))
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&& !register_operand (operands[1], QImode))
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{
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{
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operands[1] = force_reg (QImode, operands[1]);
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operands[1] = force_reg (QImode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movqi_insns_score7"
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(define_insn "*movqi_insns_score7"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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(match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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(match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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"(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
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"(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
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&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
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&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return score_limm (operands);
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case 0: return score_limm (operands);
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case 1: return score_move (operands);
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case 1: return score_move (operands);
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case 2: return score_linsn (operands, SCORE_BYTE, false);
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case 2: return score_linsn (operands, SCORE_BYTE, false);
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case 3: return score_sinsn (operands, SCORE_BYTE);
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case 3: return score_sinsn (operands, SCORE_BYTE);
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case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 7: return \"mtsr\t%1, %0\";
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case 7: return \"mtsr\t%1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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(set_attr "mode" "QI")])
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(set_attr "mode" "QI")])
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(define_insn "*movqi_insns_score3"
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(define_insn "*movqi_insns_score3"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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(match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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(match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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"(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
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"(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
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&& (TARGET_SCORE3)"
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&& (TARGET_SCORE3)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return score_limm (operands);
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case 0: return score_limm (operands);
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case 1: return \"mv!\t%0, %1\";
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case 1: return \"mv!\t%0, %1\";
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case 2: return score_linsn (operands, SCORE_BYTE, false);
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case 2: return score_linsn (operands, SCORE_BYTE, false);
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case 3: return score_sinsn (operands, SCORE_BYTE);
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case 3: return score_sinsn (operands, SCORE_BYTE);
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case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
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case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
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case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
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case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
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case 6: return \"mfsr\t%0, %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 7: return \"mtsr\t%1, %0\";
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case 7: return \"mtsr\t%1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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(set_attr "length" "6,2,6,6,4,4,4,4")
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(set_attr "length" "6,2,6,6,4,4,4,4")
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(set_attr "mode" "QI")])
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(set_attr "mode" "QI")])
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(define_expand "movhi"
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(define_expand "movhi"
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[(set (match_operand:HI 0 "nonimmediate_operand")
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[(set (match_operand:HI 0 "nonimmediate_operand")
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(match_operand:HI 1 "general_operand"))]
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(match_operand:HI 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], HImode))
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&& !register_operand (operands[1], HImode))
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{
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{
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operands[1] = force_reg (HImode, operands[1]);
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operands[1] = force_reg (HImode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movhi_insns_score7"
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(define_insn "*movhi_insns_score7"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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(match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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(match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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"(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
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"(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
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&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
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&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return score_limm (operands);
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case 0: return score_limm (operands);
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case 1: return score_move (operands);
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case 1: return score_move (operands);
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case 2: return score_linsn (operands, SCORE_HWORD, false);
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case 2: return score_linsn (operands, SCORE_HWORD, false);
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case 3: return score_sinsn (operands, SCORE_HWORD);
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case 3: return score_sinsn (operands, SCORE_HWORD);
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case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 7: return \"mtsr\t%1, %0\";
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case 7: return \"mtsr\t%1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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(set_attr "mode" "HI")])
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(set_attr "mode" "HI")])
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(define_insn "*movhi_insns_score3"
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(define_insn "*movhi_insns_score3"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
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(match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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(match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
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"(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
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"(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
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&& (TARGET_SCORE3)"
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&& (TARGET_SCORE3)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0: return score_limm (operands);
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case 0: return score_limm (operands);
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case 1: return \"mv!\t%0, %1\";
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case 1: return \"mv!\t%0, %1\";
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case 2: return score_linsn (operands, SCORE_HWORD, false);
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case 2: return score_linsn (operands, SCORE_HWORD, false);
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case 3: return score_sinsn (operands, SCORE_HWORD);
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case 3: return score_sinsn (operands, SCORE_HWORD);
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case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
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case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
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case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
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case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
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case 6: return \"mfsr\t%0, %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 7: return \"mtsr\t%1, %0\";
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case 7: return \"mtsr\t%1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
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(set_attr "length" "6,2,6,6,4,4,4,4")
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(set_attr "length" "6,2,6,6,4,4,4,4")
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(set_attr "mode" "HI")])
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(set_attr "mode" "HI")])
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(define_expand "movsi"
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(define_expand "movsi"
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[(set (match_operand:SI 0 "nonimmediate_operand")
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[(set (match_operand:SI 0 "nonimmediate_operand")
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(match_operand:SI 1 "general_operand"))]
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(match_operand:SI 1 "general_operand"))]
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""
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""
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{
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{
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if (MEM_P (operands[0])
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if (MEM_P (operands[0])
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&& !register_operand (operands[1], SImode))
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&& !register_operand (operands[1], SImode))
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{
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{
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operands[1] = force_reg (SImode, operands[1]);
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operands[1] = force_reg (SImode, operands[1]);
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}
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}
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})
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})
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(define_insn "*movsi_insns_score7"
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(define_insn "*movsi_insns_score7"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
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(match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
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(match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
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"(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
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"(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
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&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
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&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0:
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case 0:
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if (GET_CODE (operands[1]) != CONST_INT)
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if (GET_CODE (operands[1]) != CONST_INT)
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return \"la\t%0, %1\";
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return \"la\t%0, %1\";
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else
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else
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return score_limm (operands);
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return score_limm (operands);
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case 1: return score_move (operands);
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case 1: return score_move (operands);
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case 2: return score_linsn (operands, SCORE_WORD, false);
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case 2: return score_linsn (operands, SCORE_WORD, false);
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case 3: return score_sinsn (operands, SCORE_WORD);
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case 3: return score_sinsn (operands, SCORE_WORD);
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case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
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case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 6: return \"mfsr\t%0, %1\";
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case 7: return \"mtsr\t%1, %0\";
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case 7: return \"mtsr\t%1, %0\";
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case 8: return \"mfcr\t%0, %1\";
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case 8: return \"mfcr\t%0, %1\";
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case 9: return \"mtcr\t%1, %0\";
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case 9: return \"mtcr\t%1, %0\";
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default: gcc_unreachable ();
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default: gcc_unreachable ();
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}
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}
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}
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}
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
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[(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn "*movsi_insns_score3"
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(define_insn "*movsi_insns_score3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=ed,e,d,d,m,d,*x,d,*a")
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[(set (match_operand:SI 0 "nonimmediate_operand" "=ed,e,d,d,m,d,*x,d,*a")
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(match_operand:SI 1 "general_operand" "i,e,d,m,d,*x,d,*a,d"))]
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(match_operand:SI 1 "general_operand" "i,e,d,m,d,*x,d,*a,d"))]
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"(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
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"(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
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&& (TARGET_SCORE3)"
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&& (TARGET_SCORE3)"
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{
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{
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switch (which_alternative)
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switch (which_alternative)
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{
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{
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case 0:
|
case 0:
|
if (GET_CODE (operands[1]) != CONST_INT)
|
if (GET_CODE (operands[1]) != CONST_INT)
|
return \"ldi48\t%0, %1\";
|
return \"ldi48\t%0, %1\";
|
else
|
else
|
return score_limm (operands);
|
return score_limm (operands);
|
case 1: return \"mv!\t%0, %1\";
|
case 1: return \"mv!\t%0, %1\";
|
case 2: return \"mv!\t%0, %1\";
|
case 2: return \"mv!\t%0, %1\";
|
case 3: return score_linsn (operands, SCORE_WORD, false);
|
case 3: return score_linsn (operands, SCORE_WORD, false);
|
case 4: return score_sinsn (operands, SCORE_WORD);
|
case 4: return score_sinsn (operands, SCORE_WORD);
|
case 5: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
|
case 5: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
|
case 6: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
|
case 6: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
|
case 7: return \"mfsr\t%0, %1\";
|
case 7: return \"mfsr\t%0, %1\";
|
case 8: return \"mtsr\t%1, %0\";
|
case 8: return \"mtsr\t%1, %0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith,move,move,load,store,fce,tce,fsr,tsr")
|
[(set_attr "type" "arith,move,move,load,store,fce,tce,fsr,tsr")
|
(set_attr "length" "6,2,2,6,6,4,4,4,4")
|
(set_attr "length" "6,2,2,6,6,4,4,4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn_and_split "movdi"
|
(define_insn_and_split "movdi"
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
|
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
|
(match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
|
(match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(const_int 0)]
|
[(const_int 0)]
|
{
|
{
|
score_movdi (operands);
|
score_movdi (operands);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "movsf"
|
(define_expand "movsf"
|
[(set (match_operand:SF 0 "nonimmediate_operand")
|
[(set (match_operand:SF 0 "nonimmediate_operand")
|
(match_operand:SF 1 "general_operand"))]
|
(match_operand:SF 1 "general_operand"))]
|
""
|
""
|
{
|
{
|
if (MEM_P (operands[0])
|
if (MEM_P (operands[0])
|
&& !register_operand (operands[1], SFmode))
|
&& !register_operand (operands[1], SFmode))
|
{
|
{
|
operands[1] = force_reg (SFmode, operands[1]);
|
operands[1] = force_reg (SFmode, operands[1]);
|
}
|
}
|
})
|
})
|
|
|
(define_insn "*movsf_insns_score7"
|
(define_insn "*movsf_insns_score7"
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
|
(match_operand:SF 1 "general_operand" "i,d,m,d"))]
|
(match_operand:SF 1 "general_operand" "i,d,m,d"))]
|
"(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
|
"(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
|
&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
&& (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"li\t%0, %D1\";;
|
case 0: return \"li\t%0, %D1\";;
|
case 1: return score_move (operands);
|
case 1: return score_move (operands);
|
case 2: return score_linsn (operands, SCORE_WORD, false);
|
case 2: return score_linsn (operands, SCORE_WORD, false);
|
case 3: return score_sinsn (operands, SCORE_WORD);
|
case 3: return score_sinsn (operands, SCORE_WORD);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith,move,load,store")
|
[(set_attr "type" "arith,move,load,store")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*movsf_insns_score3"
|
(define_insn "*movsf_insns_score3"
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
|
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
|
(match_operand:SF 1 "general_operand" "i,d,m,d"))]
|
(match_operand:SF 1 "general_operand" "i,d,m,d"))]
|
"(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
|
"(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
|
&& (TARGET_SCORE3)"
|
&& (TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"li\t%0, %D1\";
|
case 0: return \"li\t%0, %D1\";
|
case 1: return \"mv!\t%0, %1\";
|
case 1: return \"mv!\t%0, %1\";
|
case 2: return score_linsn (operands, SCORE_WORD, false);
|
case 2: return score_linsn (operands, SCORE_WORD, false);
|
case 3: return score_sinsn (operands, SCORE_WORD);
|
case 3: return score_sinsn (operands, SCORE_WORD);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith,move,load,store")
|
[(set_attr "type" "arith,move,load,store")
|
(set_attr "length" "4,2,6,6")
|
(set_attr "length" "4,2,6,6")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn_and_split "movdf"
|
(define_insn_and_split "movdf"
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
|
(match_operand:DF 1 "general_operand" "i,d,m,d"))]
|
(match_operand:DF 1 "general_operand" "i,d,m,d"))]
|
""
|
""
|
"#"
|
"#"
|
"reload_completed"
|
"reload_completed"
|
[(const_int 0)]
|
[(const_int 0)]
|
{
|
{
|
score_movdi (operands);
|
score_movdi (operands);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "addsi3"
|
(define_expand "addsi3"
|
[(set (match_operand:SI 0 "score_register_operand" )
|
[(set (match_operand:SI 0 "score_register_operand" )
|
(plus:SI (match_operand:SI 1 "score_register_operand")
|
(plus:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))]
|
(match_operand:SI 2 "arith_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*addsi3_score7"
|
(define_insn "*addsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d")))]
|
(match_operand:SI 2 "arith_operand" "I,L,N,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis\t%0, %U2\";
|
case 0: return \"addis\t%0, %U2\";
|
case 1: return score_select_add_imm (operands, false);
|
case 1: return score_select_add_imm (operands, false);
|
case 2: return \"addri\t%0, %1, %c2\";
|
case 2: return \"addri\t%0, %1, %c2\";
|
case 3: return score_select (operands, "add", true, "", false);
|
case 3: return score_select (operands, "add", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*addsi3_score3"
|
(define_insn "*addsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(plus:SI (match_operand:SI 1 "score_register_operand" "%0,0,d,d")
|
(plus:SI (match_operand:SI 1 "score_register_operand" "%0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d")))]
|
(match_operand:SI 2 "arith_operand" "I,L,N,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis\t%0, %U2\";
|
case 0: return \"addis\t%0, %U2\";
|
case 1: return score_select_add_imm (operands, false);
|
case 1: return score_select_add_imm (operands, false);
|
case 2: return \"addri\t%0, %1, %c2\";
|
case 2: return \"addri\t%0, %1, %c2\";
|
case 3: return score_select (operands, "add", true, "", false);
|
case 3: return score_select (operands, "add", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*addsi3_cmp_score7"
|
(define_insn "*addsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (plus:SI
|
(compare:CC_NZ (plus:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis.c\t%0, %U2\";
|
case 0: return \"addis.c\t%0, %U2\";
|
case 1: return score_select_add_imm (operands, true);
|
case 1: return score_select_add_imm (operands, true);
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "add", true, "", true);
|
case 3: return score_select (operands, "add", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*addsi3_cmp_score3"
|
(define_insn "*addsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (plus:SI
|
(compare:CC_NZ (plus:SI
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis.c\t%0, %U2\";
|
case 0: return \"addis.c\t%0, %U2\";
|
case 1: return score_select_add_imm (operands, true);
|
case 1: return score_select_add_imm (operands, true);
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "add", true, "", true);
|
case 3: return score_select (operands, "add", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*addsi3_ucc_score7"
|
(define_insn "*addsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (plus:SI
|
(compare:CC_NZ (plus:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis.c\t%0, %U2\";
|
case 0: return \"addis.c\t%0, %U2\";
|
case 1: return score_select_add_imm (operands, true);
|
case 1: return score_select_add_imm (operands, true);
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "add", true, "", true);
|
case 3: return score_select (operands, "add", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*addsi3_ucc_score3"
|
(define_insn "*addsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (plus:SI
|
(compare:CC_NZ (plus:SI
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(match_operand:SI 2 "arith_operand" "I,L,N,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"addis.c\t%0, %U2\";
|
case 0: return \"addis.c\t%0, %U2\";
|
case 1: return score_select_add_imm (operands, true);
|
case 1: return score_select_add_imm (operands, true);
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 2: return \"addri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "add", true, "", true);
|
case 3: return score_select (operands, "add", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "adddi3"
|
(define_expand "adddi3"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "score_register_operand")
|
[(set (match_operand:DI 0 "score_register_operand")
|
(plus:DI (match_operand:DI 1 "score_register_operand")
|
(plus:DI (match_operand:DI 1 "score_register_operand")
|
(match_operand:DI 2 "score_register_operand")))
|
(match_operand:DI 2 "score_register_operand")))
|
(clobber (reg:CC CC_REGNUM))])]
|
(clobber (reg:CC CC_REGNUM))])]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*adddi3_score7"
|
(define_insn "*adddi3_score7"
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
(plus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(plus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
add! %L0, %L2\;addc! %H0, %H2
|
add! %L0, %L2\;addc! %H0, %H2
|
add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"
|
add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "*adddi3_score3"
|
(define_insn "*adddi3_score3"
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
(plus:DI (match_operand:DI 1 "score_register_operand" "d")
|
(plus:DI (match_operand:DI 1 "score_register_operand" "d")
|
(match_operand:DI 2 "score_register_operand" "d")))
|
(match_operand:DI 2 "score_register_operand" "d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"add.c\t%L0, %L1, %L2\;addc\t%H0, %H1, %H2"
|
"add.c\t%L0, %L1, %L2\;addc\t%H0, %H1, %H2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "8")
|
(set_attr "length" "8")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_expand "subsi3"
|
(define_expand "subsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(minus:SI (match_operand:SI 1 "score_register_operand")
|
(minus:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "score_register_operand")))]
|
(match_operand:SI 2 "score_register_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*subsi3_score7"
|
(define_insn "*subsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(minus:SI (match_operand:SI 1 "register_operand" "d")
|
(minus:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))]
|
(match_operand:SI 2 "register_operand" "d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
return score_select (operands, "sub", false, "", false);
|
return score_select (operands, "sub", false, "", false);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*subsi3_score3"
|
(define_insn "*subsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d")
|
(minus:SI (match_operand:SI 1 "score_register_operand" "0,d")
|
(minus:SI (match_operand:SI 1 "score_register_operand" "0,d")
|
(match_operand:SI 2 "score_register_operand" "e,d")))]
|
(match_operand:SI 2 "score_register_operand" "e,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"sub!\t%0, %2\";
|
case 0: return \"sub!\t%0, %2\";
|
case 1: return score_select (operands, "sub", false, "", false);
|
case 1: return score_select (operands, "sub", false, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "2,4")
|
(set_attr "length" "2,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*subsi3_cmp_score7"
|
(define_insn "*subsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
return score_select (operands, "sub", false, "", true);
|
return score_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*subsi3_cmp_score3"
|
(define_insn "*subsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
return score_select (operands, "sub", false, "", true);
|
return score_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
(minus:SI (match_operand:SI 1 "g32reg_operand" "")
|
(minus:SI (match_operand:SI 1 "g32reg_operand" "")
|
(match_operand:SI 2 "g32reg_operand" "")))
|
(match_operand:SI 2 "g32reg_operand" "")))
|
(set (reg:CC CC_REGNUM)
|
(set (reg:CC CC_REGNUM)
|
(compare:CC (match_dup 1) (match_dup 2)))]
|
(compare:CC (match_dup 1) (match_dup 2)))]
|
""
|
""
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_dup 1) (match_dup 2)))
|
(compare:CC (match_dup 1) (match_dup 2)))
|
(set (match_dup 0)
|
(set (match_dup 0)
|
(minus:SI (match_dup 1) (match_dup 2)))])
|
(minus:SI (match_dup 1) (match_dup 2)))])
|
|
|
(define_insn "subsi3_ucc_pcmp"
|
(define_insn "subsi3_ucc_pcmp"
|
[(parallel
|
[(parallel
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_operand:SI 1 "score_register_operand" "d")
|
(compare:CC (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d")))
|
(match_operand:SI 2 "score_register_operand" "d")))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(minus:SI (match_dup 1) (match_dup 2)))])]
|
(minus:SI (match_dup 1) (match_dup 2)))])]
|
""
|
""
|
{
|
{
|
return score_select (operands, "sub", false, "", true);
|
return score_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "subsi3_ucc"
|
(define_insn "subsi3_ucc"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
|
(compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(minus:SI (match_dup 1) (match_dup 2)))]
|
(minus:SI (match_dup 1) (match_dup 2)))]
|
""
|
""
|
{
|
{
|
return score_select (operands, "sub", false, "", true);
|
return score_select (operands, "sub", false, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "subdi3"
|
(define_expand "subdi3"
|
[(parallel
|
[(parallel
|
[(set (match_operand:DI 0 "score_register_operand")
|
[(set (match_operand:DI 0 "score_register_operand")
|
(minus:DI (match_operand:DI 1 "score_register_operand")
|
(minus:DI (match_operand:DI 1 "score_register_operand")
|
(match_operand:DI 2 "score_register_operand")))
|
(match_operand:DI 2 "score_register_operand")))
|
(clobber (reg:CC CC_REGNUM))])]
|
(clobber (reg:CC CC_REGNUM))])]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*subdi3_score7"
|
(define_insn "*subdi3_score7"
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
[(set (match_operand:DI 0 "register_operand" "=e,d")
|
(minus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(minus:DI (match_operand:DI 1 "register_operand" "0,d")
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(match_operand:DI 2 "register_operand" "e,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
sub! %L0, %L2\;subc %H0, %H1, %H2
|
sub! %L0, %L2\;subc %H0, %H1, %H2
|
sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"
|
sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "*subdi3_score3"
|
(define_insn "*subdi3_score3"
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
(minus:DI (match_operand:DI 1 "score_register_operand" "d")
|
(minus:DI (match_operand:DI 1 "score_register_operand" "d")
|
(match_operand:DI 2 "score_register_operand" "d")))
|
(match_operand:DI 2 "score_register_operand" "d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"sub.c\t%L0, %L1, %L2\;subc\t%H0, %H1, %H2"
|
"sub.c\t%L0, %L1, %L2\;subc\t%H0, %H1, %H2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "8")
|
(set_attr "length" "8")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_expand "andsi3"
|
(define_expand "andsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(and:SI (match_operand:SI 1 "score_register_operand")
|
(and:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))]
|
(match_operand:SI 2 "arith_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*andsi3_score7"
|
(define_insn "*andsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis\t%0, %U2\";
|
case 0: return \"andis\t%0, %U2\";
|
case 1: return \"andi\t%0, %c2";
|
case 1: return \"andi\t%0, %c2";
|
case 2: return \"andri\t%0, %1, %c2\";
|
case 2: return \"andri\t%0, %1, %c2\";
|
case 3: return score_select (operands, "and", true, "", false);
|
case 3: return score_select (operands, "and", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*andsi3_score3"
|
(define_insn "*andsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")
|
(and:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")
|
(and:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]
|
(match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"and!\t%0, %2\";
|
case 0: return \"and!\t%0, %2\";
|
case 1: return \"andis\t%0, %U2\";
|
case 1: return \"andis\t%0, %U2\";
|
case 2: return \"andi\t%0, %c2";
|
case 2: return \"andi\t%0, %c2";
|
case 3: return \"andri\t%0, %1, %c2\";
|
case 3: return \"andri\t%0, %1, %c2\";
|
case 4: return score_select (operands, "and", true, "", false);
|
case 4: return score_select (operands, "and", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "2,4,4,4,4")
|
(set_attr "length" "2,4,4,4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "andsi3_cmp_score7"
|
(define_insn "andsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
|
(compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis.c\t%0, %U2\";
|
case 0: return \"andis.c\t%0, %U2\";
|
case 1: return \"andi.c\t%0, %c2";
|
case 1: return \"andi.c\t%0, %c2";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "and", true, "", true);
|
case 3: return score_select (operands, "and", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "andsi3_cmp_score3"
|
(define_insn "andsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (and:SI (match_operand:SI 1 "score_register_operand" "0,0,0,d")
|
(compare:CC_NZ (and:SI (match_operand:SI 1 "score_register_operand" "0,0,0,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
""
|
""
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis.c\t%0, %U2\";
|
case 0: return \"andis.c\t%0, %U2\";
|
case 1: return \"andi.c\t%0, %c2";
|
case 1: return \"andi.c\t%0, %c2";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "and", true, "", true);
|
case 3: return score_select (operands, "and", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*andsi3_ucc_score7"
|
(define_insn "*andsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (and:SI
|
(compare:CC_NZ (and:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(and:SI (match_dup 1) (match_dup 2)))]
|
(and:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis.c\t%0, %U2\";
|
case 0: return \"andis.c\t%0, %U2\";
|
case 1: return \"andi.c\t%0, %c2";
|
case 1: return \"andi.c\t%0, %c2";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "and", true, "", true);
|
case 3: return score_select (operands, "and", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*andsi3_ucc_score3"
|
(define_insn "*andsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (and:SI
|
(compare:CC_NZ (and:SI
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(and:SI (match_dup 1) (match_dup 2)))]
|
(and:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"andis.c\t%0, %U2\";
|
case 0: return \"andis.c\t%0, %U2\";
|
case 1: return \"andi.c\t%0, %c2";
|
case 1: return \"andi.c\t%0, %c2";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 2: return \"andri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "and", true, "", true);
|
case 3: return score_select (operands, "and", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
|
|
(define_insn_and_split "*zero_extract_andi"
|
(define_insn_and_split "*zero_extract_andi"
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (zero_extract:SI
|
(compare:CC (zero_extract:SI
|
(match_operand:SI 0 "score_register_operand" "d")
|
(match_operand:SI 0 "score_register_operand" "d")
|
(match_operand:SI 1 "const_uimm5" "")
|
(match_operand:SI 1 "const_uimm5" "")
|
(match_operand:SI 2 "const_uimm5" ""))
|
(match_operand:SI 2 "const_uimm5" ""))
|
(const_int 0)))]
|
(const_int 0)))]
|
""
|
""
|
"#"
|
"#"
|
""
|
""
|
[(const_int 1)]
|
[(const_int 1)]
|
{
|
{
|
score_zero_extract_andi (operands);
|
score_zero_extract_andi (operands);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "iorsi3"
|
(define_expand "iorsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(ior:SI (match_operand:SI 1 "score_register_operand")
|
(ior:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))]
|
(match_operand:SI 2 "arith_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*iorsi3_score7"
|
(define_insn "*iorsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
(match_operand:SI 2 "arith_operand" "I,K,M,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris\t%0, %U2\";
|
case 0: return \"oris\t%0, %U2\";
|
case 1: return \"ori\t%0, %c2\";
|
case 1: return \"ori\t%0, %c2\";
|
case 2: return \"orri\t%0, %1, %c2\";
|
case 2: return \"orri\t%0, %1, %c2\";
|
case 3: return score_select (operands, "or", true, "", false);
|
case 3: return score_select (operands, "or", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*iorsi3_score3"
|
(define_insn "*iorsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")
|
(ior:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")
|
(ior:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]
|
(match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"or!\t%0, %2\";
|
case 0: return \"or!\t%0, %2\";
|
case 1: return \"oris\t%0, %U2\";
|
case 1: return \"oris\t%0, %U2\";
|
case 2: return \"ori\t%0, %c2\";
|
case 2: return \"ori\t%0, %c2\";
|
case 3: return \"orri\t%0, %1, %c2\";
|
case 3: return \"orri\t%0, %1, %c2\";
|
case 4: return score_select (operands, "or", true, "", false);
|
case 4: return score_select (operands, "or", true, "", false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "2,4,4,4,4")
|
(set_attr "length" "2,4,4,4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*iorsi3_ucc_score7"
|
(define_insn "*iorsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ior:SI
|
(compare:CC_NZ (ior:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris.c\t%0, %U2\";
|
case 0: return \"oris.c\t%0, %U2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "or", true, "", true);
|
case 3: return score_select (operands, "or", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*iorsi3_ucc_score3"
|
(define_insn "*iorsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ior:SI
|
(compare:CC_NZ (ior:SI
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
(ior:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris.c\t%0, %U2\";
|
case 0: return \"oris.c\t%0, %U2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "or", true, "", true);
|
case 3: return score_select (operands, "or", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*iorsi3_cmp_score7"
|
(define_insn "*iorsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ior:SI
|
(compare:CC_NZ (ior:SI
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 1 "register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris.c\t%0, %U2\";
|
case 0: return \"oris.c\t%0, %U2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "or", true, "", true);
|
case 3: return score_select (operands, "or", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*iorsi3_cmp_score3"
|
(define_insn "*iorsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ior:SI
|
(compare:CC_NZ (ior:SI
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 1 "score_register_operand" "0,0,d,d")
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(match_operand:SI 2 "arith_operand" "I,K,M,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d,d,d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"oris.c\t%0, %U2\";
|
case 0: return \"oris.c\t%0, %U2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 1: return \"ori.c\t%0, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 2: return \"orri.c\t%0, %1, %c2\";
|
case 3: return score_select (operands, "or", true, "", true);
|
case 3: return score_select (operands, "or", true, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "length" "4,4,4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "xorsi3"
|
(define_expand "xorsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(xor:SI (match_operand:SI 1 "score_register_operand")
|
(xor:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "score_register_operand")))]
|
(match_operand:SI 2 "score_register_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*xorsi3_score7"
|
(define_insn "*xorsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(xor:SI (match_operand:SI 1 "register_operand" "d")
|
(xor:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))]
|
(match_operand:SI 2 "register_operand" "d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
return score_select (operands, "xor", true, "", false);
|
return score_select (operands, "xor", true, "", false);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*xorsi3_score3"
|
(define_insn "*xorsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
(xor:SI (match_operand:SI 1 "score_register_operand" "d")
|
(xor:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d")))]
|
(match_operand:SI 2 "score_register_operand" "d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
return score_select (operands, "xor", true, "", false);
|
return score_select (operands, "xor", true, "", false);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
|
|
(define_insn "*xorsi3_ucc_score7"
|
(define_insn "*xorsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
return score_select (operands, "xor", true, "", true);
|
return score_select (operands, "xor", true, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*xorsi3_ucc_score3"
|
(define_insn "*xorsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
(xor:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
return score_select (operands, "xor", true, "", true);
|
return score_select (operands, "xor", true, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
|
|
(define_insn "*xorsi3_cmp_score7"
|
(define_insn "*xorsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d"))
|
(match_operand:SI 2 "register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
{
|
{
|
return score_select (operands, "xor", true, "", true);
|
return score_select (operands, "xor", true, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*xorsi3_cmp_score3"
|
(define_insn "*xorsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")
|
(compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(match_operand:SI 2 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
""
|
""
|
{
|
{
|
return score_select (operands, "xor", true, "", true);
|
return score_select (operands, "xor", true, "", true);
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "extendqisi2"
|
(define_expand "extendqisi2"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*extendqisi2_score7"
|
(define_insn "*extendqisi2_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extsb\t%0, %1\";
|
case 0: return \"extsb\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_BYTE, true);
|
case 1: return score_linsn (operands, SCORE_BYTE, true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith,load")
|
[(set_attr "type" "arith,load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_score3"
|
(define_insn "*extendqisi2_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extsb\t%0, %1\";
|
case 0: return \"extsb\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_BYTE, true);
|
case 1: return score_linsn (operands, SCORE_BYTE, true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith,load")
|
[(set_attr "type" "arith,load")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_ucc_score7"
|
(define_insn "*extendqisi2_ucc_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
(sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extsb.c %0, %1"
|
"extsb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_ucc_score3"
|
(define_insn "*extendqisi2_ucc_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(sign_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]
|
(sign_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extsb.c\t%0, %1"
|
"extsb.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_cmp_score7"
|
(define_insn "*extendqisi2_cmp_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extsb.c %0, %1"
|
"extsb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendqisi2_cmp_score3"
|
(define_insn "*extendqisi2_cmp_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extsb.c\t%0, %1"
|
"extsb.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "extendhisi2"
|
(define_expand "extendhisi2"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*extendhisi2_score7"
|
(define_insn "*extendhisi2_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extsh\t%0, %1\";
|
case 0: return \"extsh\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_HWORD, true);
|
case 1: return score_linsn (operands, SCORE_HWORD, true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_score3"
|
(define_insn "*extendhisi2_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extsh\t%0, %1\";
|
case 0: return \"extsh\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_HWORD, true);
|
case 1: return score_linsn (operands, SCORE_HWORD, true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_ucc_score7"
|
(define_insn "*extendhisi2_ucc_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
(sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extsh.c %0, %1"
|
"extsh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_ucc_score3"
|
(define_insn "*extendhisi2_ucc_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(sign_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]
|
(sign_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extsh.c\t%0, %1"
|
"extsh.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_cmp_score7"
|
(define_insn "*extendhisi2_cmp_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extsh.c %0, %1"
|
"extsh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*extendhisi2_cmp_score3"
|
(define_insn "*extendhisi2_cmp_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (ashiftrt:SI
|
(compare:CC_N (ashiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extsh.c\t%0, %1"
|
"extsh.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "zero_extendqisi2"
|
(define_expand "zero_extendqisi2"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*zero_extendqisi2_score7"
|
(define_insn "*zero_extendqisi2_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extzb\t%0, %1\";
|
case 0: return \"extzb\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_BYTE, false);
|
case 1: return score_linsn (operands, SCORE_BYTE, false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_score3"
|
(define_insn "*zero_extendqisi2_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extzb\t%0, %1\";
|
case 0: return \"extzb\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_BYTE, false);
|
case 1: return score_linsn (operands, SCORE_BYTE, false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_ucc_score7"
|
(define_insn "*zero_extendqisi2_ucc_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
(zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extzb.c %0, %1"
|
"extzb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_ucc_score3"
|
(define_insn "*zero_extendqisi2_ucc_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(zero_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]
|
(zero_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extzb.c\t%0, %1"
|
"extzb.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_cmp_score7"
|
(define_insn "*zero_extendqisi2_cmp_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extzb.c %0, %1"
|
"extzb.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendqisi2_cmp_score3"
|
(define_insn "*zero_extendqisi2_cmp_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 24))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extzb.c\t%0, %1"
|
"extzb.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "zero_extendhisi2"
|
(define_expand "zero_extendhisi2"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*zero_extendhisi2_score7"
|
(define_insn "*zero_extendhisi2_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extzh\t%0, %1\";
|
case 0: return \"extzh\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_HWORD, false);
|
case 1: return score_linsn (operands, SCORE_HWORD, false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_score3"
|
(define_insn "*zero_extendhisi2_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"extzh\t%0, %1\";
|
case 0: return \"extzh\t%0, %1\";
|
case 1: return score_linsn (operands, SCORE_HWORD, false);
|
case 1: return score_linsn (operands, SCORE_HWORD, false);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith, load")
|
[(set_attr "type" "arith, load")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_ucc_score7"
|
(define_insn "*zero_extendhisi2_ucc_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(set (match_operand:SI 0 "register_operand" "=d")
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
(zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extzh.c %0, %1"
|
"extzh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_ucc_score3"
|
(define_insn "*zero_extendhisi2_ucc_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(zero_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]
|
(zero_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extzh.c\t%0, %1"
|
"extzh.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_cmp_score7"
|
(define_insn "*zero_extendhisi2_cmp_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"extzh.c %0, %1"
|
"extzh.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*zero_extendhisi2_cmp_score3"
|
(define_insn "*zero_extendhisi2_cmp_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (lshiftrt:SI
|
(compare:CC_N (lshiftrt:SI
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "d")
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 16))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"extzh.c\t%0, %1"
|
"extzh.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "mulsi3"
|
(define_expand "mulsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(mult:SI (match_operand:SI 1 "score_register_operand")
|
(mult:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "score_register_operand")))]
|
(match_operand:SI 2 "score_register_operand")))]
|
""
|
""
|
{
|
{
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
emit_insn (gen_mulsi3_score7 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_mulsi3_score7 (operands[0], operands[1], operands[2]));
|
else if (TARGET_SCORE3)
|
else if (TARGET_SCORE3)
|
emit_insn (gen_mulsi3_score3 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_mulsi3_score3 (operands[0], operands[1], operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "mulsi3_score7"
|
(define_insn "mulsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(mult:SI (match_operand:SI 1 "register_operand" "d")
|
(mult:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(clobber (reg:SI HI_REGNUM))]
|
(clobber (reg:SI HI_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"mul %1, %2"
|
"mul %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mulsi3_score3"
|
(define_insn "mulsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
(mult:SI (match_operand:SI 1 "score_register_operand" "d")
|
(mult:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d")))]
|
(match_operand:SI 2 "score_register_operand" "d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"mulr.l\t%0, %1, %2"
|
"mulr.l\t%0, %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "mulsidi3"
|
(define_expand "mulsidi3"
|
[(set (match_operand:DI 0 "score_register_operand")
|
[(set (match_operand:DI 0 "score_register_operand")
|
(mult:DI (sign_extend:DI
|
(mult:DI (sign_extend:DI
|
(match_operand:SI 1 "score_register_operand"))
|
(match_operand:SI 1 "score_register_operand"))
|
(sign_extend:DI
|
(sign_extend:DI
|
(match_operand:SI 2 "score_register_operand"))))]
|
(match_operand:SI 2 "score_register_operand"))))]
|
""
|
""
|
{
|
{
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
emit_insn (gen_mulsidi3_score7 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_mulsidi3_score7 (operands[0], operands[1], operands[2]));
|
else if (TARGET_SCORE3)
|
else if (TARGET_SCORE3)
|
emit_insn (gen_mulsidi3_score3 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_mulsidi3_score3 (operands[0], operands[1], operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "mulsidi3_score7"
|
(define_insn "mulsidi3_score7"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(mult:DI (sign_extend:DI
|
(mult:DI (sign_extend:DI
|
(match_operand:SI 1 "register_operand" "d"))
|
(match_operand:SI 1 "register_operand" "d"))
|
(sign_extend:DI
|
(sign_extend:DI
|
(match_operand:SI 2 "register_operand" "d"))))]
|
(match_operand:SI 2 "register_operand" "d"))))]
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"mul %1, %2"
|
"mul %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "mulsidi3_score3"
|
(define_insn "mulsidi3_score3"
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
(mult:DI (sign_extend:DI
|
(mult:DI (sign_extend:DI
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(sign_extend:DI
|
(sign_extend:DI
|
(match_operand:SI 2 "score_register_operand" "d"))))]
|
(match_operand:SI 2 "score_register_operand" "d"))))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"mulr\t%0, %1, %2"
|
"mulr\t%0, %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_expand "umulsidi3"
|
(define_expand "umulsidi3"
|
[(set (match_operand:DI 0 "score_register_operand")
|
[(set (match_operand:DI 0 "score_register_operand")
|
(mult:DI (zero_extend:DI
|
(mult:DI (zero_extend:DI
|
(match_operand:SI 1 "score_register_operand"))
|
(match_operand:SI 1 "score_register_operand"))
|
(zero_extend:DI
|
(zero_extend:DI
|
(match_operand:SI 2 "score_register_operand"))))]
|
(match_operand:SI 2 "score_register_operand"))))]
|
""
|
""
|
{
|
{
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
emit_insn (gen_umulsidi3_score7 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_umulsidi3_score7 (operands[0], operands[1], operands[2]));
|
else if (TARGET_SCORE3)
|
else if (TARGET_SCORE3)
|
emit_insn (gen_umulsidi3_score3 (operands[0], operands[1], operands[2]));
|
emit_insn (gen_umulsidi3_score3 (operands[0], operands[1], operands[2]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "umulsidi3_score7"
|
(define_insn "umulsidi3_score7"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(mult:DI (zero_extend:DI
|
(mult:DI (zero_extend:DI
|
(match_operand:SI 1 "register_operand" "d"))
|
(match_operand:SI 1 "register_operand" "d"))
|
(zero_extend:DI
|
(zero_extend:DI
|
(match_operand:SI 2 "register_operand" "d"))))]
|
(match_operand:SI 2 "register_operand" "d"))))]
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"mulu %1, %2"
|
"mulu %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_insn "umulsidi3_score3"
|
(define_insn "umulsidi3_score3"
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
[(set (match_operand:DI 0 "score_register_operand" "=d")
|
(mult:DI (zero_extend:DI
|
(mult:DI (zero_extend:DI
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(zero_extend:DI
|
(zero_extend:DI
|
(match_operand:SI 2 "score_register_operand" "d"))))]
|
(match_operand:SI 2 "score_register_operand" "d"))))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"mulur\t%0, %1, %2"
|
"mulur\t%0, %1, %2"
|
[(set_attr "type" "mul")
|
[(set_attr "type" "mul")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "DI")])
|
(set_attr "mode" "DI")])
|
|
|
(define_expand "divmodsi4"
|
(define_expand "divmodsi4"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(div:SI (match_operand:SI 1 "score_register_operand")
|
(div:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "score_register_operand")))
|
(match_operand:SI 2 "score_register_operand")))
|
(set (match_operand:SI 3 "score_register_operand")
|
(set (match_operand:SI 3 "score_register_operand")
|
(mod:SI (match_dup 1) (match_dup 2)))])]
|
(mod:SI (match_dup 1) (match_dup 2)))])]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*divmodsi4_score7"
|
(define_insn "*divmodsi4_score7"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(div:SI (match_operand:SI 1 "register_operand" "d")
|
(div:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"div %1, %2"
|
"div %1, %2"
|
[(set_attr "type" "div")
|
[(set_attr "type" "div")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*divmodsi4_score3"
|
(define_insn "*divmodsi4_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=l")
|
[(set (match_operand:SI 0 "score_register_operand" "=l")
|
(div:SI (match_operand:SI 1 "score_register_operand" "d")
|
(div:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d")))
|
(match_operand:SI 2 "score_register_operand" "d")))
|
(set (match_operand:SI 3 "score_register_operand" "=h")
|
(set (match_operand:SI 3 "score_register_operand" "=h")
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
(mod:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"div\t%1, %2"
|
"div\t%1, %2"
|
[(set_attr "type" "div")
|
[(set_attr "type" "div")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "udivmodsi4"
|
(define_expand "udivmodsi4"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(udiv:SI (match_operand:SI 1 "score_register_operand")
|
(udiv:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "score_register_operand")))
|
(match_operand:SI 2 "score_register_operand")))
|
(set (match_operand:SI 3 "score_register_operand")
|
(set (match_operand:SI 3 "score_register_operand")
|
(umod:SI (match_dup 1) (match_dup 2)))])]
|
(umod:SI (match_dup 1) (match_dup 2)))])]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*udivmodsi4_score7"
|
(define_insn "*udivmodsi4_score7"
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
[(set (match_operand:SI 0 "register_operand" "=l")
|
(udiv:SI (match_operand:SI 1 "register_operand" "d")
|
(udiv:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))
|
(match_operand:SI 2 "register_operand" "d")))
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(set (match_operand:SI 3 "register_operand" "=h")
|
(umod:SI (match_dup 1) (match_dup 2)))]
|
(umod:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"divu %1, %2"
|
"divu %1, %2"
|
[(set_attr "type" "div")
|
[(set_attr "type" "div")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*udivmodsi4_score3"
|
(define_insn "*udivmodsi4_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=l")
|
[(set (match_operand:SI 0 "score_register_operand" "=l")
|
(udiv:SI (match_operand:SI 1 "score_register_operand" "d")
|
(udiv:SI (match_operand:SI 1 "score_register_operand" "d")
|
(match_operand:SI 2 "score_register_operand" "d")))
|
(match_operand:SI 2 "score_register_operand" "d")))
|
(set (match_operand:SI 3 "score_register_operand" "=h")
|
(set (match_operand:SI 3 "score_register_operand" "=h")
|
(umod:SI (match_dup 1) (match_dup 2)))]
|
(umod:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"divu\t%1, %2"
|
"divu\t%1, %2"
|
[(set_attr "type" "div")
|
[(set_attr "type" "div")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "ashlsi3"
|
(define_expand "ashlsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(ashift:SI (match_operand:SI 1 "score_register_operand")
|
(ashift:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))]
|
(match_operand:SI 2 "arith_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*ashlsi3_score7"
|
(define_insn "*ashlsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d,d")
|
(ashift:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
slli %0, %1, %c2
|
slli %0, %1, %c2
|
sll %0, %1, %2"
|
sll %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashlsi3_score3"
|
(define_insn "*ashlsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "0,d,d")
|
(ashift:SI (match_operand:SI 1 "score_register_operand" "0,d,d")
|
(match_operand:SI 2 "arith_operand" "J,J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,J,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
slli!\t%0, %c2
|
slli!\t%0, %c2
|
slli\t%0, %1, %c2
|
slli\t%0, %1, %c2
|
sll\t%0, %1, %2"
|
sll\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "2,4,4")
|
(set_attr "length" "2,4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashlsi3_ucc_score7"
|
(define_insn "*ashlsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashift:SI
|
(compare:CC_NZ (ashift:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashift:SI (match_dup 1) (match_dup 2)))]
|
(ashift:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashlsi3_ucc_score3"
|
(define_insn "*ashlsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashift:SI
|
(compare:CC_NZ (ashift:SI
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(ashift:SI (match_dup 1) (match_dup 2)))]
|
(ashift:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashlsi3_cmp_score7"
|
(define_insn "*ashlsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashift:SI
|
(compare:CC_NZ (ashift:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashlsi3_cmp_score3"
|
(define_insn "*ashlsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashift:SI
|
(compare:CC_NZ (ashift:SI
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 0: return score_select (operands, "slli", false, "c", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
case 1: return score_select (operands, "sll", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
|
|
(define_expand "ashrsi3"
|
(define_expand "ashrsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(ashiftrt:SI (match_operand:SI 1 "score_register_operand")
|
(ashiftrt:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))]
|
(match_operand:SI 2 "arith_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*ashrsi3_score7"
|
(define_insn "*ashrsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
srai %0, %1, %c2
|
srai %0, %1, %c2
|
sra %0, %1, %2"
|
sra %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashrsi3_score3"
|
(define_insn "*ashrsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(ashiftrt:SI (match_operand:SI 1 "score_register_operand" "d,d")
|
(ashiftrt:SI (match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
srai\t%0, %1, %c2
|
srai\t%0, %1, %c2
|
sra\t%0, %1, %2"
|
sra\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashrsi3_ucc_score7"
|
(define_insn "*ashrsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashiftrt:SI
|
(compare:CC_NZ (ashiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 1: return score_select (operands, "sra", false, "", true);
|
case 1: return score_select (operands, "sra", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashrsi3_ucc_score3"
|
(define_insn "*ashrsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashiftrt:SI
|
(compare:CC_NZ (ashiftrt:SI
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 1: return score_select (operands, "sra", false, "", true);
|
case 1: return score_select (operands, "sra", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*ashrsi3_cmp_score7"
|
(define_insn "*ashrsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashiftrt:SI
|
(compare:CC_NZ (ashiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 1: return score_select (operands, "sra", false, "", true);
|
case 1: return score_select (operands, "sra", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "ashrsi3_cmp_score3"
|
(define_insn "ashrsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (ashiftrt:SI
|
(compare:CC_NZ (ashiftrt:SI
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 0: return \"srai.c\t%0, %1, %c2\";
|
case 1: return score_select (operands, "sra", false, "", true);
|
case 1: return score_select (operands, "sra", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "lshrsi3"
|
(define_expand "lshrsi3"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(lshiftrt:SI (match_operand:SI 1 "score_register_operand")
|
(lshiftrt:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))]
|
(match_operand:SI 2 "arith_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*lshrsi3_score7"
|
(define_insn "*lshrsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
srli %0, %1, %c2
|
srli %0, %1, %c2
|
srl %0, %1, %2"
|
srl %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*lshrsi3_score3"
|
(define_insn "*lshrsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=e,d,d")
|
(lshiftrt:SI (match_operand:SI 1 "score_register_operand" "0,d,d")
|
(lshiftrt:SI (match_operand:SI 1 "score_register_operand" "0,d,d")
|
(match_operand:SI 2 "arith_operand" "J,J,d")))]
|
(match_operand:SI 2 "arith_operand" "J,J,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
srli!\t%0, %c2
|
srli!\t%0, %c2
|
srli\t%0, %1, %c2
|
srli\t%0, %1, %c2
|
srl\t%0, %1, %2"
|
srl\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "2,4,4")
|
(set_attr "length" "2,4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*lshrsi3_ucc_score7"
|
(define_insn "*lshrsi3_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (lshiftrt:SI
|
(compare:CC_NZ (lshiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(set (match_operand:SI 0 "register_operand" "=d,d")
|
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
|
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*lshrsi3_ucc_score3"
|
(define_insn "*lshrsi3_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (lshiftrt:SI
|
(compare:CC_NZ (lshiftrt:SI
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
|
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*lshrsi3_cmp_score7"
|
(define_insn "*lshrsi3_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (lshiftrt:SI
|
(compare:CC_NZ (lshiftrt:SI
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*lshrsi3_cmp_score3"
|
(define_insn "*lshrsi3_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (lshiftrt:SI
|
(compare:CC_NZ (lshiftrt:SI
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(match_operand:SI 2 "arith_operand" "J,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
(clobber (match_scratch:SI 0 "=d,d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 0: return score_select (operands, "srli", false, "c", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
case 1: return score_select (operands, "srl", false, "", true);
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "negsi2"
|
(define_expand "negsi2"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(neg:SI (match_operand:SI 1 "score_register_operand")))]
|
(neg:SI (match_operand:SI 1 "score_register_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*negsi2_score7"
|
(define_insn "*negsi2_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(neg:SI (match_operand:SI 1 "register_operand" "d")))]
|
(neg:SI (match_operand:SI 1 "register_operand" "d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"neg %0, %1"
|
"neg %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*negsi2_score3"
|
(define_insn "*negsi2_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
(neg:SI (match_operand:SI 1 "score_register_operand" "d")))]
|
(neg:SI (match_operand:SI 1 "score_register_operand" "d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"neg\t%0, %1"
|
"neg\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*negsi2_cmp_score7"
|
(define_insn "*negsi2_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
neg! %0, %1
|
neg! %0, %1
|
neg.c %0, %1"
|
neg.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*negsi2_cmp_score3"
|
(define_insn "*negsi2_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"neg.c\t%0, %1"
|
"neg.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*negsi2_ucc_score7"
|
(define_insn "*negsi2_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(neg:SI (match_dup 1)))]
|
(neg:SI (match_dup 1)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
neg! %0, %1
|
neg! %0, %1
|
neg.c %0, %1"
|
neg.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*negsi2_ucc_score3"
|
(define_insn "*negsi2_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(neg:SI (match_dup 1)))]
|
(neg:SI (match_dup 1)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"neg.c\t%0, %1"
|
"neg.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
|
|
(define_expand "one_cmplsi2"
|
(define_expand "one_cmplsi2"
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(not:SI (match_operand:SI 1 "score_register_operand")))]
|
(not:SI (match_operand:SI 1 "score_register_operand")))]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*one_cmplsi2_score7"
|
(define_insn "*one_cmplsi2_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(not:SI (match_operand:SI 1 "register_operand" "d")))]
|
(not:SI (match_operand:SI 1 "register_operand" "d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"not\t%0, %1"
|
"not\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*one_cmplsi2_score3"
|
(define_insn "*one_cmplsi2_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d")
|
(not:SI (match_operand:SI 1 "score_register_operand" "d")))]
|
(not:SI (match_operand:SI 1 "score_register_operand" "d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"not\t%0, %1"
|
"not\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*one_cmplsi2_ucc_score7"
|
(define_insn "*one_cmplsi2_ucc_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(set (match_operand:SI 0 "register_operand" "=e,d")
|
(not:SI (match_dup 1)))]
|
(not:SI (match_dup 1)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
not! %0, %1
|
not! %0, %1
|
not.c %0, %1"
|
not.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*one_cmplsi2_ucc_score3"
|
(define_insn "*one_cmplsi2_ucc_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(set (match_operand:SI 0 "score_register_operand" "=d")
|
(not:SI (match_dup 1)))]
|
(not:SI (match_dup 1)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"not.c\t%0, %1"
|
"not.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*one_cmplsi2_cmp_score7"
|
(define_insn "*one_cmplsi2_cmp_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
not! %0, %1
|
not! %0, %1
|
not.c %0, %1"
|
not.c %0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*one_cmplsi2_cmp_score3"
|
(define_insn "*one_cmplsi2_cmp_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))
|
(const_int 0)))
|
(const_int 0)))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"not.c\t%0, %1"
|
"not.c\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "rotlsi3"
|
(define_expand "rotlsi3"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(rotate:SI (match_operand:SI 1 "score_register_operand")
|
(rotate:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))
|
(match_operand:SI 2 "arith_operand")))
|
(clobber (reg:CC CC_REGNUM))])]
|
(clobber (reg:CC CC_REGNUM))])]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*rotlsi3_score7"
|
(define_insn "*rotlsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
|
(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
roli.c %0, %1, %c2
|
roli.c %0, %1, %c2
|
rol.c %0, %1, %2"
|
rol.c %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*rotlsi3_score3"
|
(define_insn "*rotlsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(rotate:SI (match_operand:SI 1 "score_register_operand" "d,d")
|
(rotate:SI (match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
roli.c\t%0, %1, %c2
|
roli.c\t%0, %1, %c2
|
rol.c\t%0, %1, %2"
|
rol.c\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "rotrsi3"
|
(define_expand "rotrsi3"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "score_register_operand")
|
[(set (match_operand:SI 0 "score_register_operand")
|
(rotatert:SI (match_operand:SI 1 "score_register_operand")
|
(rotatert:SI (match_operand:SI 1 "score_register_operand")
|
(match_operand:SI 2 "arith_operand")))
|
(match_operand:SI 2 "arith_operand")))
|
(clobber (reg:CC CC_REGNUM))])]
|
(clobber (reg:CC CC_REGNUM))])]
|
""
|
""
|
""
|
""
|
)
|
)
|
|
|
(define_insn "*rotrsi3_score7"
|
(define_insn "*rotrsi3_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
[(set (match_operand:SI 0 "register_operand" "=d,d")
|
(rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
|
(rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
rori.c %0, %1, %c2
|
rori.c %0, %1, %c2
|
ror.c %0, %1, %2"
|
ror.c %0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*rotrsi3_score3"
|
(define_insn "*rotrsi3_score3"
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
[(set (match_operand:SI 0 "score_register_operand" "=d,d")
|
(rotatert:SI (match_operand:SI 1 "score_register_operand" "d,d")
|
(rotatert:SI (match_operand:SI 1 "score_register_operand" "d,d")
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(match_operand:SI 2 "arith_operand" "J,d")))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
rori.c\t%0, %1, %c2
|
rori.c\t%0, %1, %c2
|
ror.c\t%0, %1, %2"
|
ror.c\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4,4")
|
(set_attr "length" "4,4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "cbranchsi4"
|
(define_expand "cbranchsi4"
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_operand:SI 1 "score_register_operand" "")
|
(compare:CC (match_operand:SI 1 "score_register_operand" "")
|
(match_operand:SI 2 "arith_operand" "")))
|
(match_operand:SI 2 "arith_operand" "")))
|
(set (pc)
|
(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "ordered_comparison_operator"
|
(match_operator 0 "ordered_comparison_operator"
|
[(reg:CC CC_REGNUM)
|
[(reg:CC CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 3 "" ""))
|
(label_ref (match_operand 3 "" ""))
|
(pc)))]
|
(pc)))]
|
""
|
""
|
"")
|
"")
|
|
|
(define_insn "cbrancheqz"
|
(define_insn "cbrancheqz"
|
[(set (pc) (if_then_else
|
[(set (pc) (if_then_else
|
(eq (match_operand:SI 0 "score_register_operand" "d")
|
(eq (match_operand:SI 0 "score_register_operand" "d")
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (get_attr_length (insn) == 4)
|
if (get_attr_length (insn) == 4)
|
return \"bcmpeqz\t%0, %1\";
|
return \"bcmpeqz\t%0, %1\";
|
else
|
else
|
return \"cmpi!\t%0, 0\;beq!\t%1\";
|
return \"cmpi!\t%0, 0\;beq!\t%1\";
|
}
|
}
|
[(set (attr "length")
|
[(set (attr "length")
|
(if_then_else
|
(if_then_else
|
(and (ge (minus (match_dup 1) (pc)) (const_int -504))
|
(and (ge (minus (match_dup 1) (pc)) (const_int -504))
|
(le (minus (match_dup 1) (pc)) (const_int 502)))
|
(le (minus (match_dup 1) (pc)) (const_int 502)))
|
(const_int 4)
|
(const_int 4)
|
(const_int 6)))])
|
(const_int 6)))])
|
|
|
(define_insn "cbrancheq"
|
(define_insn "cbrancheq"
|
[(set (pc) (if_then_else
|
[(set (pc) (if_then_else
|
(eq (match_operand:SI 0 "score_register_operand" "d")
|
(eq (match_operand:SI 0 "score_register_operand" "d")
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(label_ref (match_operand 2 "" ""))
|
(label_ref (match_operand 2 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (get_attr_length (insn) == 4)
|
if (get_attr_length (insn) == 4)
|
return \"bcmpeq\t%0, %1, %2\";
|
return \"bcmpeq\t%0, %1, %2\";
|
else
|
else
|
return \"cmp!\t%0, %1\;beq!\t%2\";
|
return \"cmp!\t%0, %1\;beq!\t%2\";
|
}
|
}
|
[(set (attr "length")
|
[(set (attr "length")
|
(if_then_else
|
(if_then_else
|
(and (ge (minus (match_dup 2) (pc)) (const_int -504))
|
(and (ge (minus (match_dup 2) (pc)) (const_int -504))
|
(le (minus (match_dup 2) (pc)) (const_int 502)))
|
(le (minus (match_dup 2) (pc)) (const_int 502)))
|
(const_int 4)
|
(const_int 4)
|
(const_int 6)))])
|
(const_int 6)))])
|
|
|
(define_insn "cbranchnez"
|
(define_insn "cbranchnez"
|
[(set (pc) (if_then_else
|
[(set (pc) (if_then_else
|
(ne (match_operand:SI 0 "score_register_operand" "d")
|
(ne (match_operand:SI 0 "score_register_operand" "d")
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (get_attr_length (insn) == 4)
|
if (get_attr_length (insn) == 4)
|
return \"bcmpnez\t%0, %1\";
|
return \"bcmpnez\t%0, %1\";
|
else
|
else
|
return \"cmpi!\t%0, 0\;bne\t%1\";
|
return \"cmpi!\t%0, 0\;bne\t%1\";
|
}
|
}
|
[(set (attr "length")
|
[(set (attr "length")
|
(if_then_else
|
(if_then_else
|
(and (ge (minus (match_dup 1) (pc)) (const_int -504))
|
(and (ge (minus (match_dup 1) (pc)) (const_int -504))
|
(le (minus (match_dup 1) (pc)) (const_int 502)))
|
(le (minus (match_dup 1) (pc)) (const_int 502)))
|
(const_int 4)
|
(const_int 4)
|
(const_int 6)))])
|
(const_int 6)))])
|
|
|
(define_insn "cbranchne"
|
(define_insn "cbranchne"
|
[(set (pc) (if_then_else
|
[(set (pc) (if_then_else
|
(ne (match_operand:SI 0 "score_register_operand" "d")
|
(ne (match_operand:SI 0 "score_register_operand" "d")
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(match_operand:SI 1 "score_register_operand" "d"))
|
(label_ref (match_operand 2 "" ""))
|
(label_ref (match_operand 2 "" ""))
|
(pc)))
|
(pc)))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (get_attr_length (insn) == 4)
|
if (get_attr_length (insn) == 4)
|
return \"bcmpne\t%0, %1, %2\";
|
return \"bcmpne\t%0, %1, %2\";
|
else
|
else
|
return \"cmp!\t%0, %1\;bne\t%2\";
|
return \"cmp!\t%0, %1\;bne\t%2\";
|
}
|
}
|
[(set (attr "length")
|
[(set (attr "length")
|
(if_then_else
|
(if_then_else
|
(and (ge (minus (match_dup 2) (pc)) (const_int -504))
|
(and (ge (minus (match_dup 2) (pc)) (const_int -504))
|
(le (minus (match_dup 2) (pc)) (const_int 502)))
|
(le (minus (match_dup 2) (pc)) (const_int 502)))
|
(const_int 4)
|
(const_int 4)
|
(const_int 6)))])
|
(const_int 6)))])
|
|
|
(define_insn "cmpsi_nz_score7"
|
(define_insn "cmpsi_nz_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
|
(compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
cmpi.c %0, %c1
|
cmpi.c %0, %c1
|
cmp! %0, %1
|
cmp! %0, %1
|
cmp.c %0, %1"
|
cmp.c %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_nz_score3"
|
(define_insn "cmpsi_nz_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (match_operand:SI 0 "score_register_operand" "d,d,d")
|
(compare:CC_NZ (match_operand:SI 0 "score_register_operand" "d,d,d")
|
(match_operand:SI 1 "arith_operand" "O,L,d")))]
|
(match_operand:SI 1 "arith_operand" "O,L,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
cmpi!\t%0, %c1
|
cmpi!\t%0, %c1
|
cmpi.c\t%0, %c1
|
cmpi.c\t%0, %c1
|
cmp!\t %0, %1"
|
cmp!\t %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "length" "2,4,2")
|
(set_attr "length" "2,4,2")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_n_score7"
|
(define_insn "cmpsi_n_score7"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
|
(compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
cmpi.c %0, %c1
|
cmpi.c %0, %c1
|
cmp! %0, %1
|
cmp! %0, %1
|
cmp.c %0, %1"
|
cmp.c %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_n_score3"
|
(define_insn "cmpsi_n_score3"
|
[(set (reg:CC_N CC_REGNUM)
|
[(set (reg:CC_N CC_REGNUM)
|
(compare:CC_N (match_operand:SI 0 "score_register_operand" "d,d,d")
|
(compare:CC_N (match_operand:SI 0 "score_register_operand" "d,d,d")
|
(match_operand:SI 1 "arith_operand" "O,L,d")))]
|
(match_operand:SI 1 "arith_operand" "O,L,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
cmpi!\t%0, %c1
|
cmpi!\t%0, %c1
|
cmpi.c\t%0, %c1
|
cmpi.c\t%0, %c1
|
cmp!\t%0, %1"
|
cmp!\t%0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "length" "2,4,2")
|
(set_attr "length" "2,4,2")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*cmpsi_to_addsi_score7"
|
(define_insn "*cmpsi_to_addsi_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
|
(compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
|
(neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
|
(neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
(clobber (match_scratch:SI 0 "=e,d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
add! %0, %2
|
add! %0, %2
|
add.c %0, %1, %2"
|
add.c %0, %1, %2"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*cmpsi_to_addsi_score3"
|
(define_insn "*cmpsi_to_addsi_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (match_operand:SI 1 "score_register_operand" "d")
|
(compare:CC_NZ (match_operand:SI 1 "score_register_operand" "d")
|
(neg:SI (match_operand:SI 2 "score_register_operand" "d"))))
|
(neg:SI (match_operand:SI 2 "score_register_operand" "d"))))
|
(clobber (match_scratch:SI 0 "=d"))]
|
(clobber (match_scratch:SI 0 "=d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"add.c\t%0, %1, %2"
|
"add.c\t%0, %1, %2"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_cc_score7"
|
(define_insn "cmpsi_cc_score7"
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
|
(compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
(match_operand:SI 1 "arith_operand" "L,e,d")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
cmpi.c %0, %c1
|
cmpi.c %0, %c1
|
cmp! %0, %1
|
cmp! %0, %1
|
cmp.c %0, %1"
|
cmp.c %0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "cmpsi_cc_score3"
|
(define_insn "cmpsi_cc_score3"
|
[(set (reg:CC CC_REGNUM)
|
[(set (reg:CC CC_REGNUM)
|
(compare:CC (match_operand:SI 0 "score_register_operand" "d,d,d")
|
(compare:CC (match_operand:SI 0 "score_register_operand" "d,d,d")
|
(match_operand:SI 1 "arith_operand" "O,L,d")))]
|
(match_operand:SI 1 "arith_operand" "O,L,d")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
cmpi!\t%0, %c1
|
cmpi!\t%0, %c1
|
cmpi.c\t%0, %c1
|
cmpi.c\t%0, %c1
|
cmp!\t%0, %1"
|
cmp!\t%0, %1"
|
[(set_attr "type" "cmp")
|
[(set_attr "type" "cmp")
|
(set_attr "length" "2,4,2")
|
(set_attr "length" "2,4,2")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "*branch_n_score7"
|
(define_insn "*branch_n_score7"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "branch_n_operator"
|
(match_operator 0 "branch_n_operator"
|
[(reg:CC_N CC_REGNUM)
|
[(reg:CC_N CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"b%C0 %1"
|
"b%C0 %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|
(define_insn "*branch_n_score3"
|
(define_insn "*branch_n_score3"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "branch_n_operator"
|
(match_operator 0 "branch_n_operator"
|
[(reg:CC_N CC_REGNUM)
|
[(reg:CC_N CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"b%C0\t%1"
|
"b%C0\t%1"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "*branch_nz_score7"
|
(define_insn "*branch_nz_score7"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "branch_nz_operator"
|
(match_operator 0 "branch_nz_operator"
|
[(reg:CC_NZ CC_REGNUM)
|
[(reg:CC_NZ CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"b%C0 %1"
|
"b%C0 %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|
(define_insn "*branch_nz_score3"
|
(define_insn "*branch_nz_score3"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "branch_nz_operator"
|
(match_operator 0 "branch_nz_operator"
|
[(reg:CC_NZ CC_REGNUM)
|
[(reg:CC_NZ CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"b%C0\t%1"
|
"b%C0\t%1"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
|
|
(define_insn "*branch_cc_score7"
|
(define_insn "*branch_cc_score7"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "comparison_operator"
|
(match_operator 0 "comparison_operator"
|
[(reg:CC CC_REGNUM)
|
[(reg:CC CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"b%C0 %1"
|
"b%C0 %1"
|
[(set_attr "type" "branch")])
|
[(set_attr "type" "branch")])
|
|
|
(define_insn "*branch_cc_score3"
|
(define_insn "*branch_cc_score3"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(match_operator 0 "comparison_operator"
|
(match_operator 0 "comparison_operator"
|
[(reg:CC CC_REGNUM)
|
[(reg:CC CC_REGNUM)
|
(const_int 0)])
|
(const_int 0)])
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))]
|
(pc)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"b%C0\t%1"
|
"b%C0\t%1"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "jump"
|
(define_insn "jump"
|
[(set (pc)
|
[(set (pc)
|
(label_ref (match_operand 0 "" "")))]
|
(label_ref (match_operand 0 "" "")))]
|
""
|
""
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
return \"j\t%0\";
|
return \"j\t%0\";
|
else
|
else
|
return \"b\t%0\";
|
return \"b\t%0\";
|
}
|
}
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_expand "sibcall"
|
(define_expand "sibcall"
|
[(parallel [(call (match_operand 0 "" "")
|
[(parallel [(call (match_operand 0 "" "")
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(use (match_operand 2 "" ""))])]
|
(use (match_operand 2 "" ""))])]
|
""
|
""
|
{
|
{
|
score_call (operands, true);
|
score_call (operands, true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "sibcall_internal_score7"
|
(define_insn "sibcall_internal_score7"
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(clobber (reg:SI RT_REGNUM))]
|
(clobber (reg:SI RT_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& SIBLING_CALL_P (insn)"
|
&& SIBLING_CALL_P (insn)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"br%S0\t%0\";
|
case 0: return \"br%S0\t%0\";
|
case 1: return \"j\t%0\";
|
case 1: return \"j\t%0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv\tr29, %0\;br\tr29\";
|
case 0: return \"mv\tr29, %0\;br\tr29\";
|
case 1: return \"la\tr29, %0\;br\tr29\";
|
case 1: return \"la\tr29, %0\;br\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_insn "sibcall_internal_score3"
|
(define_insn "sibcall_internal_score3"
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(clobber (reg:SI RT_REGNUM))]
|
(clobber (reg:SI RT_REGNUM))]
|
"(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"
|
"(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"br%S0\t%0\";
|
case 0: return \"br%S0\t%0\";
|
case 1: return \"j\t%0\";
|
case 1: return \"j\t%0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv!\tr29, %0\;br!\tr29\";
|
case 0: return \"mv!\tr29, %0\;br!\tr29\";
|
case 1: return \"ldi48\tr29, %0\;br!\tr29\";
|
case 1: return \"ldi48\tr29, %0\;br!\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")
|
[(set_attr "type" "call")
|
(set_attr "length" "4,8")])
|
(set_attr "length" "4,8")])
|
|
|
(define_expand "sibcall_value"
|
(define_expand "sibcall_value"
|
[(parallel [(set (match_operand 0 "" "")
|
[(parallel [(set (match_operand 0 "" "")
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(use (match_operand 3 "" ""))])]
|
(use (match_operand 3 "" ""))])]
|
""
|
""
|
{
|
{
|
score_call_value (operands, true);
|
score_call_value (operands, true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "sibcall_value_internal_score7"
|
(define_insn "sibcall_value_internal_score7"
|
[(set (match_operand 0 "register_operand" "=d,d")
|
[(set (match_operand 0 "register_operand" "=d,d")
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(clobber (reg:SI RT_REGNUM))]
|
(clobber (reg:SI RT_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& SIBLING_CALL_P (insn)"
|
&& SIBLING_CALL_P (insn)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"br%S1\t%1\";
|
case 0: return \"br%S1\t%1\";
|
case 1: return \"j\t%1\";
|
case 1: return \"j\t%1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv\tr29, %1\;br\tr29\";
|
case 0: return \"mv\tr29, %1\;br\tr29\";
|
case 1: return \"la\tr29, %1\;br\tr29\";
|
case 1: return \"la\tr29, %1\;br\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_insn "sibcall_value_internal_score3"
|
(define_insn "sibcall_value_internal_score3"
|
[(set (match_operand 0 "score_register_operand" "=d,d")
|
[(set (match_operand 0 "score_register_operand" "=d,d")
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(clobber (reg:SI RT_REGNUM))]
|
(clobber (reg:SI RT_REGNUM))]
|
"(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"
|
"(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"br%S1\t%1\";
|
case 0: return \"br%S1\t%1\";
|
case 1: return \"j\t%1\";
|
case 1: return \"j\t%1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv!\tr29, %1\;br!\tr29\";
|
case 0: return \"mv!\tr29, %1\;br!\tr29\";
|
case 1: return \"ldi48\tr29, %1\;br!\tr29\";
|
case 1: return \"ldi48\tr29, %1\;br!\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "length" "4,8")
|
[(set_attr "length" "4,8")
|
(set_attr "type" "call")])
|
(set_attr "type" "call")])
|
|
|
(define_expand "call"
|
(define_expand "call"
|
[(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
|
[(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
|
(use (match_operand 2 "" ""))])]
|
(use (match_operand 2 "" ""))])]
|
""
|
""
|
{
|
{
|
score_call (operands, false);
|
score_call (operands, false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "call_internal_score7"
|
(define_insn "call_internal_score7"
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(clobber (reg:SI RA_REGNUM))]
|
(clobber (reg:SI RA_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"brl%S0\t%0\";
|
case 0: return \"brl%S0\t%0\";
|
case 1: return \"jl\t%0\";
|
case 1: return \"jl\t%0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv\tr29, %0\;brl\tr29\";
|
case 0: return \"mv\tr29, %0\;brl\tr29\";
|
case 1: return \"la\tr29, %0\;brl\tr29\";
|
case 1: return \"la\tr29, %0\;brl\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_insn "call_internal_score3"
|
(define_insn "call_internal_score3"
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
|
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
|
(match_operand 1 "" ""))
|
(match_operand 1 "" ""))
|
(clobber (reg:SI RA_REGNUM))]
|
(clobber (reg:SI RA_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"brl!\t%0\";
|
case 0: return \"brl!\t%0\";
|
case 1: return \"jl\t%0\";
|
case 1: return \"jl\t%0\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv!\tr29, %0\;brl!\tr29\";
|
case 0: return \"mv!\tr29, %0\;brl!\tr29\";
|
case 1: return \"ldi48\tr29, %0\;brl!\tr29\";
|
case 1: return \"ldi48\tr29, %0\;brl!\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "length" "4,8")
|
[(set_attr "length" "4,8")
|
(set_attr "type" "call")])
|
(set_attr "type" "call")])
|
|
|
(define_expand "call_value"
|
(define_expand "call_value"
|
[(parallel [(set (match_operand 0 "" "")
|
[(parallel [(set (match_operand 0 "" "")
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(call (match_operand 1 "" "") (match_operand 2 "" "")))
|
(use (match_operand 3 "" ""))])]
|
(use (match_operand 3 "" ""))])]
|
""
|
""
|
{
|
{
|
score_call_value (operands, false);
|
score_call_value (operands, false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "call_value_internal_score7"
|
(define_insn "call_value_internal_score7"
|
[(set (match_operand 0 "register_operand" "=d,d")
|
[(set (match_operand 0 "register_operand" "=d,d")
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(clobber (reg:SI RA_REGNUM))]
|
(clobber (reg:SI RA_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"brl%S1\t%1\";
|
case 0: return \"brl%S1\t%1\";
|
case 1: return \"jl\t%1\";
|
case 1: return \"jl\t%1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv\tr29, %1\;brl\tr29\";
|
case 0: return \"mv\tr29, %1\;brl\tr29\";
|
case 1: return \"la\tr29, %1\;brl\tr29\";
|
case 1: return \"la\tr29, %1\;brl\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "type" "call")])
|
[(set_attr "type" "call")])
|
|
|
(define_insn "call_value_internal_score3"
|
(define_insn "call_value_internal_score3"
|
[(set (match_operand 0 "score_register_operand" "=d,d")
|
[(set (match_operand 0 "score_register_operand" "=d,d")
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
|
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
|
(match_operand 2 "" "")))
|
(match_operand 2 "" "")))
|
(clobber (reg:SI RA_REGNUM))]
|
(clobber (reg:SI RA_REGNUM))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (!flag_pic)
|
if (!flag_pic)
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"brl!\t%1\";
|
case 0: return \"brl!\t%1\";
|
case 1: return \"jl\t%1\";
|
case 1: return \"jl\t%1\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
else
|
else
|
switch (which_alternative)
|
switch (which_alternative)
|
{
|
{
|
case 0: return \"mv!\tr29, %1\;brl!\tr29\";
|
case 0: return \"mv!\tr29, %1\;brl!\tr29\";
|
case 1: return \"ldi48\tr29, %1\;brl!\tr29\";
|
case 1: return \"ldi48\tr29, %1\;brl!\tr29\";
|
default: gcc_unreachable ();
|
default: gcc_unreachable ();
|
}
|
}
|
}
|
}
|
[(set_attr "length" "4,8")
|
[(set_attr "length" "4,8")
|
(set_attr "type" "call")])
|
(set_attr "type" "call")])
|
|
|
(define_expand "indirect_jump"
|
(define_expand "indirect_jump"
|
[(set (pc) (match_operand 0 "score_register_operand" "d"))]
|
[(set (pc) (match_operand 0 "score_register_operand" "d"))]
|
""
|
""
|
{
|
{
|
rtx dest;
|
rtx dest;
|
dest = operands[0];
|
dest = operands[0];
|
if (GET_CODE (dest) != REG
|
if (GET_CODE (dest) != REG
|
|| GET_MODE (dest) != Pmode)
|
|| GET_MODE (dest) != Pmode)
|
operands[0] = copy_to_mode_reg (Pmode, dest);
|
operands[0] = copy_to_mode_reg (Pmode, dest);
|
|
|
emit_jump_insn (gen_indirect_jump_internal_score (operands[0]));
|
emit_jump_insn (gen_indirect_jump_internal_score (operands[0]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "indirect_jump_internal_score"
|
(define_insn "indirect_jump_internal_score"
|
[(set (pc) (match_operand:SI 0 "score_register_operand" "d"))]
|
[(set (pc) (match_operand:SI 0 "score_register_operand" "d"))]
|
""
|
""
|
"br%S0 %0"
|
"br%S0 %0"
|
[(set_attr "type" "jump")])
|
[(set_attr "type" "jump")])
|
|
|
(define_expand "casesi"
|
(define_expand "casesi"
|
[(match_operand:SI 0 "score_register_operand" "") ; index to jump on
|
[(match_operand:SI 0 "score_register_operand" "") ; index to jump on
|
(match_operand:SI 1 "const_int_operand" "") ; lower bound
|
(match_operand:SI 1 "const_int_operand" "") ; lower bound
|
(match_operand:SI 2 "const_int_operand" "") ; total range
|
(match_operand:SI 2 "const_int_operand" "") ; total range
|
(match_operand:SI 3 "" "") ; table label
|
(match_operand:SI 3 "" "") ; table label
|
(match_operand:SI 4 "" "")] ; Out of range label
|
(match_operand:SI 4 "" "")] ; Out of range label
|
"TARGET_SCORE3"
|
"TARGET_SCORE3"
|
{
|
{
|
rtx reg;
|
rtx reg;
|
if (operands[1] != const0_rtx)
|
if (operands[1] != const0_rtx)
|
{
|
{
|
reg = gen_reg_rtx (SImode);
|
reg = gen_reg_rtx (SImode);
|
emit_insn (gen_addsi3 (reg, operands[0],
|
emit_insn (gen_addsi3 (reg, operands[0],
|
GEN_INT (-INTVAL (operands[1]))));
|
GEN_INT (-INTVAL (operands[1]))));
|
operands[0] = reg;
|
operands[0] = reg;
|
}
|
}
|
|
|
if (!CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'L'))
|
if (!CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'L'))
|
operands[2] = force_reg (SImode, operands[2]);
|
operands[2] = force_reg (SImode, operands[2]);
|
|
|
reg = gen_reg_rtx (SImode);
|
reg = gen_reg_rtx (SImode);
|
emit_jump_insn (gen_score3_casesi_internal (operands[0], operands[2],
|
emit_jump_insn (gen_score3_casesi_internal (operands[0], operands[2],
|
operands[3], operands[4], reg));
|
operands[3], operands[4], reg));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "score3_casesi_internal"
|
(define_insn "score3_casesi_internal"
|
[(parallel [(set (pc)
|
[(parallel [(set (pc)
|
(if_then_else
|
(if_then_else
|
(leu (match_operand:SI 0 "score_register_operand" "e")
|
(leu (match_operand:SI 0 "score_register_operand" "e")
|
(match_operand:SI 1 "arith_operand" "dL"))
|
(match_operand:SI 1 "arith_operand" "dL"))
|
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
|
(mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
|
(label_ref (match_operand 2 "" ""))))
|
(label_ref (match_operand 2 "" ""))))
|
(label_ref (match_operand 3 "" ""))))
|
(label_ref (match_operand 3 "" ""))))
|
(clobber (reg:CC CC_REGNUM))
|
(clobber (reg:CC CC_REGNUM))
|
(clobber (match_operand:SI 4 "score_register_operand" "=e"))
|
(clobber (match_operand:SI 4 "score_register_operand" "=e"))
|
(use (label_ref (match_dup 2)))])]
|
(use (label_ref (match_dup 2)))])]
|
"TARGET_SCORE3 && !flag_pic"
|
"TARGET_SCORE3 && !flag_pic"
|
"*
|
"*
|
return score_output_casesi(operands);
|
return score_output_casesi(operands);
|
"
|
"
|
[(set_attr "length" "20")])
|
[(set_attr "length" "20")])
|
|
|
(define_expand "tablejump"
|
(define_expand "tablejump"
|
[(set (pc)
|
[(set (pc)
|
(match_operand 0 "score_register_operand" "d"))
|
(match_operand 0 "score_register_operand" "d"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
""
|
""
|
{
|
{
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
emit_jump_insn (gen_tablejump_internal_score7 (operands[0], operands[1]));
|
emit_jump_insn (gen_tablejump_internal_score7 (operands[0], operands[1]));
|
else if (TARGET_SCORE3)
|
else if (TARGET_SCORE3)
|
emit_jump_insn (gen_tablejump_internal_score3 (operands[0], operands[1]));
|
emit_jump_insn (gen_tablejump_internal_score3 (operands[0], operands[1]));
|
|
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "tablejump_internal_score7"
|
(define_insn "tablejump_internal_score7"
|
[(set (pc)
|
[(set (pc)
|
(match_operand:SI 0 "register_operand" "d"))
|
(match_operand:SI 0 "register_operand" "d"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
{
|
{
|
if (flag_pic)
|
if (flag_pic)
|
return \"mv\tr29, %0\;.cpadd\tr29\;br\tr29\";
|
return \"mv\tr29, %0\;.cpadd\tr29\;br\tr29\";
|
else
|
else
|
return \"br%S0\t%0\";
|
return \"br%S0\t%0\";
|
}
|
}
|
[(set_attr "type" "jump")])
|
[(set_attr "type" "jump")])
|
|
|
(define_insn "tablejump_internal_score3"
|
(define_insn "tablejump_internal_score3"
|
[(set (pc)
|
[(set (pc)
|
(match_operand:SI 0 "score_register_operand" "d"))
|
(match_operand:SI 0 "score_register_operand" "d"))
|
(use (label_ref (match_operand 1 "" "")))]
|
(use (label_ref (match_operand 1 "" "")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
if (flag_pic)
|
if (flag_pic)
|
return \"mv!\tr29, %0\;.cpadd\tr29\;br!\tr29\";
|
return \"mv!\tr29, %0\;.cpadd\tr29\;br!\tr29\";
|
else
|
else
|
return \"br%S0\t%0\";
|
return \"br%S0\t%0\";
|
}
|
}
|
[(set_attr "type" "jump")
|
[(set_attr "type" "jump")
|
(set_attr "length" "8")])
|
(set_attr "length" "8")])
|
|
|
(define_expand "prologue"
|
(define_expand "prologue"
|
[(const_int 1)]
|
[(const_int 1)]
|
""
|
""
|
{
|
{
|
score_prologue ();
|
score_prologue ();
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "epilogue"
|
(define_expand "epilogue"
|
[(const_int 2)]
|
[(const_int 2)]
|
""
|
""
|
{
|
{
|
score_epilogue (false);
|
score_epilogue (false);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_expand "sibcall_epilogue"
|
(define_expand "sibcall_epilogue"
|
[(const_int 2)]
|
[(const_int 2)]
|
""
|
""
|
{
|
{
|
score_epilogue (true);
|
score_epilogue (true);
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "return_internal_score7"
|
(define_insn "return_internal_score7"
|
[(return)
|
[(return)
|
(use (match_operand 0 "pmode_register_operand" "d"))]
|
(use (match_operand 0 "pmode_register_operand" "d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"br%S0\t%0")
|
"br%S0\t%0")
|
|
|
(define_insn "return_internal_score3"
|
(define_insn "return_internal_score3"
|
[(return)
|
[(return)
|
(use (match_operand 0 "pmode_register_operand" "d"))]
|
(use (match_operand 0 "pmode_register_operand" "d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"br%S0\t%0"
|
"br%S0\t%0"
|
[(set_attr "length" "4")])
|
[(set_attr "length" "4")])
|
|
|
(define_insn "nop"
|
(define_insn "nop"
|
[(const_int 0)]
|
[(const_int 0)]
|
""
|
""
|
"#nop!"
|
"#nop!"
|
)
|
)
|
|
|
(define_insn "cpload_score7"
|
(define_insn "cpload_score7"
|
[(unspec_volatile:SI [(const_int 1)] CPLOAD)]
|
[(unspec_volatile:SI [(const_int 1)] CPLOAD)]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& flag_pic"
|
&& flag_pic"
|
".cpload\tr29"
|
".cpload\tr29"
|
)
|
)
|
|
|
(define_insn "cpload_score3"
|
(define_insn "cpload_score3"
|
[(unspec_volatile:SI [(const_int 1)] CPLOAD)]
|
[(unspec_volatile:SI [(const_int 1)] CPLOAD)]
|
"(TARGET_SCORE3) && flag_pic"
|
"(TARGET_SCORE3) && flag_pic"
|
".cpload\tr29"
|
".cpload\tr29"
|
[(set_attr "length" "4")])
|
[(set_attr "length" "4")])
|
|
|
(define_insn "cprestore_use_fp_score7"
|
(define_insn "cprestore_use_fp_score7"
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
(use (reg:SI FP_REGNUM))]
|
(use (reg:SI FP_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& flag_pic"
|
&& flag_pic"
|
".cprestore\tr2, %0"
|
".cprestore\tr2, %0"
|
)
|
)
|
|
|
(define_insn "cprestore_use_fp_score3"
|
(define_insn "cprestore_use_fp_score3"
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
(use (reg:SI FP_REGNUM))]
|
(use (reg:SI FP_REGNUM))]
|
"(TARGET_SCORE3) && flag_pic"
|
"(TARGET_SCORE3) && flag_pic"
|
".cprestore\tr2, %0"
|
".cprestore\tr2, %0"
|
[(set_attr "length" "4")])
|
[(set_attr "length" "4")])
|
|
|
(define_insn "cprestore_use_sp_score7"
|
(define_insn "cprestore_use_sp_score7"
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
(use (reg:SI SP_REGNUM))]
|
(use (reg:SI SP_REGNUM))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& flag_pic"
|
&& flag_pic"
|
".cprestore\tr0, %0"
|
".cprestore\tr0, %0"
|
)
|
)
|
|
|
(define_insn "cprestore_use_sp_score3"
|
(define_insn "cprestore_use_sp_score3"
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
[(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
|
(use (reg:SI SP_REGNUM))]
|
(use (reg:SI SP_REGNUM))]
|
"(TARGET_SCORE3) && flag_pic"
|
"(TARGET_SCORE3) && flag_pic"
|
".cprestore\tr0, %0"
|
".cprestore\tr0, %0"
|
[(set_attr "length" "4")])
|
[(set_attr "length" "4")])
|
|
|
(define_expand "doloop_end"
|
(define_expand "doloop_end"
|
[(use (match_operand 0 "" "")) ; loop pseudo
|
[(use (match_operand 0 "" "")) ; loop pseudo
|
(use (match_operand 1 "" "")) ; iterations; zero if unknown
|
(use (match_operand 1 "" "")) ; iterations; zero if unknown
|
(use (match_operand 2 "" "")) ; max iterations
|
(use (match_operand 2 "" "")) ; max iterations
|
(use (match_operand 3 "" "")) ; loop level
|
(use (match_operand 3 "" "")) ; loop level
|
(use (match_operand 4 "" ""))] ; label
|
(use (match_operand 4 "" ""))] ; label
|
"!TARGET_NHWLOOP"
|
"!TARGET_NHWLOOP"
|
{
|
{
|
if (INTVAL (operands[3]) > 1)
|
if (INTVAL (operands[3]) > 1)
|
FAIL;
|
FAIL;
|
|
|
if (GET_MODE (operands[0]) == SImode)
|
if (GET_MODE (operands[0]) == SImode)
|
{
|
{
|
rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);
|
rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);
|
emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));
|
emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));
|
}
|
}
|
else
|
else
|
FAIL;
|
FAIL;
|
|
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_insn "doloop_end_si"
|
(define_insn "doloop_end_si"
|
[(set (pc)
|
[(set (pc)
|
(if_then_else
|
(if_then_else
|
(ne (match_operand:SI 0 "sr0_operand" "")
|
(ne (match_operand:SI 0 "sr0_operand" "")
|
(const_int 0))
|
(const_int 0))
|
(label_ref (match_operand 1 "" ""))
|
(label_ref (match_operand 1 "" ""))
|
(pc)))
|
(pc)))
|
(set (match_dup 0)
|
(set (match_dup 0)
|
(plus:SI (match_dup 0)
|
(plus:SI (match_dup 0)
|
(const_int -1)))
|
(const_int -1)))
|
(clobber (reg:CC CC_REGNUM))]
|
(clobber (reg:CC CC_REGNUM))]
|
"!TARGET_NHWLOOP"
|
"!TARGET_NHWLOOP"
|
"bcnz %1"
|
"bcnz %1"
|
[(set_attr "type" "branch")
|
[(set_attr "type" "branch")
|
(set_attr "length" "4")])
|
(set_attr "length" "4")])
|
|
|
(define_insn "pushsi_score7"
|
(define_insn "pushsi_score7"
|
[(set (match_operand:SI 0 "push_operand" "=<")
|
[(set (match_operand:SI 0 "push_operand" "=<")
|
(match_operand:SI 1 "register_operand" "d"))]
|
(match_operand:SI 1 "register_operand" "d"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"push!\t%1, [r0]"
|
"push!\t%1, [r0]"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "pushsi_score3"
|
(define_insn "pushsi_score3"
|
[(set (match_operand:SI 0 "push_operand" "=<")
|
[(set (match_operand:SI 0 "push_operand" "=<")
|
(match_operand:SI 1 "register_operand" "d"))]
|
(match_operand:SI 1 "register_operand" "d"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"push!\t%1"
|
"push!\t%1"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "2")
|
(set_attr "length" "2")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "popsi_score7"
|
(define_insn "popsi_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(match_operand:SI 1 "pop_operand" ">"))]
|
(match_operand:SI 1 "pop_operand" ">"))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"pop!\t%0, [r0]"
|
"pop!\t%0, [r0]"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "popsi_score3"
|
(define_insn "popsi_score3"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(match_operand:SI 1 "pop_operand" ">"))]
|
(match_operand:SI 1 "pop_operand" ">"))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"pop!\t%0"
|
"pop!\t%0"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "2")
|
(set_attr "length" "2")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "load_multiple"
|
(define_expand "load_multiple"
|
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
|
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
|
(match_operand:SI 1 "" ""))
|
(match_operand:SI 1 "" ""))
|
(use (match_operand:SI 2 "" ""))
|
(use (match_operand:SI 2 "" ""))
|
(clobber (reg:SI 0))])]
|
(clobber (reg:SI 0))])]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
int regno, count, i;
|
int regno, count, i;
|
|
|
if (GET_CODE (operands[2]) != CONST_INT
|
if (GET_CODE (operands[2]) != CONST_INT
|
|| INTVAL (operands[2]) < 2
|
|| INTVAL (operands[2]) < 2
|
|| GET_CODE (operands[1]) != MEM
|
|| GET_CODE (operands[1]) != MEM
|
|| XEXP (operands[1], 0) != stack_pointer_rtx
|
|| XEXP (operands[1], 0) != stack_pointer_rtx
|
|| GET_CODE (operands[0]) != REG)
|
|| GET_CODE (operands[0]) != REG)
|
FAIL;
|
FAIL;
|
|
|
count = INTVAL (operands[2]);
|
count = INTVAL (operands[2]);
|
regno = REGNO (operands[0]);
|
regno = REGNO (operands[0]);
|
|
|
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
|
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
|
|
|
for (i = 0; i < count; i++)
|
for (i = 0; i < count; i++)
|
XVECEXP (operands[3], 0, i)
|
XVECEXP (operands[3], 0, i)
|
= gen_rtx_SET (VOIDmode,
|
= gen_rtx_SET (VOIDmode,
|
gen_rtx_REG (SImode, regno + i),
|
gen_rtx_REG (SImode, regno + i),
|
gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, stack_pointer_rtx)));
|
gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, stack_pointer_rtx)));
|
})
|
})
|
|
|
(define_insn ""
|
(define_insn ""
|
[(match_parallel 0 "score_load_multiple_operation"
|
[(match_parallel 0 "score_load_multiple_operation"
|
[(set (match_operand:SI 1 "register_operand" "=d")
|
[(set (match_operand:SI 1 "register_operand" "=d")
|
(mem:SI (post_inc:SI (reg:SI SP_REGNUM))))])]
|
(mem:SI (post_inc:SI (reg:SI SP_REGNUM))))])]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
return score_rpop (operands);
|
return score_rpop (operands);
|
}
|
}
|
[(set_attr "length" "2")])
|
[(set_attr "length" "2")])
|
|
|
(define_expand "store_multiple"
|
(define_expand "store_multiple"
|
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
|
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
|
(match_operand:SI 1 "" ""))
|
(match_operand:SI 1 "" ""))
|
(use (match_operand:SI 2 "" ""))
|
(use (match_operand:SI 2 "" ""))
|
(clobber (reg:SI 0))])]
|
(clobber (reg:SI 0))])]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
int regno, count, i;
|
int regno, count, i;
|
|
|
if (GET_CODE (operands[2]) != CONST_INT
|
if (GET_CODE (operands[2]) != CONST_INT
|
|| INTVAL (operands[2]) < 2
|
|| INTVAL (operands[2]) < 2
|
|| GET_CODE (operands[0]) != MEM
|
|| GET_CODE (operands[0]) != MEM
|
|| XEXP (operands[0], 0) != stack_pointer_rtx
|
|| XEXP (operands[0], 0) != stack_pointer_rtx
|
|| GET_CODE (operands[1]) != REG)
|
|| GET_CODE (operands[1]) != REG)
|
FAIL;
|
FAIL;
|
|
|
count = INTVAL (operands[2]);
|
count = INTVAL (operands[2]);
|
regno = REGNO (operands[1]);
|
regno = REGNO (operands[1]);
|
|
|
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
|
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
|
|
|
for (i = 0; i < count; i++)
|
for (i = 0; i < count; i++)
|
XVECEXP (operands[3], 0, i)
|
XVECEXP (operands[3], 0, i)
|
= gen_rtx_SET (VOIDmode,
|
= gen_rtx_SET (VOIDmode,
|
gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)),
|
gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)),
|
gen_rtx_REG (SImode, regno + i));
|
gen_rtx_REG (SImode, regno + i));
|
})
|
})
|
|
|
(define_insn ""
|
(define_insn ""
|
[(match_parallel 0 "score_store_multiple_operation"
|
[(match_parallel 0 "score_store_multiple_operation"
|
[(set (mem:SI (pre_dec:SI (reg:SI SP_REGNUM)))
|
[(set (mem:SI (pre_dec:SI (reg:SI SP_REGNUM)))
|
(match_operand:SI 1 "register_operand" "d"))])]
|
(match_operand:SI 1 "register_operand" "d"))])]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
{
|
{
|
return score_rpush (operands);
|
return score_rpush (operands);
|
}
|
}
|
[(set_attr "length" "2")])
|
[(set_attr "length" "2")])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
(match_operand:SI 1 "loreg_operand" ""))
|
(match_operand:SI 1 "loreg_operand" ""))
|
(set (match_operand:SI 2 "g32reg_operand" "")
|
(set (match_operand:SI 2 "g32reg_operand" "")
|
(match_operand:SI 3 "hireg_operand" ""))]
|
(match_operand:SI 3 "hireg_operand" ""))]
|
""
|
""
|
[(parallel
|
[(parallel
|
[(set (match_dup 0) (match_dup 1))
|
[(set (match_dup 0) (match_dup 1))
|
(set (match_dup 2) (match_dup 3))])])
|
(set (match_dup 2) (match_dup 3))])])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
[(set (match_operand:SI 0 "g32reg_operand" "")
|
(match_operand:SI 1 "hireg_operand" ""))
|
(match_operand:SI 1 "hireg_operand" ""))
|
(set (match_operand:SI 2 "g32reg_operand" "")
|
(set (match_operand:SI 2 "g32reg_operand" "")
|
(match_operand:SI 3 "loreg_operand" ""))]
|
(match_operand:SI 3 "loreg_operand" ""))]
|
""
|
""
|
[(parallel
|
[(parallel
|
[(set (match_dup 2) (match_dup 3))
|
[(set (match_dup 2) (match_dup 3))
|
(set (match_dup 0) (match_dup 1))])])
|
(set (match_dup 0) (match_dup 1))])])
|
|
|
(define_insn "movhilo"
|
(define_insn "movhilo"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(match_operand:SI 1 "loreg_operand" ""))
|
(match_operand:SI 1 "loreg_operand" ""))
|
(set (match_operand:SI 2 "register_operand" "=d")
|
(set (match_operand:SI 2 "register_operand" "=d")
|
(match_operand:SI 3 "hireg_operand" ""))])]
|
(match_operand:SI 3 "hireg_operand" ""))])]
|
""
|
""
|
"mfcehl\t%2, %0"
|
"mfcehl\t%2, %0"
|
[(set_attr "type" "fce")
|
[(set_attr "type" "fce")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "movsicc"
|
(define_expand "movsicc"
|
[(set (match_operand:SI 0 "register_operand" "")
|
[(set (match_operand:SI 0 "register_operand" "")
|
(if_then_else:SI (match_operator 1 "comparison_operator"
|
(if_then_else:SI (match_operator 1 "comparison_operator"
|
[(reg:CC CC_REGNUM) (const_int 0)])
|
[(reg:CC CC_REGNUM) (const_int 0)])
|
(match_operand:SI 2 "register_operand" "")
|
(match_operand:SI 2 "register_operand" "")
|
(match_operand:SI 3 "register_operand" "")))]
|
(match_operand:SI 3 "register_operand" "")))]
|
""
|
""
|
{
|
{
|
score_movsicc (operands);
|
score_movsicc (operands);
|
})
|
})
|
|
|
(define_insn "movsicc_internal_score7"
|
(define_insn "movsicc_internal_score7"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(if_then_else:SI (match_operator 1 "comparison_operator"
|
(if_then_else:SI (match_operator 1 "comparison_operator"
|
[(reg:CC CC_REGNUM) (const_int 0)])
|
[(reg:CC CC_REGNUM) (const_int 0)])
|
(match_operand:SI 2 "arith_operand" "d")
|
(match_operand:SI 2 "arith_operand" "d")
|
(match_operand:SI 3 "arith_operand" "0")))]
|
(match_operand:SI 3 "arith_operand" "0")))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"mv%C1\t%0, %2"
|
"mv%C1\t%0, %2"
|
[(set_attr "type" "cndmv")
|
[(set_attr "type" "cndmv")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "movsicc_internal_score3"
|
(define_insn "movsicc_internal_score3"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(if_then_else:SI (match_operator 1 "comparison_operator"
|
(if_then_else:SI (match_operator 1 "comparison_operator"
|
[(reg:CC CC_REGNUM) (const_int 0)])
|
[(reg:CC CC_REGNUM) (const_int 0)])
|
(match_operand:SI 2 "arith_operand" "d")
|
(match_operand:SI 2 "arith_operand" "d")
|
(match_operand:SI 3 "arith_operand" "0")))]
|
(match_operand:SI 3 "arith_operand" "0")))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"mv%G1\t%0, %2"
|
"mv%G1\t%0, %2"
|
[(set_attr "type" "cndmv")
|
[(set_attr "type" "cndmv")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "zero_extract_bittst_score7"
|
(define_insn "zero_extract_bittst_score7"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (unspec:SI
|
(compare:CC_NZ (unspec:SI
|
[(match_operand:SI 0 "register_operand" "*e,d")
|
[(match_operand:SI 0 "register_operand" "*e,d")
|
(match_operand:SI 1 "const_uimm5" "")]
|
(match_operand:SI 1 "const_uimm5" "")]
|
BITTST)
|
BITTST)
|
(const_int 0)))]
|
(const_int 0)))]
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
|
"@
|
"@
|
bittst!\t%0, %c1
|
bittst!\t%0, %c1
|
bittst.c\t%0, %c1"
|
bittst.c\t%0, %c1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "zero_extract_bittst_score3"
|
(define_insn "zero_extract_bittst_score3"
|
[(set (reg:CC_NZ CC_REGNUM)
|
[(set (reg:CC_NZ CC_REGNUM)
|
(compare:CC_NZ (unspec:SI
|
(compare:CC_NZ (unspec:SI
|
[(match_operand:SI 0 "register_operand" "e,d")
|
[(match_operand:SI 0 "register_operand" "e,d")
|
(match_operand:SI 1 "const_uimm5" "")]
|
(match_operand:SI 1 "const_uimm5" "")]
|
BITTST)
|
BITTST)
|
(const_int 0)))]
|
(const_int 0)))]
|
"(TARGET_SCORE3)"
|
"(TARGET_SCORE3)"
|
"@
|
"@
|
bittst!\t%0, %c1
|
bittst!\t%0, %c1
|
bittst.c\t%0, %c1"
|
bittst.c\t%0, %c1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "2,4")
|
(set_attr "length" "2,4")
|
(set_attr "up_c" "yes")
|
(set_attr "up_c" "yes")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "extzv"
|
(define_expand "extzv"
|
[(set (match_operand:SI 0 "register_operand" "")
|
[(set (match_operand:SI 0 "register_operand" "")
|
(zero_extract (match_operand:SI 1 "memory_operand" "")
|
(zero_extract (match_operand:SI 1 "memory_operand" "")
|
(match_operand:SI 2 "immediate_operand" "")
|
(match_operand:SI 2 "immediate_operand" "")
|
(match_operand:SI 3 "immediate_operand" "")))]
|
(match_operand:SI 3 "immediate_operand" "")))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
{
|
{
|
if (score_unaligned_load (operands))
|
if (score_unaligned_load (operands))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
})
|
})
|
|
|
(define_expand "insv"
|
(define_expand "insv"
|
[(set (zero_extract (match_operand:SI 0 "memory_operand" "")
|
[(set (zero_extract (match_operand:SI 0 "memory_operand" "")
|
(match_operand:SI 1 "immediate_operand" "")
|
(match_operand:SI 1 "immediate_operand" "")
|
(match_operand:SI 2 "immediate_operand" ""))
|
(match_operand:SI 2 "immediate_operand" ""))
|
(match_operand:SI 3 "register_operand" ""))]
|
(match_operand:SI 3 "register_operand" ""))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
{
|
{
|
if (score_unaligned_store (operands))
|
if (score_unaligned_store (operands))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
})
|
})
|
|
|
(define_expand "extv"
|
(define_expand "extv"
|
[(set (match_operand:SI 0 "register_operand" "")
|
[(set (match_operand:SI 0 "register_operand" "")
|
(sign_extract (match_operand:SI 1 "memory_operand" "")
|
(sign_extract (match_operand:SI 1 "memory_operand" "")
|
(match_operand:SI 2 "immediate_operand" "")
|
(match_operand:SI 2 "immediate_operand" "")
|
(match_operand:SI 3 "immediate_operand" "")))]
|
(match_operand:SI 3 "immediate_operand" "")))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
{
|
{
|
if (score_unaligned_load (operands))
|
if (score_unaligned_load (operands))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
})
|
})
|
|
|
(define_expand "movmemsi"
|
(define_expand "movmemsi"
|
[(parallel [(set (match_operand:BLK 0 "general_operand")
|
[(parallel [(set (match_operand:BLK 0 "general_operand")
|
(match_operand:BLK 1 "general_operand"))
|
(match_operand:BLK 1 "general_operand"))
|
(use (match_operand:SI 2 ""))
|
(use (match_operand:SI 2 ""))
|
(use (match_operand:SI 3 "const_int_operand"))])]
|
(use (match_operand:SI 3 "const_int_operand"))])]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (TARGET_ULS))
|
&& (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
{
|
{
|
if (score_block_move (operands))
|
if (score_block_move (operands))
|
DONE;
|
DONE;
|
else
|
else
|
FAIL;
|
FAIL;
|
})
|
})
|
|
|
(define_insn "move_lbu_a"
|
(define_insn "move_lbu_a"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (match_operand:QI 3 "register_operand" "=d")
|
(set (match_operand:QI 3 "register_operand" "=d")
|
(mem:QI (match_dup 1)))]
|
(mem:QI (match_dup 1)))]
|
""
|
""
|
"lbu\t%3, [%1]+, %2"
|
"lbu\t%3, [%1]+, %2"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "QI")])
|
(set_attr "mode" "QI")])
|
|
|
(define_insn "move_lhu_a"
|
(define_insn "move_lhu_a"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (match_operand:HI 3 "register_operand" "=d")
|
(set (match_operand:HI 3 "register_operand" "=d")
|
(mem:HI (match_dup 1)))]
|
(mem:HI (match_dup 1)))]
|
""
|
""
|
"lhu\t%3, [%1]+, %2"
|
"lhu\t%3, [%1]+, %2"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "HI")])
|
(set_attr "mode" "HI")])
|
|
|
(define_insn "move_lw_a"
|
(define_insn "move_lw_a"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (match_operand:SI 3 "register_operand" "=d")
|
(set (match_operand:SI 3 "register_operand" "=d")
|
(mem:SI (match_dup 1)))]
|
(mem:SI (match_dup 1)))]
|
""
|
""
|
"lw\t%3, [%1]+, %2"
|
"lw\t%3, [%1]+, %2"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_sb_a"
|
(define_insn "move_sb_a"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (mem:QI (match_dup 1))
|
(set (mem:QI (match_dup 1))
|
(match_operand:QI 3 "register_operand" "d"))]
|
(match_operand:QI 3 "register_operand" "d"))]
|
""
|
""
|
"sb\t%3, [%1]+, %2"
|
"sb\t%3, [%1]+, %2"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "QI")])
|
(set_attr "mode" "QI")])
|
|
|
(define_insn "move_sh_a"
|
(define_insn "move_sh_a"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (mem:HI (match_dup 1))
|
(set (mem:HI (match_dup 1))
|
(match_operand:HI 3 "register_operand" "d"))]
|
(match_operand:HI 3 "register_operand" "d"))]
|
""
|
""
|
"sh\t%3, [%1]+, %2"
|
"sh\t%3, [%1]+, %2"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "HI")])
|
(set_attr "mode" "HI")])
|
|
|
(define_insn "move_sw_a"
|
(define_insn "move_sw_a"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (mem:SI (match_dup 1))
|
(set (mem:SI (match_dup 1))
|
(match_operand:SI 3 "register_operand" "d"))]
|
(match_operand:SI 3 "register_operand" "d"))]
|
""
|
""
|
"sw\t%3, [%1]+, %2"
|
"sw\t%3, [%1]+, %2"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_lbu_b"
|
(define_insn "move_lbu_b"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (match_operand:QI 3 "register_operand" "=d")
|
(set (match_operand:QI 3 "register_operand" "=d")
|
(mem:QI (plus:SI (match_dup 1)
|
(mem:QI (plus:SI (match_dup 1)
|
(match_dup 2))))]
|
(match_dup 2))))]
|
""
|
""
|
"lbu\t%3, [%1, %2]+"
|
"lbu\t%3, [%1, %2]+"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "QI")])
|
(set_attr "mode" "QI")])
|
|
|
(define_insn "move_lhu_b"
|
(define_insn "move_lhu_b"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (match_operand:HI 3 "register_operand" "=d")
|
(set (match_operand:HI 3 "register_operand" "=d")
|
(mem:HI (plus:SI (match_dup 1)
|
(mem:HI (plus:SI (match_dup 1)
|
(match_dup 2))))]
|
(match_dup 2))))]
|
""
|
""
|
"lhu\t%3, [%1, %2]+"
|
"lhu\t%3, [%1, %2]+"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "HI")])
|
(set_attr "mode" "HI")])
|
|
|
(define_insn "move_lw_b"
|
(define_insn "move_lw_b"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (match_operand:SI 3 "register_operand" "=d")
|
(set (match_operand:SI 3 "register_operand" "=d")
|
(mem:SI (plus:SI (match_dup 1)
|
(mem:SI (plus:SI (match_dup 1)
|
(match_dup 2))))]
|
(match_dup 2))))]
|
""
|
""
|
"lw\t%3, [%1, %2]+"
|
"lw\t%3, [%1, %2]+"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_sb_b"
|
(define_insn "move_sb_b"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (mem:QI (plus:SI (match_dup 1)
|
(set (mem:QI (plus:SI (match_dup 1)
|
(match_dup 2)))
|
(match_dup 2)))
|
(match_operand:QI 3 "register_operand" "d"))]
|
(match_operand:QI 3 "register_operand" "d"))]
|
""
|
""
|
"sb\t%3, [%1, %2]+"
|
"sb\t%3, [%1, %2]+"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "QI")])
|
(set_attr "mode" "QI")])
|
|
|
(define_insn "move_sh_b"
|
(define_insn "move_sh_b"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (mem:HI (plus:SI (match_dup 1)
|
(set (mem:HI (plus:SI (match_dup 1)
|
(match_dup 2)))
|
(match_dup 2)))
|
(match_operand:HI 3 "register_operand" "d"))]
|
(match_operand:HI 3 "register_operand" "d"))]
|
""
|
""
|
"sh\t%3, [%1, %2]+"
|
"sh\t%3, [%1, %2]+"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "HI")])
|
(set_attr "mode" "HI")])
|
|
|
(define_insn "move_sw_b"
|
(define_insn "move_sw_b"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(match_operand:SI 2 "const_simm12" "")))
|
(match_operand:SI 2 "const_simm12" "")))
|
(set (mem:SI (plus:SI (match_dup 1)
|
(set (mem:SI (plus:SI (match_dup 1)
|
(match_dup 2)))
|
(match_dup 2)))
|
(match_operand:SI 3 "register_operand" "d"))]
|
(match_operand:SI 3 "register_operand" "d"))]
|
""
|
""
|
"sw\t%3, [%1, %2]+"
|
"sw\t%3, [%1, %2]+"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_lcb"
|
(define_insn "move_lcb"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(const_int 4)))
|
(const_int 4)))
|
(set (reg:SI LC_REGNUM)
|
(set (reg:SI LC_REGNUM)
|
(unspec:SI [(mem:BLK (match_dup 1))] LCB))]
|
(unspec:SI [(mem:BLK (match_dup 1))] LCB))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
"lcb\t[%1]+"
|
"lcb\t[%1]+"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_lcw"
|
(define_insn "move_lcw"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(const_int 4)))
|
(const_int 4)))
|
(set (match_operand:SI 2 "register_operand" "=d")
|
(set (match_operand:SI 2 "register_operand" "=d")
|
(unspec:SI [(mem:BLK (match_dup 1))
|
(unspec:SI [(mem:BLK (match_dup 1))
|
(reg:SI LC_REGNUM)] LCW))
|
(reg:SI LC_REGNUM)] LCW))
|
(set (reg:SI LC_REGNUM)
|
(set (reg:SI LC_REGNUM)
|
(unspec:SI [(mem:BLK (match_dup 1))] LCB))]
|
(unspec:SI [(mem:BLK (match_dup 1))] LCB))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
"lcw\t%2, [%1]+"
|
"lcw\t%2, [%1]+"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_lce"
|
(define_insn "move_lce"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(const_int 4)))
|
(const_int 4)))
|
(set (match_operand:SI 2 "register_operand" "=d")
|
(set (match_operand:SI 2 "register_operand" "=d")
|
(unspec:SI [(mem:BLK (match_dup 1))
|
(unspec:SI [(mem:BLK (match_dup 1))
|
(reg:SI LC_REGNUM)] LCE))]
|
(reg:SI LC_REGNUM)] LCE))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
"lce\t%2, [%1]+"
|
"lce\t%2, [%1]+"
|
[(set_attr "type" "load")
|
[(set_attr "type" "load")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_scb"
|
(define_insn "move_scb"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(const_int 4)))
|
(const_int 4)))
|
(set (mem:BLK (match_dup 1))
|
(set (mem:BLK (match_dup 1))
|
(unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))
|
(unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))
|
(set (reg:SI SC_REGNUM)
|
(set (reg:SI SC_REGNUM)
|
(unspec:SI [(match_dup 2)] SCLC))]
|
(unspec:SI [(match_dup 2)] SCLC))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
"scb\t%2, [%1]+"
|
"scb\t%2, [%1]+"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_scw"
|
(define_insn "move_scw"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(const_int 4)))
|
(const_int 4)))
|
(set (mem:BLK (match_dup 1))
|
(set (mem:BLK (match_dup 1))
|
(unspec:BLK [(match_operand:SI 2 "register_operand" "d")
|
(unspec:BLK [(match_operand:SI 2 "register_operand" "d")
|
(reg:SI SC_REGNUM)] SCW))
|
(reg:SI SC_REGNUM)] SCW))
|
(set (reg:SI SC_REGNUM)
|
(set (reg:SI SC_REGNUM)
|
(unspec:SI [(match_dup 2)] SCLC))]
|
(unspec:SI [(match_dup 2)] SCLC))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
"scw\t%2, [%1]+"
|
"scw\t%2, [%1]+"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "move_sce"
|
(define_insn "move_sce"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(plus:SI (match_operand:SI 1 "register_operand" "0")
|
(const_int 4)))
|
(const_int 4)))
|
(set (mem:BLK (match_dup 1))
|
(set (mem:BLK (match_dup 1))
|
(unspec:BLK [(reg:SI SC_REGNUM)] SCE))]
|
(unspec:BLK [(reg:SI SC_REGNUM)] SCE))]
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
"((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
&& (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
|| (TARGET_SCORE3 && TARGET_ULS)"
|
"sce [%1]+"
|
"sce [%1]+"
|
[(set_attr "type" "store")
|
[(set_attr "type" "store")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "andsi3_extzh"
|
(define_insn "andsi3_extzh"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(and:SI (match_operand:SI 1 "register_operand" "d")
|
(and:SI (match_operand:SI 1 "register_operand" "d")
|
(const_int 65535)))]
|
(const_int 65535)))]
|
""
|
""
|
"extzh\t%0, %1"
|
"extzh\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "length" "4")
|
(set_attr "length" "4")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "clzsi2"
|
(define_insn "clzsi2"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(clz:SI (match_operand:SI 1 "register_operand" "d")))]
|
(clz:SI (match_operand:SI 1 "register_operand" "d")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3)"
|
"(TARGET_SCORE7D || TARGET_SCORE3)"
|
"clz\t%0, %1"
|
"clz\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "smaxsi3"
|
(define_insn "smaxsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(smax:SI (match_operand:SI 1 "register_operand" "d")
|
(smax:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))]
|
(match_operand:SI 2 "register_operand" "d")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"max\t%0, %1, %2"
|
"max\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "sminsi3"
|
(define_insn "sminsi3"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(smin:SI (match_operand:SI 1 "register_operand" "d")
|
(smin:SI (match_operand:SI 1 "register_operand" "d")
|
(match_operand:SI 2 "register_operand" "d")))]
|
(match_operand:SI 2 "register_operand" "d")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"min\t%0, %1, %2"
|
"min\t%0, %1, %2"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "abssi2"
|
(define_insn "abssi2"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(abs:SI (match_operand:SI 1 "register_operand" "d")))]
|
(abs:SI (match_operand:SI 1 "register_operand" "d")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"abs\t%0, %1"
|
"abs\t%0, %1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "sffs"
|
(define_insn "sffs"
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
[(set (match_operand:SI 0 "register_operand" "=d")
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
|
(unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"bitrev\t%0, %1, r0\;clz\t%0, %0\;addi\t%0, 0x1"
|
"bitrev\t%0, %1, r0\;clz\t%0, %0\;addi\t%0, 0x1"
|
[(set_attr "type" "arith")
|
[(set_attr "type" "arith")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_expand "ffssi2"
|
(define_expand "ffssi2"
|
[(set (match_operand:SI 0 "register_operand")
|
[(set (match_operand:SI 0 "register_operand")
|
(ffs:SI (match_operand:SI 1 "register_operand")))]
|
(ffs:SI (match_operand:SI 1 "register_operand")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
{
|
{
|
emit_insn (gen_sffs (operands[0], operands[1]));
|
emit_insn (gen_sffs (operands[0], operands[1]));
|
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
|
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
|
gen_rtx_COMPARE (CC_NZmode, operands[0],
|
gen_rtx_COMPARE (CC_NZmode, operands[0],
|
GEN_INT (33))));
|
GEN_INT (33))));
|
if (TARGET_SCORE7D)
|
if (TARGET_SCORE7D)
|
emit_insn (gen_movsicc_internal_score7 (operands[0],
|
emit_insn (gen_movsicc_internal_score7 (operands[0],
|
gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
|
gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
|
GEN_INT (0),
|
GEN_INT (0),
|
operands[0]));
|
operands[0]));
|
else
|
else
|
emit_insn (gen_movsicc_internal_score3 (operands[0],
|
emit_insn (gen_movsicc_internal_score3 (operands[0],
|
gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
|
gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
|
GEN_INT (0),
|
GEN_INT (0),
|
operands[0]));
|
operands[0]));
|
DONE;
|
DONE;
|
})
|
})
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:SI 0 "loreg_operand" "")
|
[(set (match_operand:SI 0 "loreg_operand" "")
|
(match_operand:SI 1 "register_operand" ""))
|
(match_operand:SI 1 "register_operand" ""))
|
(set (match_operand:SI 2 "hireg_operand" "")
|
(set (match_operand:SI 2 "hireg_operand" "")
|
(match_operand:SI 3 "register_operand" ""))]
|
(match_operand:SI 3 "register_operand" ""))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
[(parallel
|
[(parallel
|
[(set (match_dup 0) (match_dup 1))
|
[(set (match_dup 0) (match_dup 1))
|
(set (match_dup 2) (match_dup 3))])])
|
(set (match_dup 2) (match_dup 3))])])
|
|
|
(define_peephole2
|
(define_peephole2
|
[(set (match_operand:SI 0 "hireg_operand" "")
|
[(set (match_operand:SI 0 "hireg_operand" "")
|
(match_operand:SI 1 "register_operand" ""))
|
(match_operand:SI 1 "register_operand" ""))
|
(set (match_operand:SI 2 "loreg_operand" "")
|
(set (match_operand:SI 2 "loreg_operand" "")
|
(match_operand:SI 3 "register_operand" ""))]
|
(match_operand:SI 3 "register_operand" ""))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
[(parallel
|
[(parallel
|
[(set (match_dup 2) (match_dup 3))
|
[(set (match_dup 2) (match_dup 3))
|
(set (match_dup 0) (match_dup 1))])])
|
(set (match_dup 0) (match_dup 1))])])
|
|
|
(define_insn "movtohilo"
|
(define_insn "movtohilo"
|
[(parallel
|
[(parallel
|
[(set (match_operand:SI 0 "loreg_operand" "=l")
|
[(set (match_operand:SI 0 "loreg_operand" "=l")
|
(match_operand:SI 1 "register_operand" "d"))
|
(match_operand:SI 1 "register_operand" "d"))
|
(set (match_operand:SI 2 "hireg_operand" "=h")
|
(set (match_operand:SI 2 "hireg_operand" "=h")
|
(match_operand:SI 3 "register_operand" "d"))])]
|
(match_operand:SI 3 "register_operand" "d"))])]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"mtcehl\t%3, %1"
|
"mtcehl\t%3, %1"
|
[(set_attr "type" "fce")
|
[(set_attr "type" "fce")
|
(set_attr "mode" "SI")])
|
(set_attr "mode" "SI")])
|
|
|
(define_insn "mulsi3addsi"
|
(define_insn "mulsi3addsi"
|
[(set (match_operand:SI 0 "register_operand" "=l,l,d")
|
[(set (match_operand:SI 0 "register_operand" "=l,l,d")
|
(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
|
(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
|
(match_operand:SI 3 "register_operand" "d,d,d"))
|
(match_operand:SI 3 "register_operand" "d,d,d"))
|
(match_operand:SI 1 "register_operand" "0,d,l")))
|
(match_operand:SI 1 "register_operand" "0,d,l")))
|
(clobber (reg:SI HI_REGNUM))]
|
(clobber (reg:SI HI_REGNUM))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"@
|
"@
|
mad\t%2, %3
|
mad\t%2, %3
|
mtcel%S1\t%1\;mad\t%2, %3
|
mtcel%S1\t%1\;mad\t%2, %3
|
mad\t%2, %3\;mfcel%S0\t%0"
|
mad\t%2, %3\;mfcel%S0\t%0"
|
[(set_attr "mode" "SI")])
|
[(set_attr "mode" "SI")])
|
|
|
(define_insn "mulsi3subsi"
|
(define_insn "mulsi3subsi"
|
[(set (match_operand:SI 0 "register_operand" "=l,l,d")
|
[(set (match_operand:SI 0 "register_operand" "=l,l,d")
|
(minus:SI (match_operand:SI 1 "register_operand" "0,d,l")
|
(minus:SI (match_operand:SI 1 "register_operand" "0,d,l")
|
(mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
|
(mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
|
(match_operand:SI 3 "register_operand" "d,d,d"))))
|
(match_operand:SI 3 "register_operand" "d,d,d"))))
|
(clobber (reg:SI HI_REGNUM))]
|
(clobber (reg:SI HI_REGNUM))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"@
|
"@
|
msb\t%2, %3
|
msb\t%2, %3
|
mtcel%S1\t%1\;msb\t%2, %3
|
mtcel%S1\t%1\;msb\t%2, %3
|
msb\t%2, %3\;mfcel%S0\t%0"
|
msb\t%2, %3\;mfcel%S0\t%0"
|
[(set_attr "mode" "SI")])
|
[(set_attr "mode" "SI")])
|
|
|
(define_insn "mulsidi3adddi"
|
(define_insn "mulsidi3adddi"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(plus:DI (mult:DI
|
(plus:DI (mult:DI
|
(sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
|
(sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
|
(sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
|
(sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
|
(match_operand:DI 1 "register_operand" "0")))]
|
(match_operand:DI 1 "register_operand" "0")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"mad\t%2, %3"
|
"mad\t%2, %3"
|
[(set_attr "mode" "DI")])
|
[(set_attr "mode" "DI")])
|
|
|
(define_insn "umulsidi3adddi"
|
(define_insn "umulsidi3adddi"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(plus:DI (mult:DI
|
(plus:DI (mult:DI
|
(zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
|
(zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
|
(zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
|
(zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
|
(match_operand:DI 1 "register_operand" "0")))]
|
(match_operand:DI 1 "register_operand" "0")))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"madu\t%2, %3"
|
"madu\t%2, %3"
|
[(set_attr "mode" "DI")])
|
[(set_attr "mode" "DI")])
|
|
|
(define_insn "mulsidi3subdi"
|
(define_insn "mulsidi3subdi"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(minus:DI
|
(minus:DI
|
(match_operand:DI 1 "register_operand" "0")
|
(match_operand:DI 1 "register_operand" "0")
|
(mult:DI
|
(mult:DI
|
(sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
|
(sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
|
(sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
|
(sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"msb\t%2, %3"
|
"msb\t%2, %3"
|
[(set_attr "mode" "DI")])
|
[(set_attr "mode" "DI")])
|
|
|
(define_insn "umulsidi3subdi"
|
(define_insn "umulsidi3subdi"
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
[(set (match_operand:DI 0 "register_operand" "=x")
|
(minus:DI
|
(minus:DI
|
(match_operand:DI 1 "register_operand" "0")
|
(match_operand:DI 1 "register_operand" "0")
|
(mult:DI (zero_extend:DI
|
(mult:DI (zero_extend:DI
|
(match_operand:SI 2 "register_operand" "%d"))
|
(match_operand:SI 2 "register_operand" "%d"))
|
(zero_extend:DI
|
(zero_extend:DI
|
(match_operand:SI 3 "register_operand" "d")))))]
|
(match_operand:SI 3 "register_operand" "d")))))]
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"(TARGET_SCORE7D || TARGET_SCORE3D)"
|
"msbu\t%2, %3"
|
"msbu\t%2, %3"
|
[(set_attr "mode" "DI")])
|
[(set_attr "mode" "DI")])
|
|
|
|
|