;; Constraint definitions for SPARC.
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;; Constraint definitions for SPARC.
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;;; Unused letters:
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;;; Unused letters:
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;;; ABCD P Z
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;;; ABCD P Z
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;;; a jkl q tuvwxyz
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;;; a jkl q tuvwxyz
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;; Register constraints
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;; Register constraints
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(define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)"
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(define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)"
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"Any floating-point register in VIS mode")
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"Any floating-point register in VIS mode")
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(define_register_constraint "c" "FPCC_REGS"
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(define_register_constraint "c" "FPCC_REGS"
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"Floating-point condition code register")
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"Floating-point condition code register")
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(define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)"
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(define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)"
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"Lower floating-point register in VIS mode")
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"Lower floating-point register in VIS mode")
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;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
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;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
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;; MD file for V8 and V9.
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;; MD file for V8 and V9.
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(define_register_constraint "e" "TARGET_V9 ? EXTRA_FP_REGS : FP_REGS"
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(define_register_constraint "e" "TARGET_V9 ? EXTRA_FP_REGS : FP_REGS"
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"Any floating-point register")
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"Any floating-point register")
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(define_register_constraint "f" "FP_REGS"
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(define_register_constraint "f" "FP_REGS"
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"Lower floating-point register")
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"Lower floating-point register")
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(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
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(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
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"64-bit global or out register in V8+ mode")
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"64-bit global or out register in V8+ mode")
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;; Floating-point constant constraints
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;; Floating-point constant constraints
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(define_constraint "G"
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(define_constraint "G"
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"The floating-point zero constant"
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"The floating-point zero constant"
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "const_zero_operand (op, mode)")))
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(match_test "const_zero_operand (op, mode)")))
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;; Integer constant constraints
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;; Integer constant constraints
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(define_constraint "H"
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(define_constraint "H"
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"Valid operand of double arithmetic operation"
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"Valid operand of double arithmetic operation"
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "arith_double_operand (op, DImode)")))
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(match_test "arith_double_operand (op, DImode)")))
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(define_constraint "I"
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(define_constraint "I"
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"Signed 13-bit integer constant"
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"Signed 13-bit integer constant"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "SPARC_SIMM13_P (ival)")))
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(match_test "SPARC_SIMM13_P (ival)")))
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(define_constraint "J"
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(define_constraint "J"
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"The integer zero constant"
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"The integer zero constant"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "ival == 0")))
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(match_test "ival == 0")))
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(define_constraint "K"
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(define_constraint "K"
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"Signed 32-bit constant that can be loaded with a sethi instruction"
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"Signed 32-bit constant that can be loaded with a sethi instruction"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "SPARC_SETHI32_P (ival)")))
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(match_test "SPARC_SETHI32_P (ival)")))
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(define_constraint "L"
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(define_constraint "L"
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"Signed 11-bit integer constant"
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"Signed 11-bit integer constant"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "SPARC_SIMM11_P (ival)")))
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(match_test "SPARC_SIMM11_P (ival)")))
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(define_constraint "M"
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(define_constraint "M"
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"Signed 10-bit integer constant"
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"Signed 10-bit integer constant"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "SPARC_SIMM10_P (ival)")))
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(match_test "SPARC_SIMM10_P (ival)")))
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(define_constraint "N"
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(define_constraint "N"
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"Signed constant that can be loaded with a sethi instruction"
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"Signed constant that can be loaded with a sethi instruction"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "SPARC_SETHI_P (ival)")))
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(match_test "SPARC_SETHI_P (ival)")))
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(define_constraint "O"
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(define_constraint "O"
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"The 4096 constant"
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"The 4096 constant"
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(and (match_code "const_int")
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(and (match_code "const_int")
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(match_test "ival == 4096")))
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(match_test "ival == 4096")))
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;; Extra constraints
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;; Extra constraints
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;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
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;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
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;; i.e. accept pseudo-registers during reload.
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;; i.e. accept pseudo-registers during reload.
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(define_constraint "D"
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(define_constraint "D"
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"const_vector"
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"const_vector"
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(and (match_code "const_vector")
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(and (match_code "const_vector")
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(match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT")))
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(match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT")))
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(define_constraint "Q"
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(define_constraint "Q"
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"Floating-point constant that can be loaded with a sethi instruction"
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"Floating-point constant that can be loaded with a sethi instruction"
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "fp_sethi_p (op)")))
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(match_test "fp_sethi_p (op)")))
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(define_constraint "R"
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(define_constraint "R"
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"Floating-point constant that can be loaded with a move instruction"
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"Floating-point constant that can be loaded with a move instruction"
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "fp_mov_p (op)")))
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(match_test "fp_mov_p (op)")))
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(define_constraint "S"
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(define_constraint "S"
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"Floating-point constant that can be loaded with a high/lo_sum sequence"
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"Floating-point constant that can be loaded with a high/lo_sum sequence"
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(and (match_code "const_double")
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(and (match_code "const_double")
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(match_test "fp_high_losum_p (op)")))
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(match_test "fp_high_losum_p (op)")))
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;; Not needed in 64-bit mode
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;; Not needed in 64-bit mode
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(define_constraint "T"
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(define_constraint "T"
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"Memory reference whose address is aligned to 8-byte boundary"
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"Memory reference whose address is aligned to 8-byte boundary"
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(and (match_test "TARGET_ARCH32")
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(and (match_test "TARGET_ARCH32")
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(match_code "mem,reg")
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(match_code "mem,reg")
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(match_test "memory_ok_for_ldd (op)")))
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(match_test "memory_ok_for_ldd (op)")))
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;; Not needed in 64-bit mode
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;; Not needed in 64-bit mode
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(define_constraint "U"
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(define_constraint "U"
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"Pseudo-register or hard even-numbered integer register"
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"Pseudo-register or hard even-numbered integer register"
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(and (match_test "TARGET_ARCH32")
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(and (match_test "TARGET_ARCH32")
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(match_code "reg")
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(match_code "reg")
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(ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
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(ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
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(not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
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(not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
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(match_test "register_ok_for_ldd (op)")))
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(match_test "register_ok_for_ldd (op)")))
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;; Equivalent to 'T' but available in 64-bit mode
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;; Equivalent to 'T' but available in 64-bit mode
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(define_constraint "W"
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(define_constraint "W"
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"Memory reference for 'e' constraint floating-point register"
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"Memory reference for 'e' constraint floating-point register"
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(and (match_code "mem,reg")
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(and (match_code "mem,reg")
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(match_test "memory_ok_for_ldd (op)")))
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(match_test "memory_ok_for_ldd (op)")))
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(define_constraint "Y"
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(define_constraint "Y"
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"The vector zero constant"
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"The vector zero constant"
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(and (match_code "const_vector")
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(and (match_code "const_vector")
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(match_test "const_zero_operand (op, mode)")))
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(match_test "const_zero_operand (op, mode)")))
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