;; Scheduling description for SPARClet.
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;; Scheduling description for SPARClet.
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;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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;;
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;;
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;; This file is part of GCC.
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;; This file is part of GCC.
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;;
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; any later version.
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;;
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; GNU General Public License for more details.
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;;
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;;
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;; You should have received a copy of the GNU General Public License
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; .
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;; The SPARClet is a single-issue processor.
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;; The SPARClet is a single-issue processor.
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(define_automaton "sparclet")
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(define_automaton "sparclet")
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(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet")
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(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet")
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(define_cpu_unit "sl_store,sl_imul" "sparclet")
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(define_cpu_unit "sl_store,sl_imul" "sparclet")
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(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)")
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(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)")
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(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)")
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(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)")
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(define_insn_reservation "sl_ld" 3
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(define_insn_reservation "sl_ld" 3
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(and (eq_attr "cpu" "tsc701")
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(and (eq_attr "cpu" "tsc701")
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(eq_attr "type" "load,sload"))
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(eq_attr "type" "load,sload"))
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"sl_load_any, sl_load_any, sl_load_any")
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"sl_load_any, sl_load_any, sl_load_any")
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(define_insn_reservation "sl_st" 3
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(define_insn_reservation "sl_st" 3
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(and (eq_attr "cpu" "tsc701")
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(and (eq_attr "cpu" "tsc701")
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(eq_attr "type" "store"))
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(eq_attr "type" "store"))
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"(sl_store+sl_load_all)*3")
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"(sl_store+sl_load_all)*3")
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(define_insn_reservation "sl_imul" 5
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(define_insn_reservation "sl_imul" 5
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(and (eq_attr "cpu" "tsc701")
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(and (eq_attr "cpu" "tsc701")
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(eq_attr "type" "imul"))
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(eq_attr "type" "imul"))
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"sl_imul*5")
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"sl_imul*5")
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