Subversion Repositories openrisc_2011-10-31

// Test EH when V4SI SIMD registers are involved.

// Test EH when V4SI SIMD registers are involved.

// Contributed by Aldy Hernandez (aldy@quesejoda.com).

// Contributed by Aldy Hernandez (aldy@quesejoda.com).

// { dg-options "-O -Wno-abi" }

// { dg-options "-O -Wno-abi" }

// { dg-options "-O -w" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }

// { dg-options "-O -w" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }

// { dg-options "-O -w" { target powerpc*-*-* } }

// { dg-options "-O -w" { target powerpc*-*-* } }

// { dg-options "-O -w -maltivec" { target { powerpc*-*-* && vmx_hw } } }

// { dg-options "-O -w -maltivec" { target { powerpc*-*-* && vmx_hw } } }

// { dg-do run }

// { dg-do run }

#include "check-vect.h"

#include "check-vect.h"

typedef int __attribute__((vector_size (16))) vecint;

typedef int __attribute__((vector_size (16))) vecint;

vecint vecfunc (vecint beachbum)

vecint vecfunc (vecint beachbum)

{

{

  return beachbum;

  return beachbum;

}

}

void f3 (void)

void f3 (void)

{

{

  vecint foobar = (vecint) {0, 0};

  vecint foobar = (vecint) {0, 0};

  foobar = vecfunc (foobar);

  foobar = vecfunc (foobar);

  throw int();

  throw int();

}

}

void f2 (void)

void f2 (void)

{

{

  vecint foobar = (vecint) {0, 0};

  vecint foobar = (vecint) {0, 0};

  foobar = vecfunc (foobar);

  foobar = vecfunc (foobar);

  f3 ();

  f3 ();

}

}

void f1 (void)

void f1 (void)

{

{

  int i;

  int i;

  try

  try

    {

    {

      f2 ();

      f2 ();

    }

    }

  catch (int)

  catch (int)

    {

    {

      i = 9;

      i = 9;

    }

    }

}

}

int main ()

int main ()

{

{

  /* Exit with zero if the hardware does not support AltiVec instructions.  */

  /* Exit with zero if the hardware does not support AltiVec instructions.  */

  check_vect ();

  check_vect ();

  f1 ();

  f1 ();

  return 0;

  return 0;

}

}