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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 297 |
Rev 384 |
/* PR target/13380.
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/* PR target/13380.
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On m32r, the condition code register, (reg:SI 17), was replaced with
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On m32r, the condition code register, (reg:SI 17), was replaced with
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a pseudo reg, which would cause an unrecognized insn. */
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a pseudo reg, which would cause an unrecognized insn. */
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void
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void
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foo (unsigned int a, unsigned int b)
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foo (unsigned int a, unsigned int b)
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{
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{
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if (a > b)
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if (a > b)
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{
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{
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while (a)
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while (a)
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{
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{
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switch (b)
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switch (b)
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{
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{
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default:
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default:
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a = 0;
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a = 0;
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case 2:
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case 2:
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a = 0;
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a = 0;
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case 1:
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case 1:
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a = 0;
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a = 0;
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case 0:
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case 0:
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;
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;
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}
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}
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}
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}
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}
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}
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}
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}
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