URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 298 |
Rev 384 |
/* Verify that we optimize to conditional traps. */
|
/* Verify that we optimize to conditional traps. */
|
/* { dg-options "-O" } */
|
/* { dg-options "-O" } */
|
/* { dg-do compile { target rs6000-*-* powerpc*-*-* sparc*-*-* ia64-*-* } } */
|
/* { dg-do compile { target rs6000-*-* powerpc*-*-* sparc*-*-* ia64-*-* } } */
|
/* { dg-final { scan-assembler-not "^\t(trap|ta|break)\[ \t\]" } } */
|
/* { dg-final { scan-assembler-not "^\t(trap|ta|break)\[ \t\]" } } */
|
|
|
void f1(int p)
|
void f1(int p)
|
{
|
{
|
if (p)
|
if (p)
|
__builtin_trap();
|
__builtin_trap();
|
}
|
}
|
|
|
void f2(int p)
|
void f2(int p)
|
{
|
{
|
if (p)
|
if (p)
|
__builtin_trap();
|
__builtin_trap();
|
else
|
else
|
bar();
|
bar();
|
}
|
}
|
|
|
void f3(int p)
|
void f3(int p)
|
{
|
{
|
if (p)
|
if (p)
|
bar();
|
bar();
|
else
|
else
|
__builtin_trap();
|
__builtin_trap();
|
}
|
}
|
|
|
void f4(int p, int q)
|
void f4(int p, int q)
|
{
|
{
|
if (p)
|
if (p)
|
{
|
{
|
bar();
|
bar();
|
if (q)
|
if (q)
|
bar();
|
bar();
|
}
|
}
|
else
|
else
|
__builtin_trap();
|
__builtin_trap();
|
}
|
}
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.