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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 298 |
Rev 384 |
/* PR middle-end/38533 */
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/* PR middle-end/38533 */
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/* { dg-do compile } */
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/* { dg-do compile } */
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/* { dg-options "-O2 -fdump-tree-reassoc1" } */
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/* { dg-options "-O2 -fdump-tree-reassoc1" } */
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#define A asm volatile ("" : "=r" (f) : "0" (0)); e |= f;
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#define A asm volatile ("" : "=r" (f) : "0" (0)); e |= f;
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#define B A A A A A A A A A A A
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#define B A A A A A A A A A A A
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#define C B B B B B B B B B B B
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#define C B B B B B B B B B B B
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int
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int
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foo (void)
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foo (void)
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{
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{
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int e = 0, f;
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int e = 0, f;
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C C B B B B B A A A A A A
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C C B B B B B A A A A A A
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return e;
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return e;
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}
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}
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int
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int
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main (void)
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main (void)
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{
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{
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if (foo ())
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if (foo ())
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__builtin_abort ();
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__builtin_abort ();
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return 0;
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return 0;
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}
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}
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/* Verify that reassoc hasn't increased register pressure too much
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/* Verify that reassoc hasn't increased register pressure too much
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by moving all bitwise ors after the last __asm__. There should
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by moving all bitwise ors after the last __asm__. There should
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be exactly 2 (first) __asm__ stmts with no intervening stmts,
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be exactly 2 (first) __asm__ stmts with no intervening stmts,
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all others should have some bitwise or in between. */
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all others should have some bitwise or in between. */
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/* { dg-final { scan-tree-dump-times "__asm__\[^;\n]*;\n *__asm__" 1 "reassoc1"} } */
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/* { dg-final { scan-tree-dump-times "__asm__\[^;\n]*;\n *__asm__" 1 "reassoc1"} } */
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/* { dg-final { cleanup-tree-dump "reassoc1" } } */
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/* { dg-final { cleanup-tree-dump "reassoc1" } } */
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