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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 317 |
Rev 384 |
/* Test a situation in which an M5 instruction (mrdacc) and M4 instruction
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/* Test a situation in which an M5 instruction (mrdacc) and M4 instruction
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(mqmulhu) can be issued together. */
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(mqmulhu) can be issued together. */
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/* { dg-options "-mcpu=fr450" } */
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/* { dg-options "-mcpu=fr450" } */
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/* { dg-do run } */
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/* { dg-do run } */
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extern void abort (void);
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extern void abort (void);
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extern void exit (int);
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extern void exit (int);
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int
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int
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main ()
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main ()
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{
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{
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__MQMULHU (0, 0x0011002200330044ULL, 0x0002000300040001ULL);
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__MQMULHU (0, 0x0011002200330044ULL, 0x0002000300040001ULL);
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__MQMULHU (8, 0x0100020003000400ULL, 0x0001000200030004ULL);
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__MQMULHU (8, 0x0100020003000400ULL, 0x0001000200030004ULL);
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/* 0x22 + 0x66 + 0xcc + 0x44 = 0x198 */
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/* 0x22 + 0x66 + 0xcc + 0x44 = 0x198 */
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/* 0x100 + 0x400 + 0x900 + 0x1000 = 0x1e00 */
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/* 0x100 + 0x400 + 0x900 + 0x1000 = 0x1e00 */
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if (__MRDACC (0) + __MRDACC (1)
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if (__MRDACC (0) + __MRDACC (1)
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+ __MRDACC (2) + __MRDACC (3)
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+ __MRDACC (2) + __MRDACC (3)
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+ __MRDACC (8) + __MRDACC (9)
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+ __MRDACC (8) + __MRDACC (9)
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+ __MRDACC (10) + __MRDACC (11) != 0x1f98)
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+ __MRDACC (10) + __MRDACC (11) != 0x1f98)
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abort ();
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abort ();
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exit (0);
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exit (0);
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}
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}
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