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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 318 |
Rev 384 |
/* PR inline-asm/6806 */
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/* PR inline-asm/6806 */
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/* { dg-do run } */
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/* { dg-do run } */
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/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */
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/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */
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/* { dg-options "-O2" } */
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/* { dg-options "-O2" } */
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extern void abort (void);
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extern void abort (void);
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volatile int out = 1;
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volatile int out = 1;
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volatile int a = 2;
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volatile int a = 2;
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volatile int b = 4;
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volatile int b = 4;
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volatile int c = 8;
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volatile int c = 8;
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volatile int d = 16;
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volatile int d = 16;
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volatile int e = 32;
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volatile int e = 32;
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volatile int f = 64;
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volatile int f = 64;
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int
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int
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main ()
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main ()
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{
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{
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asm volatile ("xorl %%eax, %%eax \n\t"
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asm volatile ("xorl %%eax, %%eax \n\t"
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"xorl %%esi, %%esi \n\t"
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"xorl %%esi, %%esi \n\t"
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"addl %1, %0 \n\t"
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"addl %1, %0 \n\t"
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"addl %2, %0 \n\t"
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"addl %2, %0 \n\t"
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"addl %3, %0 \n\t"
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"addl %3, %0 \n\t"
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"addl %4, %0 \n\t"
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"addl %4, %0 \n\t"
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"addl %5, %0 \n\t"
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"addl %5, %0 \n\t"
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"addl %6, %0"
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"addl %6, %0"
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: "+r" (out)
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: "+r" (out)
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: "r" (a), "r" (b), "r" (c), "g" (d), "g" (e), "g" (f)
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: "r" (a), "r" (b), "r" (c), "g" (d), "g" (e), "g" (f)
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: "%eax", "%esi");
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: "%eax", "%esi");
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if (out != 127)
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if (out != 127)
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abort ();
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abort ();
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return 0;
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return 0;
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}
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}
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