URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 318 |
Rev 384 |
/* PR target/40838 */
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/* PR target/40838 */
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/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
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/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
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/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */
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/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */
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/* { dg-require-effective-target sse2 } */
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/* { dg-require-effective-target sse2 } */
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typedef int v4si __attribute__ ((vector_size (16)));
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typedef int v4si __attribute__ ((vector_size (16)));
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extern v4si y(v4si *s3);
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extern v4si y(v4si *s3);
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extern v4si s1, s2;
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extern v4si s1, s2;
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v4si x(void)
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v4si x(void)
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{
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{
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v4si s3 = s1 + s2;
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v4si s3 = s1 + s2;
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return y(&s3);
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return y(&s3);
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}
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}
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/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
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/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
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