URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 322 |
Rev 384 |
/* Test generation of macchwu on 405. */
|
/* Test generation of macchwu on 405. */
|
/* Origin: Joseph Myers <joseph@codesourcery.com> */
|
/* Origin: Joseph Myers <joseph@codesourcery.com> */
|
/* { dg-do compile } */
|
/* { dg-do compile } */
|
/* { dg-require-effective-target ilp32 } */
|
/* { dg-require-effective-target ilp32 } */
|
/* { dg-options "-O2 -mcpu=405" } */
|
/* { dg-options "-O2 -mcpu=405" } */
|
/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
|
/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
|
|
|
/* { dg-final { scan-assembler "macchwu " } } */
|
/* { dg-final { scan-assembler "macchwu " } } */
|
|
|
unsigned int
|
unsigned int
|
f(unsigned int a, unsigned int b, unsigned int c)
|
f(unsigned int a, unsigned int b, unsigned int c)
|
{
|
{
|
a += (unsigned short)b * (c >> 16);
|
a += (unsigned short)b * (c >> 16);
|
return a;
|
return a;
|
}
|
}
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.