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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 384 |
/* Test generation of machhwu. on 405. */
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/* Test generation of machhwu. on 405. */
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/* Origin: Joseph Myers <joseph@codesourcery.com> */
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/* Origin: Joseph Myers <joseph@codesourcery.com> */
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/* { dg-do compile } */
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/* { dg-do compile } */
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/* { dg-require-effective-target ilp32 } */
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/* { dg-require-effective-target ilp32 } */
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/* { dg-options "-O2 -mcpu=405" } */
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/* { dg-options "-O2 -mcpu=405" } */
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/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
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/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
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/* { dg-final { scan-assembler "machhwu\\. " } } */
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/* { dg-final { scan-assembler "machhwu\\. " } } */
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unsigned int
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unsigned int
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f(unsigned int a, unsigned int b, unsigned int c)
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f(unsigned int a, unsigned int b, unsigned int c)
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{
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{
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a += (b >> 16) * (c >> 16);
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a += (b >> 16) * (c >> 16);
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if (!a)
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if (!a)
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return 10;
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return 10;
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return a;
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return a;
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}
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}
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