OpenCores

URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [asm-es-2.c] - Diff between revs 322 and 384

Only display areas with differences | Details | Blame | View Log

Rev 322	Rev 384
`/* { dg-options "-O2" } */`	`/* { dg-options "-O2" } */`
`void`	`void`
`f1 (int *p, int x)`	`f1 (int *p, int x)`
`{`	`{`
`asm ("asm1 %0" : "=es" (p[x]));`	`asm ("asm1 %0" : "=es" (p[x]));`
`}`	`}`

`void`	`void`
`f2 (int *p)`	`f2 (int *p)`
`{`	`{`
`while (1)`	`while (1)`
`{`	`{`
`p += 4;`	`p += 4;`
`asm ("asm2%U0 %0" : "=m" (*p));`	`asm ("asm2%U0 %0" : "=m" (*p));`
`}`	`}`
`}`	`}`

`void`	`void`
`f3 (int *p)`	`f3 (int *p)`
`{`	`{`
`while (1)`	`while (1)`
`{`	`{`
`p += 4;`	`p += 4;`
`asm ("asm3%U0 %0" : "=es" (*p));`	`asm ("asm3%U0 %0" : "=es" (*p));`
`}`	`}`
`}`	`}`

`void`	`void`
`f4 (int *p)`	`f4 (int *p)`
`{`	`{`
`asm ("asm4 %0" : "=es" (p[100]));`	`asm ("asm4 %0" : "=es" (p[100]));`
`}`	`}`

`/* { dg-final { scan-assembler "asm1 3,4" } } */`	`/* { dg-final { scan-assembler "asm1 3,4" } } */`
`/* { dg-final { scan-assembler "asm2u 16\\(3\\)" } } */`	`/* { dg-final { scan-assembler "asm2u 16\\(3\\)" } } */`
`/* { dg-final { scan-assembler "asm3 0\\(3\\)" } } */`	`/* { dg-final { scan-assembler "asm3 0\\(3\\)" } } */`
`/* { dg-final { scan-assembler "asm4 400\\(3\\)" } } */`	`/* { dg-final { scan-assembler "asm4 400\\(3\\)" } } */`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.