/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator.
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/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* This file contains a model of Demon, ARM Ltd's Debug Monitor,
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/* This file contains a model of Demon, ARM Ltd's Debug Monitor,
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including all the SWI's required to support the C library. The code in
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including all the SWI's required to support the C library. The code in
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it is not really for the faint-hearted (especially the abort handling
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it is not really for the faint-hearted (especially the abort handling
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code), but it is a complete example. Defining NOOS will disable all the
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code), but it is a complete example. Defining NOOS will disable all the
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fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
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fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
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0x11 to halt the emulator. */
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0x11 to halt the emulator. */
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#include "config.h"
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#include "config.h"
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#include "ansidecl.h"
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#include "ansidecl.h"
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#include <time.h>
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#include <time.h>
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#include <errno.h>
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#include <errno.h>
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#include <limits.h>
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#include <limits.h>
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#include <string.h>
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#include <string.h>
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#include "targ-vals.h"
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#include "targ-vals.h"
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#ifndef TARGET_O_BINARY
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#ifndef TARGET_O_BINARY
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#define TARGET_O_BINARY 0
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#define TARGET_O_BINARY 0
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#endif
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#endif
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#ifdef HAVE_UNISTD_H
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#ifdef HAVE_UNISTD_H
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#include <unistd.h> /* For SEEK_SET etc. */
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#include <unistd.h> /* For SEEK_SET etc. */
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#endif
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#endif
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#ifdef __riscos
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#ifdef __riscos
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extern int _fisatty (FILE *);
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extern int _fisatty (FILE *);
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#define isatty_(f) _fisatty(f)
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#define isatty_(f) _fisatty(f)
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#else
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#else
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#ifdef __ZTC__
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#ifdef __ZTC__
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#include <io.h>
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#include <io.h>
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#define isatty_(f) isatty((f)->_file)
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#define isatty_(f) isatty((f)->_file)
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#else
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#else
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#ifdef macintosh
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#ifdef macintosh
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#include <ioctl.h>
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#include <ioctl.h>
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#define isatty_(f) (~ioctl ((f)->_file, FIOINTERACTIVE, NULL))
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#define isatty_(f) (~ioctl ((f)->_file, FIOINTERACTIVE, NULL))
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#else
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#else
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#define isatty_(f) isatty (fileno (f))
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#define isatty_(f) isatty (fileno (f))
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#endif
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#endif
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#endif
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#endif
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#endif
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#endif
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#include "armdefs.h"
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#include "armdefs.h"
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#include "armos.h"
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#include "armos.h"
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#include "armemu.h"
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#include "armemu.h"
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#ifndef NOOS
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#ifndef NOOS
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#ifndef VALIDATE
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#ifndef VALIDATE
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/* #ifndef ASIM */
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/* #ifndef ASIM */
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#include "armfpe.h"
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#include "armfpe.h"
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/* #endif */
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/* #endif */
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#endif
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#endif
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#endif
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#endif
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/* For RDIError_BreakpointReached. */
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/* For RDIError_BreakpointReached. */
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#include "dbg_rdi.h"
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#include "dbg_rdi.h"
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#include "gdb/callback.h"
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#include "gdb/callback.h"
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extern host_callback *sim_callback;
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extern host_callback *sim_callback;
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extern unsigned ARMul_OSInit (ARMul_State *);
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extern unsigned ARMul_OSInit (ARMul_State *);
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extern void ARMul_OSExit (ARMul_State *);
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extern void ARMul_OSExit (ARMul_State *);
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extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword);
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extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword);
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extern unsigned ARMul_OSException (ARMul_State *, ARMword, ARMword);
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extern unsigned ARMul_OSException (ARMul_State *, ARMword, ARMword);
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extern ARMword ARMul_OSLastErrorP (ARMul_State *);
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extern ARMword ARMul_OSLastErrorP (ARMul_State *);
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extern ARMword ARMul_Debug (ARMul_State *, ARMword, ARMword);
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extern ARMword ARMul_Debug (ARMul_State *, ARMword, ARMword);
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#define BUFFERSIZE 4096
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#define BUFFERSIZE 4096
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#ifndef FOPEN_MAX
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#ifndef FOPEN_MAX
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#define FOPEN_MAX 64
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#define FOPEN_MAX 64
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#endif
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#endif
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#define UNIQUETEMPS 256
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#define UNIQUETEMPS 256
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#ifndef PATH_MAX
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#ifndef PATH_MAX
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#define PATH_MAX 1024
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#define PATH_MAX 1024
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#endif
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#endif
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/* OS private Information. */
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/* OS private Information. */
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struct OSblock
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struct OSblock
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{
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{
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ARMword Time0;
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ARMword Time0;
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ARMword ErrorP;
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ARMword ErrorP;
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ARMword ErrorNo;
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ARMword ErrorNo;
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FILE *FileTable[FOPEN_MAX];
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FILE *FileTable[FOPEN_MAX];
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char FileFlags[FOPEN_MAX];
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char FileFlags[FOPEN_MAX];
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char *tempnames[UNIQUETEMPS];
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char *tempnames[UNIQUETEMPS];
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};
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};
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#define NOOP 0
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#define NOOP 0
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#define BINARY 1
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#define BINARY 1
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#define READOP 2
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#define READOP 2
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#define WRITEOP 4
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#define WRITEOP 4
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#ifdef macintosh
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#ifdef macintosh
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#define FIXCRLF(t,c) ((t & BINARY) ? \
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#define FIXCRLF(t,c) ((t & BINARY) ? \
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c : \
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c : \
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((c == '\n' || c == '\r' ) ? (c ^ 7) : c) \
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((c == '\n' || c == '\r' ) ? (c ^ 7) : c) \
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)
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)
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#else
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#else
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#define FIXCRLF(t,c) c
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#define FIXCRLF(t,c) c
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#endif
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#endif
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/* Bit mask of enabled SWI implementations. */
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/* Bit mask of enabled SWI implementations. */
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unsigned int swi_mask = -1;
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unsigned int swi_mask = -1;
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static ARMword softvectorcode[] =
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static ARMword softvectorcode[] =
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{
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{
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/* Installed instructions:
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/* Installed instructions:
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swi tidyexception + event;
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swi tidyexception + event;
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mov lr, pc;
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mov lr, pc;
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ldmia fp, {fp, pc};
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ldmia fp, {fp, pc};
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swi generateexception + event. */
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swi generateexception + event. */
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0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
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0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
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0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
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0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
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0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
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0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
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0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
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0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
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0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
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0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
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0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
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0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
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0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
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0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
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0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
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0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
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0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
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0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
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0xe1a0f00e /* Default handler */
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0xe1a0f00e /* Default handler */
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};
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};
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/* Time for the Operating System to initialise itself. */
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/* Time for the Operating System to initialise itself. */
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unsigned
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unsigned
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ARMul_OSInit (ARMul_State * state)
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ARMul_OSInit (ARMul_State * state)
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{
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{
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#ifndef NOOS
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#ifndef NOOS
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#ifndef VALIDATE
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#ifndef VALIDATE
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ARMword instr, i, j;
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ARMword instr, i, j;
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struct OSblock *OSptr = (struct OSblock *) state->OSptr;
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struct OSblock *OSptr = (struct OSblock *) state->OSptr;
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if (state->OSptr == NULL)
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if (state->OSptr == NULL)
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{
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{
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state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
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state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
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if (state->OSptr == NULL)
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if (state->OSptr == NULL)
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{
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{
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perror ("OS Memory");
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perror ("OS Memory");
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exit (15);
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exit (15);
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}
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}
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}
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}
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OSptr = (struct OSblock *) state->OSptr;
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OSptr = (struct OSblock *) state->OSptr;
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OSptr->ErrorP = 0;
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OSptr->ErrorP = 0;
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state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */
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state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */
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ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */
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ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */
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ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */
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ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */
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ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */
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ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */
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ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */
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ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */
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instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */
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instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */
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for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
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for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
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/* Write hardware vectors. */
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/* Write hardware vectors. */
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ARMul_WriteWord (state, i, instr);
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ARMul_WriteWord (state, i, instr);
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SWI_vector_installed = 0;
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SWI_vector_installed = 0;
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for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
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for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
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{
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{
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ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
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ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
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ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
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ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
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SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
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SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
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}
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}
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for (i = 0; i < sizeof (softvectorcode); i += 4)
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for (i = 0; i < sizeof (softvectorcode); i += 4)
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ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
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ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
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for (i = 0; i < FOPEN_MAX; i++)
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for (i = 0; i < FOPEN_MAX; i++)
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OSptr->FileTable[i] = NULL;
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OSptr->FileTable[i] = NULL;
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for (i = 0; i < UNIQUETEMPS; i++)
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for (i = 0; i < UNIQUETEMPS; i++)
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OSptr->tempnames[i] = NULL;
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OSptr->tempnames[i] = NULL;
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ARMul_ConsolePrint (state, ", Demon 1.01");
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ARMul_ConsolePrint (state, ", Demon 1.01");
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/* #ifndef ASIM */
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/* #ifndef ASIM */
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/* Install FPE. */
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/* Install FPE. */
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for (i = 0; i < fpesize; i += 4)
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for (i = 0; i < fpesize; i += 4)
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/* Copy the code. */
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/* Copy the code. */
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ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
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ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
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/* Scan backwards from the end of the code. */
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/* Scan backwards from the end of the code. */
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for (i = FPESTART + fpesize;; i -= 4)
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for (i = FPESTART + fpesize;; i -= 4)
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{
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{
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/* When we reach the marker value, break out of
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/* When we reach the marker value, break out of
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the loop, leaving i pointing at the maker. */
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the loop, leaving i pointing at the maker. */
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if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
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if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
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break;
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break;
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/* If necessary, reverse the error strings. */
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/* If necessary, reverse the error strings. */
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if (state->bigendSig && j < 0x80000000)
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if (state->bigendSig && j < 0x80000000)
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{
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{
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/* It's part of the string so swap it. */
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/* It's part of the string so swap it. */
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j = ((j >> 0x18) & 0x000000ff) |
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j = ((j >> 0x18) & 0x000000ff) |
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((j >> 0x08) & 0x0000ff00) |
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((j >> 0x08) & 0x0000ff00) |
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((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
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((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
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ARMul_WriteWord (state, i, j);
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ARMul_WriteWord (state, i, j);
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}
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}
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}
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}
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/* Copy old illegal instr vector. */
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/* Copy old illegal instr vector. */
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ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
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ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
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/* Install new vector. */
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/* Install new vector. */
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ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
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ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
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ARMul_ConsolePrint (state, ", FPE");
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ARMul_ConsolePrint (state, ", FPE");
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/* #endif ASIM */
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/* #endif ASIM */
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#endif /* VALIDATE */
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#endif /* VALIDATE */
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#endif /* NOOS */
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#endif /* NOOS */
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/* Intel do not want DEMON SWI support. */
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/* Intel do not want DEMON SWI support. */
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if (state->is_XScale)
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if (state->is_XScale)
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swi_mask = SWI_MASK_ANGEL;
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swi_mask = SWI_MASK_ANGEL;
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return TRUE;
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return TRUE;
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}
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}
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void
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void
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ARMul_OSExit (ARMul_State * state)
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ARMul_OSExit (ARMul_State * state)
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{
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{
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free ((char *) state->OSptr);
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free ((char *) state->OSptr);
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}
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}
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/* Return the last Operating System Error. */
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/* Return the last Operating System Error. */
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ARMword ARMul_OSLastErrorP (ARMul_State * state)
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ARMword ARMul_OSLastErrorP (ARMul_State * state)
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{
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{
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return ((struct OSblock *) state->OSptr)->ErrorP;
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return ((struct OSblock *) state->OSptr)->ErrorP;
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}
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}
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static int translate_open_mode[] =
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static int translate_open_mode[] =
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{
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{
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TARGET_O_RDONLY, /* "r" */
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TARGET_O_RDONLY, /* "r" */
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TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */
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TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */
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TARGET_O_RDWR, /* "r+" */
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TARGET_O_RDWR, /* "r+" */
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TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */
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TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */
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TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */
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TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */
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TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */
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TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */
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TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */
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TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */
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TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */
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TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */
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TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */
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TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */
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TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */
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TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */
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TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */
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TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */
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TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */
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TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */
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};
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};
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static void
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static void
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SWIWrite0 (ARMul_State * state, ARMword addr)
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SWIWrite0 (ARMul_State * state, ARMword addr)
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{
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{
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ARMword temp;
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ARMword temp;
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struct OSblock *OSptr = (struct OSblock *) state->OSptr;
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struct OSblock *OSptr = (struct OSblock *) state->OSptr;
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|
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while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
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while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
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{
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{
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char buffer = temp;
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char buffer = temp;
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/* Note - we cannot just cast 'temp' to a (char *) here,
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/* Note - we cannot just cast 'temp' to a (char *) here,
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since on a big-endian host the byte value will end
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since on a big-endian host the byte value will end
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up in the wrong place and a nul character will be printed. */
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up in the wrong place and a nul character will be printed. */
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(void) sim_callback->write_stdout (sim_callback, & buffer, 1);
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(void) sim_callback->write_stdout (sim_callback, & buffer, 1);
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}
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}
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OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
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OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
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}
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}
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static void
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static void
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WriteCommandLineTo (ARMul_State * state, ARMword addr)
|
WriteCommandLineTo (ARMul_State * state, ARMword addr)
|
{
|
{
|
ARMword temp;
|
ARMword temp;
|
char *cptr = state->CommandLine;
|
char *cptr = state->CommandLine;
|
|
|
if (cptr == NULL)
|
if (cptr == NULL)
|
cptr = "\0";
|
cptr = "\0";
|
do
|
do
|
{
|
{
|
temp = (ARMword) * cptr++;
|
temp = (ARMword) * cptr++;
|
ARMul_SafeWriteByte (state, addr++, temp);
|
ARMul_SafeWriteByte (state, addr++, temp);
|
}
|
}
|
while (temp != 0);
|
while (temp != 0);
|
}
|
}
|
|
|
static int
|
static int
|
ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
|
ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
char *p = buf;
|
char *p = buf;
|
|
|
while (n--)
|
while (n--)
|
if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
|
if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
|
return 0;
|
return 0;
|
OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
|
OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
|
state->Reg[0] = -1;
|
state->Reg[0] = -1;
|
return -1;
|
return -1;
|
}
|
}
|
|
|
static void
|
static void
|
SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
|
SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
char buf[PATH_MAX];
|
char buf[PATH_MAX];
|
int flags;
|
int flags;
|
|
|
if (ReadFileName (state, buf, name, sizeof buf) == -1)
|
if (ReadFileName (state, buf, name, sizeof buf) == -1)
|
return;
|
return;
|
|
|
/* Now we need to decode the Demon open mode. */
|
/* Now we need to decode the Demon open mode. */
|
flags = translate_open_mode[SWIflags];
|
flags = translate_open_mode[SWIflags];
|
|
|
/* Filename ":tt" is special: it denotes stdin/out. */
|
/* Filename ":tt" is special: it denotes stdin/out. */
|
if (strcmp (buf, ":tt") == 0)
|
if (strcmp (buf, ":tt") == 0)
|
{
|
{
|
if (flags == TARGET_O_RDONLY) /* opening tty "r" */
|
if (flags == TARGET_O_RDONLY) /* opening tty "r" */
|
state->Reg[0] = 0; /* stdin */
|
state->Reg[0] = 0; /* stdin */
|
else
|
else
|
state->Reg[0] = 1; /* stdout */
|
state->Reg[0] = 1; /* stdout */
|
}
|
}
|
else
|
else
|
{
|
{
|
state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
|
state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
}
|
}
|
|
|
static void
|
static void
|
SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
|
SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
int res;
|
int res;
|
int i;
|
int i;
|
char *local = malloc (len);
|
char *local = malloc (len);
|
|
|
if (local == NULL)
|
if (local == NULL)
|
{
|
{
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback,
|
(sim_callback,
|
"sim: Unable to read 0x%ulx bytes - out of memory\n",
|
"sim: Unable to read 0x%ulx bytes - out of memory\n",
|
len);
|
len);
|
return;
|
return;
|
}
|
}
|
|
|
res = sim_callback->read (sim_callback, f, local, len);
|
res = sim_callback->read (sim_callback, f, local, len);
|
if (res > 0)
|
if (res > 0)
|
for (i = 0; i < res; i++)
|
for (i = 0; i < res; i++)
|
ARMul_SafeWriteByte (state, ptr + i, local[i]);
|
ARMul_SafeWriteByte (state, ptr + i, local[i]);
|
|
|
free (local);
|
free (local);
|
state->Reg[0] = res == -1 ? -1 : len - res;
|
state->Reg[0] = res == -1 ? -1 : len - res;
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
|
|
static void
|
static void
|
SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
|
SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
int res;
|
int res;
|
ARMword i;
|
ARMword i;
|
char *local = malloc (len);
|
char *local = malloc (len);
|
|
|
if (local == NULL)
|
if (local == NULL)
|
{
|
{
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback,
|
(sim_callback,
|
"sim: Unable to write 0x%lx bytes - out of memory\n",
|
"sim: Unable to write 0x%lx bytes - out of memory\n",
|
(long) len);
|
(long) len);
|
return;
|
return;
|
}
|
}
|
|
|
for (i = 0; i < len; i++)
|
for (i = 0; i < len; i++)
|
local[i] = ARMul_SafeReadByte (state, ptr + i);
|
local[i] = ARMul_SafeReadByte (state, ptr + i);
|
|
|
res = sim_callback->write (sim_callback, f, local, len);
|
res = sim_callback->write (sim_callback, f, local, len);
|
state->Reg[0] = res == -1 ? -1 : len - res;
|
state->Reg[0] = res == -1 ? -1 : len - res;
|
free (local);
|
free (local);
|
|
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
|
|
static void
|
static void
|
SWIflen (ARMul_State * state, ARMword fh)
|
SWIflen (ARMul_State * state, ARMword fh)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
ARMword addr;
|
ARMword addr;
|
|
|
if (fh > FOPEN_MAX)
|
if (fh > FOPEN_MAX)
|
{
|
{
|
OSptr->ErrorNo = EBADF;
|
OSptr->ErrorNo = EBADF;
|
state->Reg[0] = -1L;
|
state->Reg[0] = -1L;
|
return;
|
return;
|
}
|
}
|
|
|
addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
|
addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
|
|
|
state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
|
state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
|
(void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
|
(void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
|
|
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
|
|
static void
|
static void
|
SWIremove (ARMul_State * state, ARMword path)
|
SWIremove (ARMul_State * state, ARMword path)
|
{
|
{
|
char buf[PATH_MAX];
|
char buf[PATH_MAX];
|
|
|
if (ReadFileName (state, buf, path, sizeof buf) != -1)
|
if (ReadFileName (state, buf, path, sizeof buf) != -1)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
state->Reg[0] = sim_callback->unlink (sim_callback, buf);
|
state->Reg[0] = sim_callback->unlink (sim_callback, buf);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
}
|
}
|
|
|
static void
|
static void
|
SWIrename (ARMul_State * state, ARMword old, ARMword new)
|
SWIrename (ARMul_State * state, ARMword old, ARMword new)
|
{
|
{
|
char oldbuf[PATH_MAX], newbuf[PATH_MAX];
|
char oldbuf[PATH_MAX], newbuf[PATH_MAX];
|
|
|
if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
|
if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
|
&& ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
|
&& ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
|
{
|
{
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
|
state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
|
state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
}
|
}
|
|
|
/* The emulator calls this routine when a SWI instruction is encuntered.
|
/* The emulator calls this routine when a SWI instruction is encuntered.
|
The parameter passed is the SWI number (lower 24 bits of the instruction). */
|
The parameter passed is the SWI number (lower 24 bits of the instruction). */
|
|
|
unsigned
|
unsigned
|
ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
|
ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
|
{
|
{
|
struct OSblock * OSptr = (struct OSblock *) state->OSptr;
|
struct OSblock * OSptr = (struct OSblock *) state->OSptr;
|
int unhandled = FALSE;
|
int unhandled = FALSE;
|
|
|
switch (number)
|
switch (number)
|
{
|
{
|
case SWI_Read:
|
case SWI_Read:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
|
SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Write:
|
case SWI_Write:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
|
SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Open:
|
case SWI_Open:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIopen (state, state->Reg[0], state->Reg[1]);
|
SWIopen (state, state->Reg[0], state->Reg[1]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Clock:
|
case SWI_Clock:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
/* Return number of centi-seconds. */
|
/* Return number of centi-seconds. */
|
state->Reg[0] =
|
state->Reg[0] =
|
#ifdef CLOCKS_PER_SEC
|
#ifdef CLOCKS_PER_SEC
|
(CLOCKS_PER_SEC >= 100)
|
(CLOCKS_PER_SEC >= 100)
|
? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
|
? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
|
: (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
|
: (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
|
#else
|
#else
|
/* Presume unix... clock() returns microseconds. */
|
/* Presume unix... clock() returns microseconds. */
|
(ARMword) (clock () / 10000);
|
(ARMword) (clock () / 10000);
|
#endif
|
#endif
|
OSptr->ErrorNo = errno;
|
OSptr->ErrorNo = errno;
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Time:
|
case SWI_Time:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
|
state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Close:
|
case SWI_Close:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
|
state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Flen:
|
case SWI_Flen:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIflen (state, state->Reg[0]);
|
SWIflen (state, state->Reg[0]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Exit:
|
case SWI_Exit:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Seek:
|
case SWI_Seek:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
/* We must return non-zero for failure. */
|
/* We must return non-zero for failure. */
|
state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
|
state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_WriteC:
|
case SWI_WriteC:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
char tmp = state->Reg[0];
|
char tmp = state->Reg[0];
|
(void) sim_callback->write_stdout (sim_callback, &tmp, 1);
|
(void) sim_callback->write_stdout (sim_callback, &tmp, 1);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Write0:
|
case SWI_Write0:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIWrite0 (state, state->Reg[0]);
|
SWIWrite0 (state, state->Reg[0]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_GetErrno:
|
case SWI_GetErrno:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
state->Reg[0] = OSptr->ErrorNo;
|
state->Reg[0] = OSptr->ErrorNo;
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_GetEnv:
|
case SWI_GetEnv:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
state->Reg[0] = ADDRCMDLINE;
|
state->Reg[0] = ADDRCMDLINE;
|
if (state->MemSize)
|
if (state->MemSize)
|
state->Reg[1] = state->MemSize;
|
state->Reg[1] = state->MemSize;
|
else
|
else
|
state->Reg[1] = ADDRUSERSTACK;
|
state->Reg[1] = ADDRUSERSTACK;
|
|
|
WriteCommandLineTo (state, state->Reg[0]);
|
WriteCommandLineTo (state, state->Reg[0]);
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Breakpoint:
|
case SWI_Breakpoint:
|
state->EndCondition = RDIError_BreakpointReached;
|
state->EndCondition = RDIError_BreakpointReached;
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
break;
|
break;
|
|
|
case SWI_Remove:
|
case SWI_Remove:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIremove (state, state->Reg[0]);
|
SWIremove (state, state->Reg[0]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_Rename:
|
case SWI_Rename:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
SWIrename (state, state->Reg[0], state->Reg[1]);
|
SWIrename (state, state->Reg[0], state->Reg[1]);
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case SWI_IsTTY:
|
case SWI_IsTTY:
|
if (swi_mask & SWI_MASK_DEMON)
|
if (swi_mask & SWI_MASK_DEMON)
|
{
|
{
|
state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
|
state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
/* Handle Angel SWIs as well as Demon ones. */
|
/* Handle Angel SWIs as well as Demon ones. */
|
case AngelSWI_ARM:
|
case AngelSWI_ARM:
|
case AngelSWI_Thumb:
|
case AngelSWI_Thumb:
|
if (swi_mask & SWI_MASK_ANGEL)
|
if (swi_mask & SWI_MASK_ANGEL)
|
{
|
{
|
ARMword addr;
|
ARMword addr;
|
ARMword temp;
|
ARMword temp;
|
|
|
/* R1 is almost always a parameter block. */
|
/* R1 is almost always a parameter block. */
|
addr = state->Reg[1];
|
addr = state->Reg[1];
|
/* R0 is a reason code. */
|
/* R0 is a reason code. */
|
switch (state->Reg[0])
|
switch (state->Reg[0])
|
{
|
{
|
case -1:
|
case -1:
|
/* This can happen when a SWI is interrupted (eg receiving a
|
/* This can happen when a SWI is interrupted (eg receiving a
|
ctrl-C whilst processing SWIRead()). The SWI will complete
|
ctrl-C whilst processing SWIRead()). The SWI will complete
|
returning -1 in r0 to the caller. If GDB is then used to
|
returning -1 in r0 to the caller. If GDB is then used to
|
resume the system call the reason code will now be -1. */
|
resume the system call the reason code will now be -1. */
|
return TRUE;
|
return TRUE;
|
|
|
/* Unimplemented reason codes. */
|
/* Unimplemented reason codes. */
|
case AngelSWI_Reason_ReadC:
|
case AngelSWI_Reason_ReadC:
|
case AngelSWI_Reason_TmpNam:
|
case AngelSWI_Reason_TmpNam:
|
case AngelSWI_Reason_System:
|
case AngelSWI_Reason_System:
|
case AngelSWI_Reason_EnterSVC:
|
case AngelSWI_Reason_EnterSVC:
|
default:
|
default:
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
return FALSE;
|
return FALSE;
|
|
|
case AngelSWI_Reason_Clock:
|
case AngelSWI_Reason_Clock:
|
/* Return number of centi-seconds. */
|
/* Return number of centi-seconds. */
|
state->Reg[0] =
|
state->Reg[0] =
|
#ifdef CLOCKS_PER_SEC
|
#ifdef CLOCKS_PER_SEC
|
(CLOCKS_PER_SEC >= 100)
|
(CLOCKS_PER_SEC >= 100)
|
? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
|
? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
|
: (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
|
: (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
|
#else
|
#else
|
/* Presume unix... clock() returns microseconds. */
|
/* Presume unix... clock() returns microseconds. */
|
(ARMword) (clock () / 10000);
|
(ARMword) (clock () / 10000);
|
#endif
|
#endif
|
OSptr->ErrorNo = errno;
|
OSptr->ErrorNo = errno;
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Time:
|
case AngelSWI_Reason_Time:
|
state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
|
state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case AngelSWI_Reason_WriteC:
|
case AngelSWI_Reason_WriteC:
|
{
|
{
|
char tmp = ARMul_SafeReadByte (state, addr);
|
char tmp = ARMul_SafeReadByte (state, addr);
|
(void) sim_callback->write_stdout (sim_callback, &tmp, 1);
|
(void) sim_callback->write_stdout (sim_callback, &tmp, 1);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
}
|
}
|
|
|
case AngelSWI_Reason_Write0:
|
case AngelSWI_Reason_Write0:
|
SWIWrite0 (state, addr);
|
SWIWrite0 (state, addr);
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Close:
|
case AngelSWI_Reason_Close:
|
state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
|
state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Seek:
|
case AngelSWI_Reason_Seek:
|
state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
|
state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr + 4),
|
ARMul_ReadWord (state, addr + 4),
|
SEEK_SET);
|
SEEK_SET);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case AngelSWI_Reason_FLen:
|
case AngelSWI_Reason_FLen:
|
SWIflen (state, ARMul_ReadWord (state, addr));
|
SWIflen (state, ARMul_ReadWord (state, addr));
|
break;
|
break;
|
|
|
case AngelSWI_Reason_GetCmdLine:
|
case AngelSWI_Reason_GetCmdLine:
|
WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
|
WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
|
break;
|
break;
|
|
|
case AngelSWI_Reason_HeapInfo:
|
case AngelSWI_Reason_HeapInfo:
|
/* R1 is a pointer to a pointer. */
|
/* R1 is a pointer to a pointer. */
|
addr = ARMul_ReadWord (state, addr);
|
addr = ARMul_ReadWord (state, addr);
|
|
|
/* Pick up the right memory limit. */
|
/* Pick up the right memory limit. */
|
if (state->MemSize)
|
if (state->MemSize)
|
temp = state->MemSize;
|
temp = state->MemSize;
|
else
|
else
|
temp = ADDRUSERSTACK;
|
temp = ADDRUSERSTACK;
|
|
|
ARMul_WriteWord (state, addr, 0); /* Heap base. */
|
ARMul_WriteWord (state, addr, 0); /* Heap base. */
|
ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */
|
ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */
|
ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */
|
ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */
|
ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */
|
ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */
|
break;
|
break;
|
|
|
case AngelSWI_Reason_ReportException:
|
case AngelSWI_Reason_ReportException:
|
if (state->Reg[1] == ADP_Stopped_ApplicationExit)
|
if (state->Reg[1] == ADP_Stopped_ApplicationExit)
|
state->Reg[0] = 0;
|
state->Reg[0] = 0;
|
else
|
else
|
state->Reg[0] = -1;
|
state->Reg[0] = -1;
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
break;
|
break;
|
|
|
case ADP_Stopped_ApplicationExit:
|
case ADP_Stopped_ApplicationExit:
|
state->Reg[0] = 0;
|
state->Reg[0] = 0;
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
break;
|
break;
|
|
|
case ADP_Stopped_RunTimeError:
|
case ADP_Stopped_RunTimeError:
|
state->Reg[0] = -1;
|
state->Reg[0] = -1;
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Errno:
|
case AngelSWI_Reason_Errno:
|
state->Reg[0] = OSptr->ErrorNo;
|
state->Reg[0] = OSptr->ErrorNo;
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Open:
|
case AngelSWI_Reason_Open:
|
SWIopen (state,
|
SWIopen (state,
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr + 4));
|
ARMul_ReadWord (state, addr + 4));
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Read:
|
case AngelSWI_Reason_Read:
|
SWIread (state,
|
SWIread (state,
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr + 4),
|
ARMul_ReadWord (state, addr + 4),
|
ARMul_ReadWord (state, addr + 8));
|
ARMul_ReadWord (state, addr + 8));
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Write:
|
case AngelSWI_Reason_Write:
|
SWIwrite (state,
|
SWIwrite (state,
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr + 4),
|
ARMul_ReadWord (state, addr + 4),
|
ARMul_ReadWord (state, addr + 8));
|
ARMul_ReadWord (state, addr + 8));
|
break;
|
break;
|
|
|
case AngelSWI_Reason_IsTTY:
|
case AngelSWI_Reason_IsTTY:
|
state->Reg[0] = sim_callback->isatty (sim_callback,
|
state->Reg[0] = sim_callback->isatty (sim_callback,
|
ARMul_ReadWord (state, addr));
|
ARMul_ReadWord (state, addr));
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case AngelSWI_Reason_Remove:
|
case AngelSWI_Reason_Remove:
|
SWIremove (state,
|
SWIremove (state,
|
ARMul_ReadWord (state, addr));
|
ARMul_ReadWord (state, addr));
|
|
|
case AngelSWI_Reason_Rename:
|
case AngelSWI_Reason_Rename:
|
SWIrename (state,
|
SWIrename (state,
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr),
|
ARMul_ReadWord (state, addr + 4));
|
ARMul_ReadWord (state, addr + 4));
|
}
|
}
|
}
|
}
|
else
|
else
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
/* The following SWIs are generated by the softvectorcode[]
|
/* The following SWIs are generated by the softvectorcode[]
|
installed by default by the simulator. */
|
installed by default by the simulator. */
|
case 0x91: /* Undefined Instruction. */
|
case 0x91: /* Undefined Instruction. */
|
{
|
{
|
ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
|
ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
|
|
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n",
|
(sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n",
|
ARMul_ReadWord (state, addr), addr);
|
ARMul_ReadWord (state, addr), addr);
|
state->EndCondition = RDIError_SoftwareInterrupt;
|
state->EndCondition = RDIError_SoftwareInterrupt;
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
return FALSE;
|
return FALSE;
|
}
|
}
|
|
|
case 0x90: /* Reset. */
|
case 0x90: /* Reset. */
|
case 0x92: /* SWI. */
|
case 0x92: /* SWI. */
|
/* These two can be safely ignored. */
|
/* These two can be safely ignored. */
|
break;
|
break;
|
|
|
case 0x93: /* Prefetch Abort. */
|
case 0x93: /* Prefetch Abort. */
|
case 0x94: /* Data Abort. */
|
case 0x94: /* Data Abort. */
|
case 0x95: /* Address Exception. */
|
case 0x95: /* Address Exception. */
|
case 0x96: /* IRQ. */
|
case 0x96: /* IRQ. */
|
case 0x97: /* FIQ. */
|
case 0x97: /* FIQ. */
|
case 0x98: /* Error. */
|
case 0x98: /* Error. */
|
unhandled = TRUE;
|
unhandled = TRUE;
|
break;
|
break;
|
|
|
case -1:
|
case -1:
|
/* This can happen when a SWI is interrupted (eg receiving a
|
/* This can happen when a SWI is interrupted (eg receiving a
|
ctrl-C whilst processing SWIRead()). The SWI will complete
|
ctrl-C whilst processing SWIRead()). The SWI will complete
|
returning -1 in r0 to the caller. If GDB is then used to
|
returning -1 in r0 to the caller. If GDB is then used to
|
resume the system call the reason code will now be -1. */
|
resume the system call the reason code will now be -1. */
|
return TRUE;
|
return TRUE;
|
|
|
case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */
|
case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */
|
if (swi_mask & SWI_MASK_REDBOOT)
|
if (swi_mask & SWI_MASK_REDBOOT)
|
{
|
{
|
switch (state->Reg[0])
|
switch (state->Reg[0])
|
{
|
{
|
/* These numbers are defined in libgloss/syscall.h
|
/* These numbers are defined in libgloss/syscall.h
|
but the simulator should not be dependend upon
|
but the simulator should not be dependend upon
|
libgloss being installed. */
|
libgloss being installed. */
|
case 1: /* Exit. */
|
case 1: /* Exit. */
|
state->Emulate = FALSE;
|
state->Emulate = FALSE;
|
/* Copy exit code into r0. */
|
/* Copy exit code into r0. */
|
state->Reg[0] = state->Reg[1];
|
state->Reg[0] = state->Reg[1];
|
break;
|
break;
|
|
|
case 2: /* Open. */
|
case 2: /* Open. */
|
SWIopen (state, state->Reg[1], state->Reg[2]);
|
SWIopen (state, state->Reg[1], state->Reg[2]);
|
break;
|
break;
|
|
|
case 3: /* Close. */
|
case 3: /* Close. */
|
state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
|
state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case 4: /* Read. */
|
case 4: /* Read. */
|
SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
|
SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
|
break;
|
break;
|
|
|
case 5: /* Write. */
|
case 5: /* Write. */
|
SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
|
SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
|
break;
|
break;
|
|
|
case 6: /* Lseek. */
|
case 6: /* Lseek. */
|
state->Reg[0] = sim_callback->lseek (sim_callback,
|
state->Reg[0] = sim_callback->lseek (sim_callback,
|
state->Reg[1],
|
state->Reg[1],
|
state->Reg[2],
|
state->Reg[2],
|
state->Reg[3]);
|
state->Reg[3]);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case 17: /* Utime. */
|
case 17: /* Utime. */
|
state->Reg[0] = (ARMword) sim_callback->time (sim_callback,
|
state->Reg[0] = (ARMword) sim_callback->time (sim_callback,
|
(long *) state->Reg[1]);
|
(long *) state->Reg[1]);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
|
break;
|
break;
|
|
|
case 7: /* Unlink. */
|
case 7: /* Unlink. */
|
case 8: /* Getpid. */
|
case 8: /* Getpid. */
|
case 9: /* Kill. */
|
case 9: /* Kill. */
|
case 10: /* Fstat. */
|
case 10: /* Fstat. */
|
case 11: /* Sbrk. */
|
case 11: /* Sbrk. */
|
case 12: /* Argvlen. */
|
case 12: /* Argvlen. */
|
case 13: /* Argv. */
|
case 13: /* Argv. */
|
case 14: /* ChDir. */
|
case 14: /* ChDir. */
|
case 15: /* Stat. */
|
case 15: /* Stat. */
|
case 16: /* Chmod. */
|
case 16: /* Chmod. */
|
case 18: /* Time. */
|
case 18: /* Time. */
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback,
|
(sim_callback,
|
"sim: unhandled RedBoot syscall `%d' encountered - "
|
"sim: unhandled RedBoot syscall `%d' encountered - "
|
"returning ENOSYS\n",
|
"returning ENOSYS\n",
|
state->Reg[0]);
|
state->Reg[0]);
|
state->Reg[0] = -1;
|
state->Reg[0] = -1;
|
OSptr->ErrorNo = cb_host_to_target_errno
|
OSptr->ErrorNo = cb_host_to_target_errno
|
(sim_callback, ENOSYS);
|
(sim_callback, ENOSYS);
|
break;
|
break;
|
case 1001: /* Meminfo. */
|
case 1001: /* Meminfo. */
|
{
|
{
|
ARMword totmem = state->Reg[1],
|
ARMword totmem = state->Reg[1],
|
topmem = state->Reg[2];
|
topmem = state->Reg[2];
|
ARMword stack = state->MemSize > 0
|
ARMword stack = state->MemSize > 0
|
? state->MemSize : ADDRUSERSTACK;
|
? state->MemSize : ADDRUSERSTACK;
|
if (totmem != 0)
|
if (totmem != 0)
|
ARMul_WriteWord (state, totmem, stack);
|
ARMul_WriteWord (state, totmem, stack);
|
if (topmem != 0)
|
if (topmem != 0)
|
ARMul_WriteWord (state, topmem, stack);
|
ARMul_WriteWord (state, topmem, stack);
|
state->Reg[0] = 0;
|
state->Reg[0] = 0;
|
break;
|
break;
|
}
|
}
|
|
|
default:
|
default:
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback,
|
(sim_callback,
|
"sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
|
"sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
|
state->Reg[0]);
|
state->Reg[0]);
|
return FALSE;
|
return FALSE;
|
}
|
}
|
break;
|
break;
|
}
|
}
|
|
|
default:
|
default:
|
unhandled = TRUE;
|
unhandled = TRUE;
|
}
|
}
|
|
|
if (unhandled)
|
if (unhandled)
|
{
|
{
|
if (SWI_vector_installed)
|
if (SWI_vector_installed)
|
{
|
{
|
ARMword cpsr;
|
ARMword cpsr;
|
ARMword i_size;
|
ARMword i_size;
|
|
|
cpsr = ARMul_GetCPSR (state);
|
cpsr = ARMul_GetCPSR (state);
|
i_size = INSN_SIZE;
|
i_size = INSN_SIZE;
|
|
|
ARMul_SetSPSR (state, SVC32MODE, cpsr);
|
ARMul_SetSPSR (state, SVC32MODE, cpsr);
|
|
|
cpsr &= ~0xbf;
|
cpsr &= ~0xbf;
|
cpsr |= SVC32MODE | 0x80;
|
cpsr |= SVC32MODE | 0x80;
|
ARMul_SetCPSR (state, cpsr);
|
ARMul_SetCPSR (state, cpsr);
|
|
|
state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
|
state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
|
state->NextInstr = RESUME;
|
state->NextInstr = RESUME;
|
state->Reg[15] = state->pc = ARMSWIV;
|
state->Reg[15] = state->pc = ARMSWIV;
|
FLUSHPIPE;
|
FLUSHPIPE;
|
}
|
}
|
else
|
else
|
{
|
{
|
sim_callback->printf_filtered
|
sim_callback->printf_filtered
|
(sim_callback,
|
(sim_callback,
|
"sim: unknown SWI encountered - %x - ignoring\n",
|
"sim: unknown SWI encountered - %x - ignoring\n",
|
number);
|
number);
|
return FALSE;
|
return FALSE;
|
}
|
}
|
}
|
}
|
|
|
return TRUE;
|
return TRUE;
|
}
|
}
|
|
|
#ifndef NOOS
|
#ifndef NOOS
|
#ifndef ASIM
|
#ifndef ASIM
|
|
|
/* The emulator calls this routine when an Exception occurs. The second
|
/* The emulator calls this routine when an Exception occurs. The second
|
parameter is the address of the relevant exception vector. Returning
|
parameter is the address of the relevant exception vector. Returning
|
FALSE from this routine causes the trap to be taken, TRUE causes it to
|
FALSE from this routine causes the trap to be taken, TRUE causes it to
|
be ignored (so set state->Emulate to FALSE!). */
|
be ignored (so set state->Emulate to FALSE!). */
|
|
|
unsigned
|
unsigned
|
ARMul_OSException (ARMul_State * state ATTRIBUTE_UNUSED,
|
ARMul_OSException (ARMul_State * state ATTRIBUTE_UNUSED,
|
ARMword vector ATTRIBUTE_UNUSED,
|
ARMword vector ATTRIBUTE_UNUSED,
|
ARMword pc ATTRIBUTE_UNUSED)
|
ARMword pc ATTRIBUTE_UNUSED)
|
{
|
{
|
return FALSE;
|
return FALSE;
|
}
|
}
|
|
|
#endif
|
#endif
|
#endif /* NOOS */
|
#endif /* NOOS */
|
|
|
