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SIS - Sparc Instruction Simulator README file (v2.0, 05-02-1996)
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SIS - Sparc Instruction Simulator README file (v2.0, 05-02-1996)
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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1. Introduction
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1. Introduction
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The SIS is a SPARC V7 architecture simulator. It consist of two parts,
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The SIS is a SPARC V7 architecture simulator. It consist of two parts,
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the simulator core and a user defined memory module. The simulator
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the simulator core and a user defined memory module. The simulator
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core executes the instructions while the memory module emulates memory
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core executes the instructions while the memory module emulates memory
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and peripherals.
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and peripherals.
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2. Usage
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2. Usage
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The simulator is started as follows:
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The simulator is started as follows:
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sis [-uart1 uart_device1] [-uart2 uart_device2]
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sis [-uart1 uart_device1] [-uart2 uart_device2]
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[-nfp] [-freq frequency] [-c batch_file] [files]
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[-nfp] [-freq frequency] [-c batch_file] [files]
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The default uart devices for SIS are /dev/ptypc and /dev/ptypd. The
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The default uart devices for SIS are /dev/ptypc and /dev/ptypd. The
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-uart[1,2] switch can be used to connect the uarts to other devices.
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-uart[1,2] switch can be used to connect the uarts to other devices.
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Use 'tip /dev/ttypc' to connect a terminal emulator to the uarts.
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Use 'tip /dev/ttypc' to connect a terminal emulator to the uarts.
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The '-nfp' will disable the simulated FPU, so each FPU instruction will
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The '-nfp' will disable the simulated FPU, so each FPU instruction will
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generate a FPU disabled trap. The '-freq' switch can be used to define
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generate a FPU disabled trap. The '-freq' switch can be used to define
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which "frequency" the simulator runs at. This is used by the 'perf'
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which "frequency" the simulator runs at. This is used by the 'perf'
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command to calculated the MIPS figure for a particular configuration.
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command to calculated the MIPS figure for a particular configuration.
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The give frequency must be an integer indicating the frequency in MHz.
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The give frequency must be an integer indicating the frequency in MHz.
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The -c option indicates that sis commands should be read from 'batch_file'
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The -c option indicates that sis commands should be read from 'batch_file'
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at startup.
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at startup.
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Files to be loaded must be in one of the supported formats (see INSTALLATION),
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Files to be loaded must be in one of the supported formats (see INSTALLATION),
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and will be loaded into the simulated memory. The file formats are
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and will be loaded into the simulated memory. The file formats are
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automatically recognised.
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automatically recognised.
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The script 'startsim' will start the simulator in one xterm window and
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The script 'startsim' will start the simulator in one xterm window and
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open a terminal emulator (tip) connected to the UART A in a second
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open a terminal emulator (tip) connected to the UART A in a second
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xterm window. Below is description of commands that are recognized by
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xterm window. Below is description of commands that are recognized by
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the simulator. The command-line is parsed using GNU readline. A command
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the simulator. The command-line is parsed using GNU readline. A command
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history of 64 commands is maintained. Use the up/down arrows to recall
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history of 64 commands is maintained. Use the up/down arrows to recall
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previous commands. For more details, see the readline documentation.
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previous commands. For more details, see the readline documentation.
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batch
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batch
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Execute a batch file of SIS commands.
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Execute a batch file of SIS commands.
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+bp
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+bp
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Adds an breakpoint at address .
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Adds an breakpoint at address .
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bp
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bp
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Prints all breakpoints
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Prints all breakpoints
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-bp
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-bp
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Deletes breakpoint . Use 'bp' to see which number is assigned to the
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Deletes breakpoint . Use 'bp' to see which number is assigned to the
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breakpoints.
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breakpoints.
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cont [inst_count]
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cont [inst_count]
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Continue execution at present position, optionally for [inst_count]
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Continue execution at present position, optionally for [inst_count]
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instructions.
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instructions.
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dis [addr] [count]
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dis [addr] [count]
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Disassemble [count] instructions at address [addr]. Default values for
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Disassemble [count] instructions at address [addr]. Default values for
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count is 16 and addr is the present address.
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count is 16 and addr is the present address.
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echo
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echo
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Print to the simulator window.
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Print to the simulator window.
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float
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float
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Prints the FPU registers
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Prints the FPU registers
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go [inst_count]
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go [inst_count]
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The go command will set pc to and npc to + 4, and start
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The go command will set pc to and npc to + 4, and start
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execution. No other initialisation will be done. If inst_count is given,
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execution. No other initialisation will be done. If inst_count is given,
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execution will stop after the specified number of instructions.
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execution will stop after the specified number of instructions.
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help
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help
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Print a small help menu for the SIS commands.
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Print a small help menu for the SIS commands.
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hist [trace_length]
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hist [trace_length]
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Enable the instruction trace buffer. The 'trace_length' last executed
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Enable the instruction trace buffer. The 'trace_length' last executed
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instructions will be placed in the trace buffer. A 'hist' command without
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instructions will be placed in the trace buffer. A 'hist' command without
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a trace_length will display the trace buffer. Specifying a zero trace
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a trace_length will display the trace buffer. Specifying a zero trace
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length will disable the trace buffer.
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length will disable the trace buffer.
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load
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load
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Loads a file into simulator memory.
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Loads a file into simulator memory.
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mem [addr] [count]
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mem [addr] [count]
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Display memory at [addr] for [count] bytes. Same default values as above.
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Display memory at [addr] for [count] bytes. Same default values as above.
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quit
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quit
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Exits the simulator.
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Exits the simulator.
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perf [reset]
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perf [reset]
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The 'perf' command will display various execution statistics. A 'perf reset'
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The 'perf' command will display various execution statistics. A 'perf reset'
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command will reset the statistics. This can be used if statistics shall
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command will reset the statistics. This can be used if statistics shall
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be calculated only over a part of the program. The 'run' and 'reset'
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be calculated only over a part of the program. The 'run' and 'reset'
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command also resets the statistic information.
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command also resets the statistic information.
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reg [reg_name] [value]
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reg [reg_name] [value]
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Prints and sets the IU regiters. 'reg' without parameters prints the IU
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Prints and sets the IU regiters. 'reg' without parameters prints the IU
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registers. 'reg [reg_name] [value]' sets the corresponding register to
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registers. 'reg [reg_name] [value]' sets the corresponding register to
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[value]. Valid register names are psr, tbr, wim, y, g1-g7, o0-o7 and
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[value]. Valid register names are psr, tbr, wim, y, g1-g7, o0-o7 and
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l0-l7.
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l0-l7.
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reset
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reset
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Performs a power-on reset. This command is equal to 'run 0'.
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Performs a power-on reset. This command is equal to 'run 0'.
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run [inst_count]
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run [inst_count]
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Resets the simulator and starts execution from address 0. If an instruction
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Resets the simulator and starts execution from address 0. If an instruction
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count is given (inst_count), the simulator will stop after the specified
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count is given (inst_count), the simulator will stop after the specified
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number of instructions. The event queue is emptied but any set breakpoints
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number of instructions. The event queue is emptied but any set breakpoints
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remain.
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remain.
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step
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step
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Equal to 'trace 1'
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Equal to 'trace 1'
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tra [inst_count]
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tra [inst_count]
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Starts the simulator at the present position and prints each instruction
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Starts the simulator at the present position and prints each instruction
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it executes. If an instruction count is given (inst_count), the simulator
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it executes. If an instruction count is given (inst_count), the simulator
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will stop after the specified number of instructions.
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will stop after the specified number of instructions.
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Typing a 'Ctrl-C' will interrupt a running simulator.
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Typing a 'Ctrl-C' will interrupt a running simulator.
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Short forms of the commands are allowed, e.g 'c' 'co' or 'con' are all
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Short forms of the commands are allowed, e.g 'c' 'co' or 'con' are all
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interpreted as 'cont'.
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interpreted as 'cont'.
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3. Simulator core
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3. Simulator core
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The SIS emulates the behavior of the 90C601E and 90C602E sparc IU and
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The SIS emulates the behavior of the 90C601E and 90C602E sparc IU and
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FPU from Matra MHS. These are roughly equivalent to the Cypress C601
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FPU from Matra MHS. These are roughly equivalent to the Cypress C601
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and C602. The simulator is cycle true, i.e a simulator time is
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and C602. The simulator is cycle true, i.e a simulator time is
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maintained and inremented according the IU and FPU instruction timing.
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maintained and inremented according the IU and FPU instruction timing.
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The parallel execution between the IU and FPU is modelled, as well as
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The parallel execution between the IU and FPU is modelled, as well as
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stalls due to operand dependencies (FPU). The core interacts with the
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stalls due to operand dependencies (FPU). The core interacts with the
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user-defined memory modules through a number of functions. The memory
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user-defined memory modules through a number of functions. The memory
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module must provide the following functions:
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module must provide the following functions:
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int memory_read(asi,addr,data,ws)
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int memory_read(asi,addr,data,ws)
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int asi;
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int asi;
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unsigned int addr;
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unsigned int addr;
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unsigned int *data;
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unsigned int *data;
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int *ws;
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int *ws;
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int memory_write(asi,addr,data,sz,ws)
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int memory_write(asi,addr,data,sz,ws)
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int asi;
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int asi;
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unsigned int addr;
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unsigned int addr;
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unsigned int *data;
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unsigned int *data;
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int sz;
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int sz;
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int *ws;
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int *ws;
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int sis_memory_read(addr, data, length)
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int sis_memory_read(addr, data, length)
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unsigned int addr;
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unsigned int addr;
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char *data;
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char *data;
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unsigned int length;
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unsigned int length;
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int sis_memory_write(addr, data, length)
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int sis_memory_write(addr, data, length)
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unsigned int addr;
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unsigned int addr;
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char *data;
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char *data;
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unsigned int length;
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unsigned int length;
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int init_sim()
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int init_sim()
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int reset()
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int reset()
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int error_mode(pc)
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int error_mode(pc)
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unsigned int pc;
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unsigned int pc;
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memory_read() is used by the simulator to fetch instructions and
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memory_read() is used by the simulator to fetch instructions and
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operands. The address space identifier (asi) and address is passed as
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operands. The address space identifier (asi) and address is passed as
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parameters. The read data should be assigned to the data pointer
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parameters. The read data should be assigned to the data pointer
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(*data) and the number of waitstate to *ws. 'memory_read' should return
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(*data) and the number of waitstate to *ws. 'memory_read' should return
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0 on success and 1 on failure. A failure will cause a data or
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0 on success and 1 on failure. A failure will cause a data or
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instruction fetch trap. memory_read() always reads one 32-bit word.
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instruction fetch trap. memory_read() always reads one 32-bit word.
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sis_memory_read() is used by the simulator to display and disassemble
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sis_memory_read() is used by the simulator to display and disassemble
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memory contants. The function should copy 'length' bytes of the simulated
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memory contants. The function should copy 'length' bytes of the simulated
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memory starting at 'addr' to '*data'.
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memory starting at 'addr' to '*data'.
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The sis_memory_read() should return 1 on success and 0 on failure.
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The sis_memory_read() should return 1 on success and 0 on failure.
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Failure should only be indicated if access to unimplemented memory is attempted.
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Failure should only be indicated if access to unimplemented memory is attempted.
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memory_write() is used to write to memory. In addition to the asi
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memory_write() is used to write to memory. In addition to the asi
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and address parameters, the size of the written data is given by 'sz'.
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and address parameters, the size of the written data is given by 'sz'.
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The pointer *data points to the data to be written. The 'sz' is coded
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The pointer *data points to the data to be written. The 'sz' is coded
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as follows:
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as follows:
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sz access type
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sz access type
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0 byte
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0 byte
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1 halfword
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1 halfword
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2 word
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2 word
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3 double-word
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3 double-word
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If a double word is written, the most significant word is in data[0] and
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If a double word is written, the most significant word is in data[0] and
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the least significant in data[1].
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the least significant in data[1].
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sis_memory_write() is used by the simulator during loading of programs.
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sis_memory_write() is used by the simulator during loading of programs.
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The function should copy 'length' bytes from *data to the simulated
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The function should copy 'length' bytes from *data to the simulated
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memory starting at 'addr'. sis_memory_write() should return 1 on
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memory starting at 'addr'. sis_memory_write() should return 1 on
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success and 0 on failure. Failure should only be indicated if access
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success and 0 on failure. Failure should only be indicated if access
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to unimplemented memory is attempted. See erc32.c for more details
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to unimplemented memory is attempted. See erc32.c for more details
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on how to define the memory emulation functions.
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on how to define the memory emulation functions.
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The 'init_sim' is called once when the simulator is started. This function
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The 'init_sim' is called once when the simulator is started. This function
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should be used to perform initialisations of user defined memory or
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should be used to perform initialisations of user defined memory or
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peripherals that only have to be done once, such as opening files etc.
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peripherals that only have to be done once, such as opening files etc.
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The 'reset' is called every time the simulator is reset, i.e. when a
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The 'reset' is called every time the simulator is reset, i.e. when a
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'run' command is given. This function should be used to simulate a power
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'run' command is given. This function should be used to simulate a power
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on reset of memory and peripherals.
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on reset of memory and peripherals.
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error_mode() is called by the simulator when the IU goes into error mode,
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error_mode() is called by the simulator when the IU goes into error mode,
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typically if a trap is caused when traps are disabled. The memory module
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typically if a trap is caused when traps are disabled. The memory module
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can then take actions, such as issue a reset.
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can then take actions, such as issue a reset.
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sys_reset() can be called by the memory module to reset the simulator. A
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sys_reset() can be called by the memory module to reset the simulator. A
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reset will empty the event queue and perform a power-on reset.
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reset will empty the event queue and perform a power-on reset.
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4. Events and interrupts
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4. Events and interrupts
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The simulator supports an event queue and the generation of processor
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The simulator supports an event queue and the generation of processor
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interrupts. The following functions are available to the user-defined
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interrupts. The following functions are available to the user-defined
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memory module:
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memory module:
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event(cfunc,arg,delta)
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event(cfunc,arg,delta)
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void (*cfunc)();
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void (*cfunc)();
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int arg;
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int arg;
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unsigned int delta;
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unsigned int delta;
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set_int(level,callback,arg)
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set_int(level,callback,arg)
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int level;
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int level;
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void (*callback)();
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void (*callback)();
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int arg;
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int arg;
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clear_int(level)
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clear_int(level)
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int level;
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int level;
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sim_stop()
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sim_stop()
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The 'event' functions will schedule the execution of the function 'cfunc'
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The 'event' functions will schedule the execution of the function 'cfunc'
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at time 'now + delta' clock cycles. The parameter 'arg' is passed as a
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at time 'now + delta' clock cycles. The parameter 'arg' is passed as a
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parameter to 'cfunc'.
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parameter to 'cfunc'.
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The 'set_int' function set the processor interrupt 'level'. When the interrupt
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The 'set_int' function set the processor interrupt 'level'. When the interrupt
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is taken, the function 'callback' is called with the argument 'arg'. This
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is taken, the function 'callback' is called with the argument 'arg'. This
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will also clear the interrupt. An interrupt can be cleared before it is
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will also clear the interrupt. An interrupt can be cleared before it is
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taken by calling 'clear_int' with the appropriate interrupt level.
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taken by calling 'clear_int' with the appropriate interrupt level.
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The sim_stop function is called each time the simulator stops execution.
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The sim_stop function is called each time the simulator stops execution.
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It can be used to flush buffered devices to get a clean state during
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It can be used to flush buffered devices to get a clean state during
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single stepping etc.
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single stepping etc.
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See 'erc32.c' for examples on how to use events and interrupts.
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See 'erc32.c' for examples on how to use events and interrupts.
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5. Memory module
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5. Memory module
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The supplied memory module (erc32.c) emulates the functions of memory and
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The supplied memory module (erc32.c) emulates the functions of memory and
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the MEC asic developed for the 90C601/2. It includes the following functions:
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the MEC asic developed for the 90C601/2. It includes the following functions:
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* UART A & B
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* UART A & B
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* Real-time clock
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* Real-time clock
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* General purpose timer
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* General purpose timer
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* Interrupt controller
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* Interrupt controller
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* Breakpoint register
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* Breakpoint register
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* Watchpoint register
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* Watchpoint register
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* 512 Kbyte ROM
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* 512 Kbyte ROM
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* 4 Mbyte RAM
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* 4 Mbyte RAM
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See README.erc32 on how the MEC functions are emulated. For a detailed MEC
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See README.erc32 on how the MEC functions are emulated. For a detailed MEC
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specification, look at the ERC32 home page at URL:
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specification, look at the ERC32 home page at URL:
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http://www.estec.esa.nl/wsmwww/erc32
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http://www.estec.esa.nl/wsmwww/erc32
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6. Compile and linking programs
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6. Compile and linking programs
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The directory 'examples' contain some code fragments for SIS.
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The directory 'examples' contain some code fragments for SIS.
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The script gccx indicates how the native sunos gcc and linker can be used
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The script gccx indicates how the native sunos gcc and linker can be used
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to produce executables for the simulator. To compile and link the provided
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to produce executables for the simulator. To compile and link the provided
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'hello.c', type 'gccx hello.c'. This will build the executable 'hello'.
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'hello.c', type 'gccx hello.c'. This will build the executable 'hello'.
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Start the simulator by running 'startsim hello', and issue the command 'run.
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Start the simulator by running 'startsim hello', and issue the command 'run.
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After the program is terminated, the IU will be force to error mode through
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After the program is terminated, the IU will be force to error mode through
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a software trap and halt.
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a software trap and halt.
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The programs are linked with a start-up file, srt0.S. This file includes
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The programs are linked with a start-up file, srt0.S. This file includes
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the traptable and window underflow/overflow trap routines.
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the traptable and window underflow/overflow trap routines.
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7. IU and FPU instruction timing.
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7. IU and FPU instruction timing.
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The simulator provides cycle true simulation. The following table shows
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The simulator provides cycle true simulation. The following table shows
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the emulated instruction timing for 90C601E & 90C602E:
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the emulated instruction timing for 90C601E & 90C602E:
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Instructions Cycles
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Instructions Cycles
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jmpl, rett 2
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jmpl, rett 2
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load 2
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load 2
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store 3
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store 3
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load double 3
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load double 3
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store double 4
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store double 4
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other integer ops 1
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other integer ops 1
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fabs 2
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fabs 2
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fadds 4
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fadds 4
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faddd 4
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faddd 4
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fcmps 4
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fcmps 4
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fcmpd 4
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fcmpd 4
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fdivs 20
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fdivs 20
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fdivd 35
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fdivd 35
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fmovs 2
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fmovs 2
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fmuls 5
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fmuls 5
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fmuld 9
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fmuld 9
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fnegs 2
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fnegs 2
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fsqrts 37
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fsqrts 37
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fsqrtd 65
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fsqrtd 65
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fsubs 4
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fsubs 4
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fsubd 4
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fsubd 4
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fdtoi 7
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fdtoi 7
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fdots 3
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fdots 3
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fitos 6
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fitos 6
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fitod 6
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fitod 6
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fstoi 6
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fstoi 6
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fstod 2
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fstod 2
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The parallel operation between the IU and FPU is modelled. This means
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The parallel operation between the IU and FPU is modelled. This means
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that a FPU instruction will execute in parallel with other instructions as
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that a FPU instruction will execute in parallel with other instructions as
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long as no data or resource dependency is detected. See the 90C602E data
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long as no data or resource dependency is detected. See the 90C602E data
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sheet for the various types of dependencies. Tracing using the 'trace'
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sheet for the various types of dependencies. Tracing using the 'trace'
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command will display the current simulator time in the left column. This
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command will display the current simulator time in the left column. This
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time indicates when the instruction is fetched. If a dependency is detetected,
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time indicates when the instruction is fetched. If a dependency is detetected,
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the following fetch will be delayed until the conflict is resolved.
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the following fetch will be delayed until the conflict is resolved.
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The load dependency in the 90C601E is also modelled - if the destination
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The load dependency in the 90C601E is also modelled - if the destination
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register of a load instruction is used by the following instruction, an
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register of a load instruction is used by the following instruction, an
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idle cycle is inserted.
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idle cycle is inserted.
|
|
|
8. FPU implementation
|
8. FPU implementation
|
|
|
The simulator maps floating-point operations on the hosts floating point
|
The simulator maps floating-point operations on the hosts floating point
|
capabilities. This means that accuracy and generation of IEEE exceptions is
|
capabilities. This means that accuracy and generation of IEEE exceptions is
|
host dependent.
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host dependent.
|
|
|
