/* Altivec expression macros, for PSIM, the PowerPC simulator.
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/* Altivec expression macros, for PSIM, the PowerPC simulator.
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Copyright 2003, 2007, 2008 Free Software Foundation, Inc.
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Copyright 2003, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Red Hat Inc; developed under contract from Motorola.
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Contributed by Red Hat Inc; developed under contract from Motorola.
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Written by matthew green <mrg@redhat.com>.
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Written by matthew green <mrg@redhat.com>.
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This file is part of GDB.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* AltiVec macro helpers. */
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/* AltiVec macro helpers. */
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#define ALTIVEC_SET_CR6(vS, checkone) \
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#define ALTIVEC_SET_CR6(vS, checkone) \
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do { \
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do { \
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if (checkone && ((*vS).w[0] == 0xffffffff && \
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if (checkone && ((*vS).w[0] == 0xffffffff && \
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(*vS).w[1] == 0xffffffff && \
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(*vS).w[1] == 0xffffffff && \
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(*vS).w[2] == 0xffffffff && \
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(*vS).w[2] == 0xffffffff && \
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(*vS).w[3] == 0xffffffff)) \
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(*vS).w[3] == 0xffffffff)) \
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CR_SET(6, 1 << 3); \
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CR_SET(6, 1 << 3); \
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else if ((*vS).w[0] == 0 && \
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else if ((*vS).w[0] == 0 && \
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(*vS).w[1] == 0 && \
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(*vS).w[1] == 0 && \
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(*vS).w[2] == 0 && \
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(*vS).w[2] == 0 && \
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(*vS).w[3] == 0) \
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(*vS).w[3] == 0) \
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CR_SET(6, 1 << 1); \
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CR_SET(6, 1 << 1); \
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else \
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else \
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CR_SET(6, 0); \
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CR_SET(6, 0); \
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} while (0)
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} while (0)
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#define VSCR_SAT 0x00000001
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#define VSCR_SAT 0x00000001
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#define VSCR_NJ 0x00010000
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#define VSCR_NJ 0x00010000
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#define ALTIVEC_SET_SAT(sat) \
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#define ALTIVEC_SET_SAT(sat) \
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do { \
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do { \
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if (sat) \
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if (sat) \
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VSCR |= VSCR_SAT; \
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VSCR |= VSCR_SAT; \
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} while (0)
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} while (0)
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