URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [d10v-elf/] [t-dbt.s] - Diff between revs 24 and 157

Rev 24	Rev 157
`.include "t-macros.i"`	`.include "t-macros.i"`

`start`	`start`

`PSW_BITS = PSW_DM`	`PSW_BITS = PSW_DM`

`;;; Blat our DMAP registers so that they point at on-chip imem`	`;;; Blat our DMAP registers so that they point at on-chip imem`

`ldi r2, MAP_INSN \| 0xf`	`ldi r2, MAP_INSN \| 0xf`
`st r2, @(DMAP_REG,r0)`	`st r2, @(DMAP_REG,r0)`
`ldi r2, MAP_INSN`	`ldi r2, MAP_INSN`
`st r2, @(IMAP1_REG,r0)`	`st r2, @(IMAP1_REG,r0)`

`;;; Patch the interrupt vector's dbt entry with a jmp to success`	`;;; Patch the interrupt vector's dbt entry with a jmp to success`

`ldi r4, #trap`	`ldi r4, #trap`
`ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE`	`ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE`
`ld2w r2, @(0,r4)`	`ld2w r2, @(0,r4)`
`st2w r2, @(0,r5)`	`st2w r2, @(0,r5)`
`ld2w r2, @(4,r4)`	`ld2w r2, @(4,r4)`
`st2w r2, @(4,r5)`	`st2w r2, @(4,r5)`

`test_dbt:`	`test_dbt:`
`dbt -> nop`	`dbt -> nop`
`exit47`	`exit47`

`success:`	`success:`
`checkpsw2 1 PSW_BITS`	`checkpsw2 1 PSW_BITS`
`exit0`	`exit0`

`.data`	`.data`
`trap: ldi r1, success@word`	`trap: ldi r1, success@word`
`jmp r1`	`jmp r1`