URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 157 |
Rev 223 |
# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK
|
# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK
|
# mach: xscale
|
# mach: xscale
|
# as: -mcpu=xscale+iwmmxt
|
# as: -mcpu=xscale+iwmmxt
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
|
|
.global tmovmsk
|
.global tmovmsk
|
tmovmsk:
|
tmovmsk:
|
# Enable access to CoProcessors 0 & 1 before
|
# Enable access to CoProcessors 0 & 1 before
|
# we attempt these instructions.
|
# we attempt these instructions.
|
|
|
mvi_h_gr r1, 3
|
mvi_h_gr r1, 3
|
mcr p15, 0, r1, cr15, cr1, 0
|
mcr p15, 0, r1, cr15, cr1, 0
|
|
|
# Test Byte Wide Mask Transfer
|
# Test Byte Wide Mask Transfer
|
|
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r2, 0
|
mvi_h_gr r2, 0
|
|
|
tmcrr wr0, r0, r1
|
tmcrr wr0, r0, r1
|
|
|
tmovmskb r2, wr0
|
tmovmskb r2, wr0
|
|
|
tmrrc r0, r1, wr0
|
tmrrc r0, r1, wr0
|
|
|
test_h_gr r0, 0x12345678
|
test_h_gr r0, 0x12345678
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r2, 0x000000f0
|
test_h_gr r2, 0x000000f0
|
|
|
# Test Half Word Wide Mask Transfer
|
# Test Half Word Wide Mask Transfer
|
|
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r2, 0
|
mvi_h_gr r2, 0
|
|
|
tmcrr wr0, r0, r1
|
tmcrr wr0, r0, r1
|
|
|
tmovmskh r2, wr0
|
tmovmskh r2, wr0
|
|
|
tmrrc r0, r1, wr0
|
tmrrc r0, r1, wr0
|
|
|
test_h_gr r0, 0x12345678
|
test_h_gr r0, 0x12345678
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r2, 0x0000000c
|
test_h_gr r2, 0x0000000c
|
|
|
# Test Word Wide Mask Transfer
|
# Test Word Wide Mask Transfer
|
|
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r2, 0
|
mvi_h_gr r2, 0
|
|
|
tmcrr wr0, r0, r1
|
tmcrr wr0, r0, r1
|
|
|
tmovmskw r2, wr0
|
tmovmskw r2, wr0
|
|
|
tmrrc r0, r1, wr0
|
tmrrc r0, r1, wr0
|
|
|
test_h_gr r0, 0x12345678
|
test_h_gr r0, 0x12345678
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r2, 0x00000002
|
test_h_gr r2, 0x00000002
|
|
|
pass
|
pass
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.