# Intel(r) Wireless MMX(tm) technology testcase for WADD
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# Intel(r) Wireless MMX(tm) technology testcase for WADD
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# mach: xscale
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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# as: -mcpu=xscale+iwmmxt
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global wadd
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.global wadd
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wadd:
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wadd:
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# Enable access to CoProcessors 0 & 1 before
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# Enable access to CoProcessors 0 & 1 before
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# we attempt these instructions.
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# we attempt these instructions.
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mvi_h_gr r1, 3
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mvi_h_gr r1, 3
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mcr p15, 0, r1, cr15, cr1, 0
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mcr p15, 0, r1, cr15, cr1, 0
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# Test UnSaturated Byte Addition
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# Test UnSaturated Byte Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddb wr2, wr0, wr1
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waddb wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test Unsigned Saturated Byte Addition
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# Test Unsigned Saturated Byte Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddbus wr2, wr0, wr1
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waddbus wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test Signed Saturated Byte Addition
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# Test Signed Saturated Byte Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddbss wr2, wr0, wr1
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waddbss wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x2345677f
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test_h_gr r4, 0x2345677f
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test UnSaturated Halfword Addition
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# Test UnSaturated Halfword Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddh wr2, wr0, wr1
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waddh wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test Unsigned Saturated Halfword Addition
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# Test Unsigned Saturated Halfword Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddhus wr2, wr0, wr1
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waddhus wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test Signed Saturated Halfword Addition
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# Test Signed Saturated Halfword Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddhss wr2, wr0, wr1
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waddhss wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test UnSaturated Word Addition
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# Test UnSaturated Word Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddw wr2, wr0, wr1
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waddw wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test Unsigned Saturated Word Addition
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# Test Unsigned Saturated Word Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddwus wr2, wr0, wr1
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waddwus wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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# Test Signed Saturated Word Addition
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# Test Signed Saturated Word Addition
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r1, 0x9abcde00
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r3, 0x11111111
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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waddwss wr2, wr0, wr1
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waddwss wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcde00
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test_h_gr r1, 0x9abcde00
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r3, 0x11111111
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test_h_gr r4, 0x23456789
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test_h_gr r4, 0x23456789
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test_h_gr r5, 0xabcdef11
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test_h_gr r5, 0xabcdef11
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pass
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pass
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