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Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmax.cgs] - Diff between revs 24 and 157

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Rev 24	Rev 157
`# Intel(r) Wireless MMX(tm) technology testcase for WMAX`	`# Intel(r) Wireless MMX(tm) technology testcase for WMAX`
`# mach: xscale`	`# mach: xscale`
`# as: -mcpu=xscale+iwmmxt`	`# as: -mcpu=xscale+iwmmxt`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global wmax`	`.global wmax`
`wmax:`	`wmax:`
`# Enable access to CoProcessors 0 & 1 before`	`# Enable access to CoProcessors 0 & 1 before`
`# we attempt these instructions.`	`# we attempt these instructions.`

`mvi_h_gr r1, 3`	`mvi_h_gr r1, 3`
`mcr p15, 0, r1, cr15, cr1, 0`	`mcr p15, 0, r1, cr15, cr1, 0`

`# Test Unsigned Byte Maximum`	`# Test Unsigned Byte Maximum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmaxub wr2, wr0, wr1`	`wmaxub wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x12345678`	`test_h_gr r4, 0x12345678`
`test_h_gr r5, 0x9abcde11`	`test_h_gr r5, 0x9abcde11`

`# Test Signed Byte Maximum`	`# Test Signed Byte Maximum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmaxsb wr2, wr0, wr1`	`wmaxsb wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x12345678`	`test_h_gr r4, 0x12345678`
`test_h_gr r5, 0x11111111`	`test_h_gr r5, 0x11111111`

`# Test Unsigned Halfword Maximum`	`# Test Unsigned Halfword Maximum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmaxuh wr2, wr0, wr1`	`wmaxuh wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x12345678`	`test_h_gr r4, 0x12345678`
`test_h_gr r5, 0x9abcde00`	`test_h_gr r5, 0x9abcde00`

`# Test Signed Halfword Maximum`	`# Test Signed Halfword Maximum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmaxsh wr2, wr0, wr1`	`wmaxsh wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x12345678`	`test_h_gr r4, 0x12345678`
`test_h_gr r5, 0x11111111`	`test_h_gr r5, 0x11111111`

`# Test Unsigned Word Maximum`	`# Test Unsigned Word Maximum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmaxuw wr2, wr0, wr1`	`wmaxuw wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x12345678`	`test_h_gr r4, 0x12345678`
`test_h_gr r5, 0x9abcde00`	`test_h_gr r5, 0x9abcde00`

`# Test Signed Word Maximum`	`# Test Signed Word Maximum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmaxsw wr2, wr0, wr1`	`wmaxsw wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x12345678`	`test_h_gr r4, 0x12345678`
`test_h_gr r5, 0x11111111`	`test_h_gr r5, 0x11111111`

`pass`	`pass`

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Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmax.cgs] - Diff between revs 24 and 157