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Rev 223 |
# Intel(r) Wireless MMX(tm) technology testcase for WROR
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# Intel(r) Wireless MMX(tm) technology testcase for WROR
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# mach: xscale
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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# as: -mcpu=xscale+iwmmxt
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global wror
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.global wror
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wror:
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wror:
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# Enable access to CoProcessors 0 & 1 before
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# Enable access to CoProcessors 0 & 1 before
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# we attempt these instructions.
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# we attempt these instructions.
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mvi_h_gr r1, 3
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mvi_h_gr r1, 3
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mcr p15, 0, r1, cr15, cr1, 0
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mcr p15, 0, r1, cr15, cr1, 0
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# Test Halfword wide rotate right by register
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# Test Halfword wide rotate right by register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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wrorh wr2, wr0, wr1
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wrorh wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0x091a2b3c
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test_h_gr r4, 0x091a2b3c
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test_h_gr r5, 0x4d5e6f78
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test_h_gr r5, 0x4d5e6f78
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# Test Halfword wide rotate right by CG register
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# Test Halfword wide rotate right by CG register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcr wcgr0, r2
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tmcr wcgr0, r2
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wrorhg wr1, wr0, wcgr0
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wrorhg wr1, wr0, wcgr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrc r2, wcgr0
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tmrc r2, wcgr0
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tmrrc r3, r4, wr2
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tmrrc r3, r4, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x091a2b3c
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test_h_gr r3, 0x091a2b3c
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test_h_gr r4, 0x4d5e6f78
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test_h_gr r4, 0x4d5e6f78
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# Test Word wide rotate right by register
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# Test Word wide rotate right by register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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wrorw wr2, wr0, wr1
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wrorw wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0x2b3c091a
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test_h_gr r4, 0x2b3c091a
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test_h_gr r5, 0x6f784d5e
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test_h_gr r5, 0x6f784d5e
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# Test Word wide rotate right by CG register
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# Test Word wide rotate right by CG register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcr wcgr0, r2
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tmcr wcgr0, r2
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wrorwg wr1, wr0, wcgr0
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wrorwg wr1, wr0, wcgr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrc r2, wcgr0
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tmrc r2, wcgr0
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tmrrc r3, r4, wr2
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tmrrc r3, r4, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x2b3c091a
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test_h_gr r3, 0x2b3c091a
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test_h_gr r4, 0x6f784d5e
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test_h_gr r4, 0x6f784d5e
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# Test Double Word wide rotate right by register
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# Test Double Word wide rotate right by register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r3, 0x00000000
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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mvi_h_gr r5, 0
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mvi_h_gr r5, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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tmcrr wr2, r4, r5
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tmcrr wr2, r4, r5
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wrord wr2, wr0, wr1
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wrord wr2, wr0, wr1
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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tmrrc r4, r5, wr2
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tmrrc r4, r5, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x00000000
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test_h_gr r3, 0x00000000
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test_h_gr r4, 0x6f78091a
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test_h_gr r4, 0x6f78091a
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test_h_gr r5, 0x2b3c4d5e
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test_h_gr r5, 0x2b3c4d5e
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# Test Double Word wide rotate right by CG register
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# Test Double Word wide rotate right by CG register
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r2, 0x11111111
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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mvi_h_gr r4, 0
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mvi_h_gr r4, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcr wcgr0, r2
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tmcr wcgr0, r2
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wrordg wr1, wr0, wcgr0
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wrordg wr1, wr0, wcgr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrc r2, wcgr0
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tmrc r2, wcgr0
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tmrrc r3, r4, wr2
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tmrrc r3, r4, wr2
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x11111111
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test_h_gr r2, 0x11111111
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test_h_gr r3, 0x6f78091a
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test_h_gr r3, 0x6f78091a
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test_h_gr r4, 0x2b3c4d5e
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test_h_gr r4, 0x2b3c4d5e
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pass
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pass
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