URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 157 |
Rev 223 |
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH
|
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH
|
# mach: xscale
|
# mach: xscale
|
# as: -mcpu=xscale+iwmmxt
|
# as: -mcpu=xscale+iwmmxt
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
|
|
.global wunpckih
|
.global wunpckih
|
wunpckih:
|
wunpckih:
|
# Enable access to CoProcessors 0 & 1 before
|
# Enable access to CoProcessors 0 & 1 before
|
# we attempt these instructions.
|
# we attempt these instructions.
|
|
|
mvi_h_gr r1, 3
|
mvi_h_gr r1, 3
|
mcr p15, 0, r1, cr15, cr1, 0
|
mcr p15, 0, r1, cr15, cr1, 0
|
|
|
# Test Byte unpacking
|
# Test Byte unpacking
|
|
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r2, 0x11111111
|
mvi_h_gr r2, 0x11111111
|
mvi_h_gr r3, 0x00000000
|
mvi_h_gr r3, 0x00000000
|
mvi_h_gr r4, 0
|
mvi_h_gr r4, 0
|
mvi_h_gr r5, 0
|
mvi_h_gr r5, 0
|
|
|
tmcrr wr0, r0, r1
|
tmcrr wr0, r0, r1
|
tmcrr wr1, r2, r3
|
tmcrr wr1, r2, r3
|
tmcrr wr2, r4, r5
|
tmcrr wr2, r4, r5
|
|
|
wunpckihb wr2, wr0, wr1
|
wunpckihb wr2, wr0, wr1
|
|
|
tmrrc r0, r1, wr0
|
tmrrc r0, r1, wr0
|
tmrrc r2, r3, wr1
|
tmrrc r2, r3, wr1
|
tmrrc r4, r5, wr2
|
tmrrc r4, r5, wr2
|
|
|
test_h_gr r0, 0x12345678
|
test_h_gr r0, 0x12345678
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r2, 0x11111111
|
test_h_gr r2, 0x11111111
|
test_h_gr r3, 0x00000000
|
test_h_gr r3, 0x00000000
|
test_h_gr r4, 0x00de00f0
|
test_h_gr r4, 0x00de00f0
|
test_h_gr r5, 0x009a00bc
|
test_h_gr r5, 0x009a00bc
|
|
|
# Test Halfword unpacking
|
# Test Halfword unpacking
|
|
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r2, 0x11111111
|
mvi_h_gr r2, 0x11111111
|
mvi_h_gr r3, 0x00000000
|
mvi_h_gr r3, 0x00000000
|
mvi_h_gr r4, 0
|
mvi_h_gr r4, 0
|
mvi_h_gr r5, 0
|
mvi_h_gr r5, 0
|
|
|
tmcrr wr0, r0, r1
|
tmcrr wr0, r0, r1
|
tmcrr wr1, r2, r3
|
tmcrr wr1, r2, r3
|
tmcrr wr2, r4, r5
|
tmcrr wr2, r4, r5
|
|
|
wunpckihh wr2, wr0, wr1
|
wunpckihh wr2, wr0, wr1
|
|
|
tmrrc r0, r1, wr0
|
tmrrc r0, r1, wr0
|
tmrrc r2, r3, wr1
|
tmrrc r2, r3, wr1
|
tmrrc r4, r5, wr2
|
tmrrc r4, r5, wr2
|
|
|
test_h_gr r0, 0x12345678
|
test_h_gr r0, 0x12345678
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r2, 0x11111111
|
test_h_gr r2, 0x11111111
|
test_h_gr r3, 0x00000000
|
test_h_gr r3, 0x00000000
|
test_h_gr r4, 0x0000def0
|
test_h_gr r4, 0x0000def0
|
test_h_gr r5, 0x00009abc
|
test_h_gr r5, 0x00009abc
|
|
|
# Test Word unpacking
|
# Test Word unpacking
|
|
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r0, 0x12345678
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r1, 0x9abcdef0
|
mvi_h_gr r2, 0x11111111
|
mvi_h_gr r2, 0x11111111
|
mvi_h_gr r3, 0x00000000
|
mvi_h_gr r3, 0x00000000
|
mvi_h_gr r4, 0
|
mvi_h_gr r4, 0
|
mvi_h_gr r5, 0
|
mvi_h_gr r5, 0
|
|
|
tmcrr wr0, r0, r1
|
tmcrr wr0, r0, r1
|
tmcrr wr1, r2, r3
|
tmcrr wr1, r2, r3
|
tmcrr wr2, r4, r5
|
tmcrr wr2, r4, r5
|
|
|
wunpckihw wr2, wr0, wr1
|
wunpckihw wr2, wr0, wr1
|
|
|
tmrrc r0, r1, wr0
|
tmrrc r0, r1, wr0
|
tmrrc r2, r3, wr1
|
tmrrc r2, r3, wr1
|
tmrrc r4, r5, wr2
|
tmrrc r4, r5, wr2
|
|
|
test_h_gr r0, 0x12345678
|
test_h_gr r0, 0x12345678
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r1, 0x9abcdef0
|
test_h_gr r2, 0x11111111
|
test_h_gr r2, 0x11111111
|
test_h_gr r3, 0x00000000
|
test_h_gr r3, 0x00000000
|
test_h_gr r4, 0x9abcdef0
|
test_h_gr r4, 0x9abcdef0
|
test_h_gr r5, 0x00000000
|
test_h_gr r5, 0x00000000
|
|
|
pass
|
pass
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.