URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 223 |
# arm testcase for teq${cond}${set-cc?} $rn,$imm12
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# arm testcase for teq${cond}${set-cc?} $rn,$imm12
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# mach: unfinished
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# mach: unfinished
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global teq_imm
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.global teq_imm
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teq_imm:
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teq_imm:
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teq00 pc,0
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teq00 pc,0
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pass
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pass
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# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
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# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
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# mach: unfinished
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# mach: unfinished
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global teq_reg_imm_shift
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.global teq_reg_imm_shift
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teq_reg_imm_shift:
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teq_reg_imm_shift:
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teq00 pc,pc,pc,lsl 0
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teq00 pc,pc,pc,lsl 0
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pass
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pass
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# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
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# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
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# mach: unfinished
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# mach: unfinished
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global teq_reg_reg_shift
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.global teq_reg_reg_shift
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teq_reg_reg_shift:
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teq_reg_reg_shift:
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teq00 pc,pc,pc,lsl pc
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teq00 pc,pc,pc,lsl pc
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pass
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pass
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