OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [arm/] [testutils.inc] - Diff between revs 157 and 223

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 157 Rev 223
# r0-r3 are used as tmps, consider them call clobbered by these macros.
# r0-r3 are used as tmps, consider them call clobbered by these macros.
# This uses the angel rom monitor calls.
# This uses the angel rom monitor calls.
# ??? How do we use the \@ facility of .macros ???
# ??? How do we use the \@ facility of .macros ???
# @ is the comment char!
# @ is the comment char!
        .macro mvi_h_gr reg, val
        .macro mvi_h_gr reg, val
        ldr \reg,[pc]
        ldr \reg,[pc]
        b . + 8
        b . + 8
        .word \val
        .word \val
        .endm
        .endm
        .macro mvaddr_h_gr reg, addr
        .macro mvaddr_h_gr reg, addr
        ldr \reg,[pc]
        ldr \reg,[pc]
        b . + 8
        b . + 8
        .word \addr
        .word \addr
        .endm
        .endm
        .macro start
        .macro start
        .data
        .data
failmsg:
failmsg:
        .asciz "fail\n"
        .asciz "fail\n"
passmsg:
passmsg:
        .asciz "pass\n"
        .asciz "pass\n"
        .text
        .text
do_pass:
do_pass:
        ldr r1, passmsg_addr
        ldr r1, passmsg_addr
        mov r0, #4
        mov r0, #4
        swi #0x123456
        swi #0x123456
        exit 0
        exit 0
passmsg_addr:
passmsg_addr:
        .word passmsg
        .word passmsg
do_fail:
do_fail:
        ldr r1, failmsg_addr
        ldr r1, failmsg_addr
        mov r0, #4
        mov r0, #4
        swi #0x123456
        swi #0x123456
        exit 1
        exit 1
failmsg_addr:
failmsg_addr:
        .word failmsg
        .word failmsg
        .global _start
        .global _start
_start:
_start:
        .endm
        .endm
# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
        .macro pass
        .macro pass
        b do_pass
        b do_pass
        .endm
        .endm
        .macro fail
        .macro fail
        b do_fail
        b do_fail
        .endm
        .endm
        .macro exit rc
        .macro exit rc
        # ??? This works with the ARMulator but maybe not others.
        # ??? This works with the ARMulator but maybe not others.
        #mov r0, #\rc
        #mov r0, #\rc
        #swi #1
        #swi #1
        # This seems to be portable (though it ignores rc).
        # This seems to be portable (though it ignores rc).
        mov r0,#0x18
        mov r0,#0x18
        mvi_h_gr r1, 0x20026
        mvi_h_gr r1, 0x20026
        swi #0x123456
        swi #0x123456
        # If that returns, punt with a sigill.
        # If that returns, punt with a sigill.
        stc 0,cr0,[r0]
        stc 0,cr0,[r0]
        .endm
        .endm
# Other macros know this only clobbers r0.
# Other macros know this only clobbers r0.
# WARNING: It also clobbers the condition codes (FIXME).
# WARNING: It also clobbers the condition codes (FIXME).
        .macro test_h_gr reg, val
        .macro test_h_gr reg, val
        mvaddr_h_gr r0, \val
        mvaddr_h_gr r0, \val
        cmp \reg, r0
        cmp \reg, r0
        beq . + 8
        beq . + 8
        fail
        fail
        .endm
        .endm
        .macro mvi_h_cnvz c, n, v, z
        .macro mvi_h_cnvz c, n, v, z
        mov r0, #0
        mov r0, #0
        .if \c
        .if \c
        orr r0, r0, #0x20000000
        orr r0, r0, #0x20000000
        .endif
        .endif
        .if \n
        .if \n
        orr r0, r0, #0x80000000
        orr r0, r0, #0x80000000
        .endif
        .endif
        .if \v
        .if \v
        orr r0, r0, #0x10000000
        orr r0, r0, #0x10000000
        .endif
        .endif
        .if \z
        .if \z
        orr r0, r0, #0x40000000
        orr r0, r0, #0x40000000
        .endif
        .endif
        mrs r1, cpsr
        mrs r1, cpsr
        bic r1, r1, #0xf0000000
        bic r1, r1, #0xf0000000
        orr r1, r1, r0
        orr r1, r1, r0
        msr cpsr, r1
        msr cpsr, r1
        # ??? nops needed
        # ??? nops needed
        .endm
        .endm
# ??? Preserve condition codes?
# ??? Preserve condition codes?
        .macro test_h_cnvz c, n, v, z
        .macro test_h_cnvz c, n, v, z
        mov r0, #0
        mov r0, #0
        .if \c
        .if \c
        orr r0, r0, #0x20000000
        orr r0, r0, #0x20000000
        .endif
        .endif
        .if \n
        .if \n
        orr r0, r0, #0x80000000
        orr r0, r0, #0x80000000
        .endif
        .endif
        .if \v
        .if \v
        orr r0, r0, #0x10000000
        orr r0, r0, #0x10000000
        .endif
        .endif
        .if \z
        .if \z
        orr r0, r0, #0x40000000
        orr r0, r0, #0x40000000
        .endif
        .endif
        mrs r1, cpsr
        mrs r1, cpsr
        and r1, r1, #0xf0000000
        and r1, r1, #0xf0000000
        cmp r0, r1
        cmp r0, r1
        beq . + 8
        beq . + 8
        fail
        fail
        .endm
        .endm
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.