URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [nopv32t2.ms] - Diff between revs 157 and 223

Rev 157	Rev 223
`#mach: crisv10 crisv32`	`#mach: crisv10 crisv32`
`#output: Clock cycles including stall cycles for unaligned accesses @: 5\n`	`#output: Clock cycles including stall cycles for unaligned accesses @: 5\n`
`#output: Memory source stall cycles: 0\n`	`#output: Memory source stall cycles: 0\n`
`#output: Memory read-after-write stall cycles: 0\n`	`#output: Memory read-after-write stall cycles: 0\n`
`#output: Movem source stall cycles: 0\n`	`#output: Movem source stall cycles: 0\n`
`#output: Movem destination stall cycles: 0\n`	`#output: Movem destination stall cycles: 0\n`
`#output: Movem address stall cycles: 0\n`	`#output: Movem address stall cycles: 0\n`
`#output: Multiplication source stall cycles: 0\n`	`#output: Multiplication source stall cycles: 0\n`
`#output: Jump source stall cycles: 0\n`	`#output: Jump source stall cycles: 0\n`
`#output: Branch misprediction stall cycles: 0\n`	`#output: Branch misprediction stall cycles: 0\n`
`#output: Jump target stall cycles: 0\n`	`#output: Jump target stall cycles: 0\n`
`#sim: --cris-cycles=unaligned`	`#sim: --cris-cycles=unaligned`
`.include "nopv32t.ms"`	`.include "nopv32t.ms"`