URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [raw15.ms] - Diff between revs 157 and 223

Rev 157	Rev 223
`; Checking read-after-write: cycles included in "all".`	`; Checking read-after-write: cycles included in "all".`
`#mach: crisv32`	`#mach: crisv32`
`#output: All accounted clock cycles, total @: 6\n`	`#output: All accounted clock cycles, total @: 6\n`
`#output: Memory source stall cycles: 0\n`	`#output: Memory source stall cycles: 0\n`
`#output: Memory read-after-write stall cycles: 2\n`	`#output: Memory read-after-write stall cycles: 2\n`
`#output: Movem source stall cycles: 0\n`	`#output: Movem source stall cycles: 0\n`
`#output: Movem destination stall cycles: 0\n`	`#output: Movem destination stall cycles: 0\n`
`#output: Movem address stall cycles: 0\n`	`#output: Movem address stall cycles: 0\n`
`#output: Multiplication source stall cycles: 0\n`	`#output: Multiplication source stall cycles: 0\n`
`#output: Jump source stall cycles: 0\n`	`#output: Jump source stall cycles: 0\n`
`#output: Branch misprediction stall cycles: 0\n`	`#output: Branch misprediction stall cycles: 0\n`
`#output: Jump target stall cycles: 0\n`	`#output: Jump target stall cycles: 0\n`
`#sim: --cris-cycles=all`	`#sim: --cris-cycles=all`
`.include "raw4.ms"`	`.include "raw4.ms"`