URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 157 |
Rev 223 |
#mach: crisv10
|
#mach: crisv10
|
#output: Basic clock cycles, total @: 6\n
|
#output: Basic clock cycles, total @: 6\n
|
#output: Memory source stall cycles: 1\n
|
#output: Memory source stall cycles: 1\n
|
#output: Memory read-after-write stall cycles: 0\n
|
#output: Memory read-after-write stall cycles: 0\n
|
#output: Movem source stall cycles: 0\n
|
#output: Movem source stall cycles: 0\n
|
#output: Movem destination stall cycles: 0\n
|
#output: Movem destination stall cycles: 0\n
|
#output: Movem address stall cycles: 0\n
|
#output: Movem address stall cycles: 0\n
|
#output: Multiplication source stall cycles: 0\n
|
#output: Multiplication source stall cycles: 0\n
|
#output: Jump source stall cycles: 0\n
|
#output: Jump source stall cycles: 0\n
|
#output: Branch misprediction stall cycles: 0\n
|
#output: Branch misprediction stall cycles: 0\n
|
#output: Jump target stall cycles: 0\n
|
#output: Jump target stall cycles: 0\n
|
#sim: --cris-cycles=basic
|
#sim: --cris-cycles=basic
|
|
|
; Check that the 4-byte-skip doesn't make the simulator barf.
|
; Check that the 4-byte-skip doesn't make the simulator barf.
|
; Nothing deeper.
|
; Nothing deeper.
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
startnostack
|
startnostack
|
nop
|
nop
|
move.d 0f,r5
|
move.d 0f,r5
|
jsrc r5
|
jsrc r5
|
nop
|
nop
|
.dword -1
|
.dword -1
|
0:
|
0:
|
jsrc 1f
|
jsrc 1f
|
nop
|
nop
|
.dword -2
|
.dword -2
|
1:
|
1:
|
break 15
|
break 15
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.