OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [tmvm1.ms] - Diff between revs 157 and 223

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 157 Rev 223
#mach: crisv32
#mach: crisv32
#output: Basic clock cycles, total @: 18\n
#output: Basic clock cycles, total @: 18\n
#output: Memory source stall cycles: 0\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 6\n
#output: Movem destination stall cycles: 6\n
#output: Movem address stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
#sim: --cris-cycles=basic
; Check that movem to register followed by register write dword
; Check that movem to register followed by register write dword
; to one of the registers is logged as needing two stall cycles,
; to one of the registers is logged as needing two stall cycles,
; regardless of size.
; regardless of size.
 .include "testutils.inc"
 .include "testutils.inc"
 startnostack
 startnostack
 move.d 0f,r5
 move.d 0f,r5
 moveq 0,r8
 moveq 0,r8
 moveq 0,r9
 moveq 0,r9
 movem [r5],r4
 movem [r5],r4
 move.d r8,r1
 move.d r8,r1
 addq 1,r1      ; 2 cycles.
 addq 1,r1      ; 2 cycles.
 movem [r5],r4
 movem [r5],r4
 move.w r8,r1
 move.w r8,r1
 addq 1,r1      ; 2 cycles.
 addq 1,r1      ; 2 cycles.
 movem [r5],r4
 movem [r5],r4
 move.b r8,r1
 move.b r8,r1
 addq 1,r1      ; 2 cycles.
 addq 1,r1      ; 2 cycles.
 movem [r5],r4
 movem [r5],r4
 move.b r8,r1
 move.b r8,r1
 addq 1,r9
 addq 1,r9
 movem [r5],r4
 movem [r5],r4
 move.d r8,r1
 move.d r8,r1
 addq 1,r8
 addq 1,r8
 break 15
 break 15
 .data
 .data
 .p2align 5
 .p2align 5
0:
0:
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 .dword 0b
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.