URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 157 |
Rev 223 |
# fr30 testcase for andb $Rj,@$Ri
|
# fr30 testcase for andb $Rj,@$Ri
|
# mach(): fr30
|
# mach(): fr30
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
START
|
START
|
|
|
.text
|
.text
|
.global andb
|
.global andb
|
andb:
|
andb:
|
; Test andb $Rj,@$Ri
|
; Test andb $Rj,@$Ri
|
mvi_h_gr 0xaaaaaaaa,r7
|
mvi_h_gr 0xaaaaaaaa,r7
|
mvi_h_mem 0x55555555,sp
|
mvi_h_mem 0x55555555,sp
|
set_cc 0x0b ; Set mask opposite of expected
|
set_cc 0x0b ; Set mask opposite of expected
|
andb r7,@sp
|
andb r7,@sp
|
test_cc 0 1 1 1
|
test_cc 0 1 1 1
|
test_h_mem 0x00555555,sp
|
test_h_mem 0x00555555,sp
|
|
|
mvi_h_mem 0xffffffff,sp
|
mvi_h_mem 0xffffffff,sp
|
set_cc 0x04 ; Set mask opposite of expected
|
set_cc 0x04 ; Set mask opposite of expected
|
andb r7,@sp
|
andb r7,@sp
|
test_cc 1 0 0 0
|
test_cc 1 0 0 0
|
test_h_mem 0xaaffffff,sp
|
test_h_mem 0xaaffffff,sp
|
|
|
mvi_h_mem 0x0fffffff,sp
|
mvi_h_mem 0x0fffffff,sp
|
set_cc 0x0d ; Set mask opposite of expected
|
set_cc 0x0d ; Set mask opposite of expected
|
andb r7,@sp
|
andb r7,@sp
|
test_cc 0 0 0 1
|
test_cc 0 0 0 1
|
test_h_mem 0x0affffff,sp
|
test_h_mem 0x0affffff,sp
|
|
|
pass
|
pass
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.