URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [fr30/] [btstl.cgs] - Diff between revs 157 and 223

Rev 157	Rev 223
`# fr30 testcase for btstl $Rj,@$Ri`	`# fr30 testcase for btstl $Rj,@$Ri`
`# mach(): fr30`	`# mach(): fr30`

`.include "testutils.inc"`	`.include "testutils.inc"`

`START`	`START`

`.text`	`.text`
`.global btstl`	`.global btstl`
`btstl:`	`btstl:`
`; Test btstl $Rj,@$Ri`	`; Test btstl $Rj,@$Ri`
`mvi_h_mem 0x55555555,sp`	`mvi_h_mem 0x55555555,sp`
`set_cc 0x0b ; Set mask opposite of expected`	`set_cc 0x0b ; Set mask opposite of expected`
`btstl 0x0a,@sp`	`btstl 0x0a,@sp`
`test_cc 0 1 1 1`	`test_cc 0 1 1 1`
`test_h_mem 0x55555555,sp`	`test_h_mem 0x55555555,sp`

`mvi_h_mem 0xffffffff,sp`	`mvi_h_mem 0xffffffff,sp`
`set_cc 0x0c ; Set mask opposite of expected`	`set_cc 0x0c ; Set mask opposite of expected`
`btstl 0x0a,@sp`	`btstl 0x0a,@sp`
`test_cc 0 0 0 0`	`test_cc 0 0 0 0`
`test_h_mem 0xffffffff,sp`	`test_h_mem 0xffffffff,sp`

`mvi_h_mem 0x5effffff,sp`	`mvi_h_mem 0x5effffff,sp`
`set_cc 0x0e ; Set mask opposite of expected`	`set_cc 0x0e ; Set mask opposite of expected`
`btstl 0x07,@sp`	`btstl 0x07,@sp`
`test_cc 0 0 1 0`	`test_cc 0 0 1 0`
`test_h_mem 0x5effffff,sp`	`test_h_mem 0x5effffff,sp`

`pass`	`pass`