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Rev 223 |
# fr30 testcase for division
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# fr30 testcase for division
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# mach(): fr30
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# mach(): fr30
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.include "testutils.inc"
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.include "testutils.inc"
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START
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START
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.text
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.text
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.global div
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.global div
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div:
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div:
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; simple division 12 / 3
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; simple division 12 / 3
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mvi_h_gr 0x00000003,r2
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mvi_h_gr 0x00000003,r2
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0x0000000c,mdl
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mvi_h_dr 0x0000000c,mdl
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div0s r2
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div0s r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div2 r2
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div2 r2
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div3
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div3
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div4s
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div4s
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test_h_gr 0x00000003,r2
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test_h_gr 0x00000003,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x00000000,mdh
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test_h_dr 0x00000004,mdl
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test_h_dr 0x00000004,mdl
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test_dbits 0x0
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test_dbits 0x0
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; example 1 from div0s the manual
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; example 1 from div0s the manual
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mvi_h_gr 0x01234567,r2
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mvi_h_gr 0x01234567,r2
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xfedcba98,mdl
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mvi_h_dr 0xfedcba98,mdl
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div0s r2
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div0s r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div2 r2
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div2 r2
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div3
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div3
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div4s
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div4s
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test_h_gr 0x01234567,r2
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test_h_gr 0x01234567,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdl
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test_h_dr 0xffffffff,mdl
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test_dbits 0x3
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test_dbits 0x3
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; example 2 from div0s the manual
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; example 2 from div0s the manual
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xfedcba98,mdl
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mvi_h_dr 0xfedcba98,mdl
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mvi_h_gr 0x1234567,r2
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mvi_h_gr 0x1234567,r2
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mvi_h_gr 1,r0
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mvi_h_gr 1,r0
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mvi_h_gr 32,r1
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mvi_h_gr 32,r1
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div0s r2
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div0s r2
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loop1: sub r0,r1
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loop1: sub r0,r1
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bne:d loop1
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bne:d loop1
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div1 r2
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div1 r2
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div2 r2
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div2 r2
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div3
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div3
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div4s
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div4s
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test_h_gr 0x01234567,r2
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test_h_gr 0x01234567,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdl
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test_h_dr 0xffffffff,mdl
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test_dbits 0x3
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test_dbits 0x3
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; example 1 from div0u in the manual
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; example 1 from div0u in the manual
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mvi_h_gr 0x01234567,r2
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mvi_h_gr 0x01234567,r2
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xfedcba98,mdl
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mvi_h_dr 0xfedcba98,mdl
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div0u r2
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div0u r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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div1 r2
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test_h_gr 0x01234567,r2
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test_h_gr 0x01234567,r2
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test_h_dr 0x00000078,mdh
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test_h_dr 0x00000078,mdh
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test_h_dr 0x000000e0,mdl
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test_h_dr 0x000000e0,mdl
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test_dbits 0x0
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test_dbits 0x0
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; example 2 from div0u in the manual
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; example 2 from div0u in the manual
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xdeadbeef,mdh
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mvi_h_dr 0xfedcba98,mdl
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mvi_h_dr 0xfedcba98,mdl
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mvi_h_gr 0x1234567,r2
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mvi_h_gr 0x1234567,r2
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mvi_h_gr 1,r0
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mvi_h_gr 1,r0
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mvi_h_gr 32,r1
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mvi_h_gr 32,r1
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div0u r2
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div0u r2
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loop2: sub r0,r1
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loop2: sub r0,r1
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bne:d loop2
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bne:d loop2
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div1 r2
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div1 r2
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test_h_gr 0x01234567,r2
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test_h_gr 0x01234567,r2
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test_h_dr 0x00000078,mdh
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test_h_dr 0x00000078,mdh
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test_h_dr 0x000000e0,mdl
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test_h_dr 0x000000e0,mdl
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test_dbits 0x0
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test_dbits 0x0
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pass
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pass
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