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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [fr30/] [div3.cgs] - Diff between revs 157 and 223

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Rev 157	Rev 223
`# fr30 testcase for div3`	`# fr30 testcase for div3`
`# mach(): fr30`	`# mach(): fr30`

`.include "testutils.inc"`	`.include "testutils.inc"`

`START`	`START`

`.text`	`.text`
`.global div3`	`.global div3`
`div3:`	`div3:`
`; Test div3`	`; Test div3`
`; example from the manual`	`; example from the manual`
`mvi_h_gr 0x00ffffff,r2`	`mvi_h_gr 0x00ffffff,r2`
`mvi_h_dr 0x00000000,mdh`	`mvi_h_dr 0x00000000,mdh`
`mvi_h_dr 0x0000000f,mdl`	`mvi_h_dr 0x0000000f,mdl`
`set_dbits 0x0`	`set_dbits 0x0`
`set_cc 0x04`	`set_cc 0x04`
`div3`	`div3`
`test_cc 0 1 0 0`	`test_cc 0 1 0 0`
`test_dbits 0x0`	`test_dbits 0x0`
`test_h_gr 0x00ffffff,r2`	`test_h_gr 0x00ffffff,r2`
`test_h_dr 0x00000000,mdh`	`test_h_dr 0x00000000,mdh`
`test_h_dr 0x00000010,mdl`	`test_h_dr 0x00000010,mdl`

`set_dbits 0x0`	`set_dbits 0x0`
`set_cc 0x00`	`set_cc 0x00`
`div3`	`div3`
`test_cc 0 0 0 0`	`test_cc 0 0 0 0`
`test_dbits 0x0`	`test_dbits 0x0`
`test_h_gr 0x00ffffff,r2`	`test_h_gr 0x00ffffff,r2`
`test_h_dr 0x00000000,mdh`	`test_h_dr 0x00000000,mdh`
`test_h_dr 0x00000010,mdl`	`test_h_dr 0x00000010,mdl`

`pass`	`pass`

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