URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 24 |
Rev 157 |
# fr30 testcase for enter $u10
|
# fr30 testcase for enter $u10
|
# mach(): fr30
|
# mach(): fr30
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
START
|
START
|
|
|
.text
|
.text
|
.global enter
|
.global enter
|
enter:
|
enter:
|
; Test enter $u10
|
; Test enter $u10
|
mvr_h_gr sp,r7 ; save stack pointer
|
mvr_h_gr sp,r7 ; save stack pointer
|
mvr_h_gr sp,r8 ; shadow stack pointer
|
mvr_h_gr sp,r8 ; shadow stack pointer
|
mvr_h_gr sp,r14 ; Initialize
|
mvr_h_gr sp,r14 ; Initialize
|
set_cc 0x0f ; Condition codes are irrelevent
|
set_cc 0x0f ; Condition codes are irrelevent
|
enter 0
|
enter 0
|
test_cc 1 1 1 1
|
test_cc 1 1 1 1
|
testr_h_gr r8,sp
|
testr_h_gr r8,sp
|
inci_h_gr -4,r8
|
inci_h_gr -4,r8
|
testr_h_gr r14,r8
|
testr_h_gr r14,r8
|
testr_h_mem r7,r14
|
testr_h_mem r7,r14
|
|
|
mvr_h_gr sp,r8 ; shadow stack pointer
|
mvr_h_gr sp,r8 ; shadow stack pointer
|
mvr_h_gr r14,r9 ; save
|
mvr_h_gr r14,r9 ; save
|
set_cc 0x0e ; Condition codes are irrelevent
|
set_cc 0x0e ; Condition codes are irrelevent
|
enter 0x3fc
|
enter 0x3fc
|
test_cc 1 1 1 0
|
test_cc 1 1 1 0
|
inci_h_gr -4,r8
|
inci_h_gr -4,r8
|
testr_h_gr r14,r8
|
testr_h_gr r14,r8
|
testr_h_mem r9,r14
|
testr_h_mem r9,r14
|
inci_h_gr -0x3f8,r8
|
inci_h_gr -0x3f8,r8
|
testr_h_gr r8,sp
|
testr_h_gr r8,sp
|
|
|
pass
|
pass
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.