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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 157 |
Rev 223 |
# frv testcase for bltlr $ICCi,$hint
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# frv testcase for bltlr $ICCi,$hint
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global bltlr
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.global bltlr
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bltlr:
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bltlr:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x0 0
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set_icc 0x0 0
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bltlr icc0,0
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bltlr icc0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x1 1
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set_icc 0x1 1
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bltlr icc1,1
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bltlr icc1,1
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set_spr_addr ok3,lr
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set_spr_addr ok3,lr
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set_icc 0x2 2
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set_icc 0x2 2
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bltlr icc2,2
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bltlr icc2,2
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fail
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fail
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ok3:
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ok3:
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set_spr_addr ok4,lr
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set_spr_addr ok4,lr
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set_icc 0x3 3
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set_icc 0x3 3
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bltlr icc3,3
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bltlr icc3,3
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fail
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fail
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ok4:
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ok4:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x4 0
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set_icc 0x4 0
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bltlr icc0,0
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bltlr icc0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x5 1
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set_icc 0x5 1
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bltlr icc1,1
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bltlr icc1,1
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set_spr_addr ok7,lr
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set_spr_addr ok7,lr
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set_icc 0x6 2
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set_icc 0x6 2
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bltlr icc2,2
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bltlr icc2,2
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fail
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fail
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ok7:
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ok7:
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set_spr_addr ok8,lr
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set_spr_addr ok8,lr
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set_icc 0x7 3
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set_icc 0x7 3
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bltlr icc3,3
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bltlr icc3,3
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fail
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fail
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ok8:
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ok8:
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set_spr_addr ok9,lr
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set_spr_addr ok9,lr
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set_icc 0x8 0
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set_icc 0x8 0
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bltlr icc0,0
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bltlr icc0,0
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fail
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fail
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ok9:
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ok9:
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set_spr_addr oka,lr
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set_spr_addr oka,lr
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set_icc 0x9 1
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set_icc 0x9 1
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bltlr icc1,1
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bltlr icc1,1
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fail
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fail
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oka:
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oka:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0xa 2
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set_icc 0xa 2
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bltlr icc2,2
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bltlr icc2,2
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0xb 3
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set_icc 0xb 3
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bltlr icc3,3
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bltlr icc3,3
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set_spr_addr okd,lr
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set_spr_addr okd,lr
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set_icc 0xc 0
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set_icc 0xc 0
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bltlr icc0,0
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bltlr icc0,0
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fail
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fail
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okd:
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okd:
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set_spr_addr oke,lr
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set_spr_addr oke,lr
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set_icc 0xd 1
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set_icc 0xd 1
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bltlr icc1,1
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bltlr icc1,1
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fail
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fail
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oke:
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oke:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0xe 2
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set_icc 0xe 2
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bltlr icc2,2
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bltlr icc2,2
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0xf 3
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set_icc 0xf 3
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bltlr icc3,3
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bltlr icc3,3
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pass
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pass
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bad:
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bad:
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fail
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fail
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