# FRV testcase for break
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# FRV testcase for break
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global tra
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.global tra
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tra:
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tra:
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; Can't test break anymore in the user environment because it is the
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; Can't test break anymore in the user environment because it is the
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; debugger's breakpoint insn. Just pass this test for now.
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; debugger's breakpoint insn. Just pass this test for now.
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pass
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pass
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set_gr_spr tbr,gr7
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set_gr_spr tbr,gr7
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and_gr_immed -4081,gr7 ; clear tbr.tt
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and_gr_immed -4081,gr7 ; clear tbr.tt
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inc_gr_immed 0xff0,gr7 ; break handler
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inc_gr_immed 0xff0,gr7 ; break handler
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set_bctrlr_0_0 gr7
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set_bctrlr_0_0 gr7
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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test_spr_bits 0x4,2,0x1,psr ; psr.s is set
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test_spr_bits 0x4,2,0x1,psr ; psr.s is set
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test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
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test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
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set_spr_addr ok1,lr
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set_spr_addr ok1,lr
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break
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break
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ret:
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ret:
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or_spr_immed 0x00000001,psr ; turn on psr.et
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or_spr_immed 0x00000001,psr ; turn on psr.et
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and_spr_immed 0xfffffffb,psr ; turn off psr.s
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and_spr_immed 0xfffffffb,psr ; turn off psr.s
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test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
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test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
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test_spr_bits 0x1,0,0x1,psr ; psr.et is set
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test_spr_bits 0x1,0,0x1,psr ; psr.et is set
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set_spr_addr ok0,lr
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set_spr_addr ok0,lr
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break
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break
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ret1:
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ret1:
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test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
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test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
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test_spr_bits 0x1,0,0x1,psr ; psr.et is set
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test_spr_bits 0x1,0,0x1,psr ; psr.et is set
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pass
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pass
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; check interrupt for second break
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; check interrupt for second break
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ok0: test_spr_addr ret1,bpcsr
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ok0: test_spr_addr ret1,bpcsr
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test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear
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test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear
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test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set
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test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set
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test_spr_bits 0x4,2,0x1,psr ; psr.s is set
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test_spr_bits 0x4,2,0x1,psr ; psr.s is set
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test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
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test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
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rett 0 ; nop
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rett 0 ; nop
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rett 1
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rett 1
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; check interrupt for first break
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; check interrupt for first break
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ok1: test_spr_addr ret,bpcsr
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ok1: test_spr_addr ret,bpcsr
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test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set
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test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set
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test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear
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test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear
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test_spr_bits 0x4,2,0x1,psr ; psr.s is set
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test_spr_bits 0x4,2,0x1,psr ; psr.s is set
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test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
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test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
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rett 0 ; nop
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rett 0 ; nop
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rett 1
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rett 1
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