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[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [frv/] [fcbnolr.cgs] - Diff between revs 157 and 223

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Rev 157 Rev 223
# frv testcase for fcbnolr
# frv testcase for fcbnolr
# mach: all
# mach: all
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global fcbnolr
        .global fcbnolr
fcbnolr:
fcbnolr:
        ; ccond is true
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        set_fcc         0x0 0
        fcbnolr
        fcbnolr
        set_fcc         0x1 1
        set_fcc         0x1 1
        fcbnolr
        fcbnolr
        set_fcc         0x2 2
        set_fcc         0x2 2
        fcbnolr
        fcbnolr
        set_fcc         0x3 3
        set_fcc         0x3 3
        fcbnolr
        fcbnolr
        set_fcc         0x4 0
        set_fcc         0x4 0
        fcbnolr
        fcbnolr
        set_fcc         0x5 1
        set_fcc         0x5 1
        fcbnolr
        fcbnolr
        set_fcc         0x6 2
        set_fcc         0x6 2
        fcbnolr
        fcbnolr
        set_fcc         0x7 3
        set_fcc         0x7 3
        fcbnolr
        fcbnolr
        set_fcc         0x8 0
        set_fcc         0x8 0
        fcbnolr
        fcbnolr
        set_fcc         0x9 1
        set_fcc         0x9 1
        fcbnolr
        fcbnolr
        set_fcc         0xa 2
        set_fcc         0xa 2
        fcbnolr
        fcbnolr
        set_fcc         0xb 3
        set_fcc         0xb 3
        fcbnolr
        fcbnolr
        set_fcc         0xc 0
        set_fcc         0xc 0
        fcbnolr
        fcbnolr
        set_fcc         0xd 1
        set_fcc         0xd 1
        fcbnolr
        fcbnolr
        set_fcc         0xe 2
        set_fcc         0xe 2
        fcbnolr
        fcbnolr
        set_fcc         0xf 3
        set_fcc         0xf 3
        fcbnolr
        fcbnolr
        ; ccond is true
        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x0 0
        set_fcc         0x0 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x1 1
        set_fcc         0x1 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x2 2
        set_fcc         0x2 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x3 3
        set_fcc         0x3 3
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x4 0
        set_fcc         0x4 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x5 1
        set_fcc         0x5 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x6 2
        set_fcc         0x6 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x7 3
        set_fcc         0x7 3
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x8 0
        set_fcc         0x8 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x9 1
        set_fcc         0x9 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xa 2
        set_fcc         0xa 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xb 3
        set_fcc         0xb 3
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xc 0
        set_fcc         0xc 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xd 1
        set_fcc         0xd 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xe 2
        set_fcc         0xe 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xf 3
        set_fcc         0xf 3
        fcbnolr
        fcbnolr
        ; ccond is false
        ; ccond is false
        set_spr_immed   128,lcr
        set_spr_immed   128,lcr
        set_fcc         0x0 0
        set_fcc         0x0 0
        fcbnolr
        fcbnolr
        set_fcc         0x1 1
        set_fcc         0x1 1
        fcbnolr
        fcbnolr
        set_fcc         0x2 2
        set_fcc         0x2 2
        fcbnolr
        fcbnolr
        set_fcc         0x3 3
        set_fcc         0x3 3
        fcbnolr
        fcbnolr
        set_fcc         0x4 0
        set_fcc         0x4 0
        fcbnolr
        fcbnolr
        set_fcc         0x5 1
        set_fcc         0x5 1
        fcbnolr
        fcbnolr
        set_fcc         0x6 2
        set_fcc         0x6 2
        fcbnolr
        fcbnolr
        set_fcc         0x7 3
        set_fcc         0x7 3
        fcbnolr
        fcbnolr
        set_fcc         0x8 0
        set_fcc         0x8 0
        fcbnolr
        fcbnolr
        set_fcc         0x9 1
        set_fcc         0x9 1
        fcbnolr
        fcbnolr
        set_fcc         0xa 2
        set_fcc         0xa 2
        fcbnolr
        fcbnolr
        set_fcc         0xb 3
        set_fcc         0xb 3
        fcbnolr
        fcbnolr
        set_fcc         0xc 0
        set_fcc         0xc 0
        fcbnolr
        fcbnolr
        set_fcc         0xd 1
        set_fcc         0xd 1
        fcbnolr
        fcbnolr
        set_fcc         0xe 2
        set_fcc         0xe 2
        fcbnolr
        fcbnolr
        set_fcc         0xf 3
        set_fcc         0xf 3
        fcbnolr
        fcbnolr
        ; ccond is false
        ; ccond is false
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x0 0
        set_fcc         0x0 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x1 1
        set_fcc         0x1 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x2 2
        set_fcc         0x2 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x3 3
        set_fcc         0x3 3
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x4 0
        set_fcc         0x4 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x5 1
        set_fcc         0x5 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x6 2
        set_fcc         0x6 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x7 3
        set_fcc         0x7 3
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x8 0
        set_fcc         0x8 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0x9 1
        set_fcc         0x9 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xa 2
        set_fcc         0xa 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xb 3
        set_fcc         0xb 3
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xc 0
        set_fcc         0xc 0
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xd 1
        set_fcc         0xd 1
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xe 2
        set_fcc         0xe 2
        fcbnolr
        fcbnolr
        set_spr_immed   1,lcr
        set_spr_immed   1,lcr
        set_fcc         0xf 3
        set_fcc         0xf 3
        fcbnolr
        fcbnolr
        pass
        pass
bad:
bad:
        fail
        fail
 
 

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