# frv testcase for mqcpxis $GRi,$GRj,$ACCk
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# frv testcase for mqcpxis $GRi,$GRj,$ACCk
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global mqcpxis
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.global mqcpxis
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mqcpxis:
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mqcpxis:
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; Positive operands
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; Positive operands
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set_fr_iimmed 2,4,fr8 ; multiply small numbers
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set_fr_iimmed 2,4,fr8 ; multiply small numbers
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set_fr_iimmed 5,3,fr10
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set_fr_iimmed 5,3,fr10
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set_fr_iimmed 3,1,fr9 ; multiply by 0
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set_fr_iimmed 3,1,fr9 ; multiply by 0
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set_fr_iimmed 0,2,fr11
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set_fr_iimmed 0,2,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0x00,accg0
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test_accg_immed 0x00,accg0
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test_acc_immed 26,acc0
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test_acc_immed 26,acc0
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test_accg_immed 0,accg1
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test_accg_immed 0,accg1
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test_acc_immed 6,acc1
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test_acc_immed 6,acc1
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set_fr_iimmed 2,1,fr8 ; multiply by 1
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set_fr_iimmed 2,1,fr8 ; multiply by 1
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set_fr_iimmed 1,1,fr10
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set_fr_iimmed 1,1,fr10
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set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result
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set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result
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set_fr_iimmed 0x0001,2,fr11
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set_fr_iimmed 0x0001,2,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0,accg0
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test_accg_immed 0,accg0
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test_acc_immed 3,acc0
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test_acc_immed 3,acc0
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test_accg_immed 0,accg1
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test_accg_immed 0,accg1
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test_acc_limmed 0,0x7fff,acc1
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test_acc_limmed 0,0x7fff,acc1
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set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
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set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
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set_fr_iimmed 0x2000,2,fr10
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set_fr_iimmed 0x2000,2,fr10
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set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result
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set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result
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set_fr_iimmed 0x7fff,0x7fff,fr11
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set_fr_iimmed 0x7fff,0x7fff,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0,accg0
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test_accg_immed 0,accg0
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test_acc_limmed 0x0000,0xc000,acc0
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test_acc_limmed 0x0000,0xc000,acc0
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test_accg_immed 0,accg1
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test_accg_immed 0,accg1
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test_acc_limmed 0x3fff,0x0001,acc1
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test_acc_limmed 0x3fff,0x0001,acc1
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; Mixed operands
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; Mixed operands
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set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
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set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
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set_fr_iimmed 1,0xfffd,fr10
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set_fr_iimmed 1,0xfffd,fr10
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set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1
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set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1
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set_fr_iimmed 0xfffe,1,fr11
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set_fr_iimmed 0xfffe,1,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0xff,accg0
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test_accg_immed 0xff,accg0
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test_acc_immed -9,acc0
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test_acc_immed -9,acc0
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test_accg_immed 0xff,accg1
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test_accg_immed 0xff,accg1
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test_acc_immed -6,acc1
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test_acc_immed -6,acc1
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set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
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set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
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set_fr_iimmed 0xfffe,1,fr10
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set_fr_iimmed 0xfffe,1,fr10
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set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result
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set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result
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set_fr_iimmed 0xffff,0xfffe,fr11
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set_fr_iimmed 0xffff,0xfffe,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0xff,accg0
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test_accg_immed 0xff,accg0
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test_acc_immed -2,acc0
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test_acc_immed -2,acc0
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test_accg_immed 0xff,accg1
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test_accg_immed 0xff,accg1
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test_acc_limmed 0xffff,0xbfff,acc1
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test_acc_limmed 0xffff,0xbfff,acc1
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set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
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set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
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set_fr_iimmed 0x0003,0xfffe,fr10
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set_fr_iimmed 0x0003,0xfffe,fr10
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set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result
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set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result
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set_fr_iimmed 0x8000,0x8000,fr11
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set_fr_iimmed 0x8000,0x8000,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0xff,accg0
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test_accg_immed 0xff,accg0
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test_acc_limmed 0xffff,0x7ffa,acc0
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test_acc_limmed 0xffff,0x7ffa,acc0
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test_accg_immed 0xff,accg1
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test_accg_immed 0xff,accg1
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test_acc_limmed 0x8001,0x0000,acc1
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test_acc_limmed 0x8001,0x0000,acc1
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; Negative operands
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; Negative operands
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set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr10
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set_fr_iimmed 0x8000,0x8000,fr10
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set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers
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set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers
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set_fr_iimmed 0xfffb,0xfffd,fr11
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set_fr_iimmed 0xfffb,0xfffd,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0x00,accg0
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test_accg_immed 0x00,accg0
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test_acc_limmed 0x8000,0x0000,acc0
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test_acc_limmed 0x8000,0x0000,acc0
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test_accg_immed 0x00,accg1
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test_accg_immed 0x00,accg1
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test_acc_immed 26,acc1
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test_acc_immed 26,acc1
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set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1
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set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1
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set_fr_iimmed 0xffff,0xfffe,fr10
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set_fr_iimmed 0xffff,0xfffe,fr10
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set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result
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set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result
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set_fr_iimmed 0x8001,0x7fff,fr11
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set_fr_iimmed 0x8001,0x7fff,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0,accg0
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test_accg_immed 0,accg0
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test_acc_immed 3,acc0
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test_acc_immed 3,acc0
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test_accg_immed 0,accg1
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test_accg_immed 0,accg1
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test_acc_immed 0x3fff0001,acc1
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test_acc_immed 0x3fff0001,acc1
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set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result
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set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr10
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set_fr_iimmed 0x8000,0x8000,fr10
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set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result
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set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result
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set_fr_iimmed 0x8000,0x8000,fr11
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set_fr_iimmed 0x8000,0x8000,fr11
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mqcpxis fr8,fr10,acc0
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mqcpxis fr8,fr10,acc0
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test_accg_immed 0,accg0
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test_accg_immed 0,accg0
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test_acc_immed 0x40000000,acc0
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test_acc_immed 0x40000000,acc0
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test_accg_immed 0,accg1
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test_accg_immed 0,accg1
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test_acc_immed 0x40000000,acc1
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test_acc_immed 0x40000000,acc1
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pass
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pass
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