# Hitachi H8 testcase 'not.b, not.w, not.l'
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# Hitachi H8 testcase 'not.b, not.w, not.l'
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# mach(): all
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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# Instructions tested:
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# Instructions tested:
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# not.b rd ; 1 7 0 rd
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# not.b rd ; 1 7 0 rd
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# not.b @erd ; 7 d rd ???? 1 7 0 ignore
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# not.b @erd ; 7 d rd ???? 1 7 0 ignore
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# not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore
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# not.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 0 ignore
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# not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore
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# not.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 0 ignore
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# not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore
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# not.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 0 ignore
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# not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore
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# not.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 0 ignore
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# not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore
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# not.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 0 ignore
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# not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore
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# not.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 0 ignore
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# not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore
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# not.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 0 ignore
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# not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore
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# not.b @aa:16 ; 6 a 1 1??? aa:16 1 7 0 ignore
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# not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore
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# not.b @aa:32 ; 6 a 3 1??? aa:32 1 7 0 ignore
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# word operations
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# word operations
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# long operations
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# long operations
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#
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#
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# Coming soon:
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# Coming soon:
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# not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore
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# not.b @aa:8 ; 7 f aaaaaaaa 1 7 0 ignore
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#
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#
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.data
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.data
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byte_dest: .byte 0xa5
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byte_dest: .byte 0xa5
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.align 2
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.align 2
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word_dest: .word 0xa5a5
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word_dest: .word 0xa5a5
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.align 4
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.align 4
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long_dest: .long 0xa5a5a5a5
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long_dest: .long 0xa5a5a5a5
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start
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start
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#
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#
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# 8-bit byte operations
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# 8-bit byte operations
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#
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#
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not_b_reg8:
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not_b_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; not.b Rd
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;; not.b Rd
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not r0l ; 8-bit register
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not r0l ; 8-bit register
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;;; .word 0x1708
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;;; .word 0x1708
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cmp.b #0x5a, r0l ; result of "not 0xa5"
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cmp.b #0x5a, r0l ; result of "not 0xa5"
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beq .Lbrd
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beq .Lbrd
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fail
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fail
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.Lbrd:
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.Lbrd:
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa55a r0 ; r0 changed by 'not'
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test_h_gr16 0xa55a r0 ; r0 changed by 'not'
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not'
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test_h_gr32 0xa5a5a55a er0 ; er0 changed by 'not'
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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.if (sim_cpu == h8sx)
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not_b_rdind:
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not_b_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @eRd
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;; not.b @eRd
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mov #byte_dest, er0
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mov #byte_dest, er0
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not.b @er0 ; register indirect operand
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not.b @er0 ; register indirect operand
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;;; .word 0x7d00
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;;; .word 0x7d00
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 byte_dest er0 ; er0 still contains address
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test_h_gr32 byte_dest er0 ; er0 still contains address
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cmp.b #0x5a:8, @er0 ; memory contents changed
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cmp.b #0x5a:8, @er0 ; memory contents changed
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beq .Lbind
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beq .Lbind
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fail
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fail
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.Lbind:
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.Lbind:
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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not_b_rdpostinc:
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not_b_rdpostinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @eRd+
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;; not.b @eRd+
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mov #byte_dest, er0 ; register post-increment operand
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mov #byte_dest, er0 ; register post-increment operand
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not.b @er0+
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not.b @er0+
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;;; .word 0x0174
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;;; .word 0x0174
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;;; .word 0x6c08
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;;; .word 0x6c08
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_set
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test_neg_set
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test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one
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test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one
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cmp.b #0xa5:8, @-er0
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cmp.b #0xa5:8, @-er0
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beq .Lbpostinc
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beq .Lbpostinc
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fail
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fail
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.Lbpostinc:
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.Lbpostinc:
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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not_b_rdpostdec:
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not_b_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @eRd-
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;; not.b @eRd-
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mov #byte_dest, er0 ; register post-decrement operand
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mov #byte_dest, er0 ; register post-decrement operand
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not.b @er0-
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not.b @er0-
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;;; .word 0x0176
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;;; .word 0x0176
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;;; .word 0x6c08
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;;; .word 0x6c08
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_clear
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test_neg_clear
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test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
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test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
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cmp.b #0x5a:8, @+er0
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cmp.b #0x5a:8, @+er0
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;;; .word 0x0175
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;;; .word 0x0175
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;;; .word 0x6c08
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;;; .word 0x6c08
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;;; .word 0xa05a
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;;; .word 0xa05a
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beq .Lbpostdec
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beq .Lbpostdec
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fail
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fail
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.Lbpostdec:
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.Lbpostdec:
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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not_b_rdpreinc:
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not_b_rdpreinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @+eRd
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;; not.b @+eRd
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mov #byte_dest-1, er0
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mov #byte_dest-1, er0
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not.b @+er0 ; reg pre-increment operand
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not.b @+er0 ; reg pre-increment operand
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;;; .word 0x0175
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;;; .word 0x0175
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;;; .word 0x6c08
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;;; .word 0x6c08
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_set
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test_neg_set
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cmp.b #0xa5:8, @er0
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cmp.b #0xa5:8, @er0
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beq .Lbpreinc
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beq .Lbpreinc
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fail
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fail
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.Lbpreinc:
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.Lbpreinc:
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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not_b_rdpredec:
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not_b_rdpredec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @-eRd
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;; not.b @-eRd
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mov #byte_dest+1, er0
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mov #byte_dest+1, er0
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not.b @-er0 ; reg pre-decr operand
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not.b @-er0 ; reg pre-decr operand
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;;; .word 0x0177
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;;; .word 0x0177
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;;; .word 0x6c08
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;;; .word 0x6c08
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_clear
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test_neg_clear
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cmp.b #0x5a:8, @er0
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cmp.b #0x5a:8, @er0
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beq .Lbpredec
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beq .Lbpredec
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fail
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fail
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.Lbpredec:
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.Lbpredec:
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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not_b_disp2dst:
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not_b_disp2dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @(dd:2, erd)
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;; not.b @(dd:2, erd)
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mov #byte_dest-1, er0
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mov #byte_dest-1, er0
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not.b @(1:2, er0) ; reg plus 2-bit displacement
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not.b @(1:2, er0) ; reg plus 2-bit displacement
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;;; .word 0x0175
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;;; .word 0x0175
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;;; .word 0x6808
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;;; .word 0x6808
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_set
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test_neg_set
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cmp.b #0xa5:8, @+er0
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cmp.b #0xa5:8, @+er0
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beq .Lbdisp2
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beq .Lbdisp2
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fail
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fail
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.Lbdisp2:
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.Lbdisp2:
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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not_b_disp16dst:
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not_b_disp16dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
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;; not.b @(dd:16, erd)
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;; not.b @(dd:16, erd)
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mov #byte_dest+100, er0
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mov #byte_dest+100, er0
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not.b @(-100:16, er0) ; reg plus 16-bit displacement
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not.b @(-100:16, er0) ; reg plus 16-bit displacement
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;;; .word 0x0174
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;;; .word 0x0174
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;;; .word 0x6e08
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;;; .word 0x6e08
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;;; .word -100
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;;; .word -100
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;;; .word 0x1700
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;;; .word 0x1700
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_ovf_clear
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test_zero_clear
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test_zero_clear
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test_neg_clear
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test_neg_clear
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cmp.b #0x5a:8, @byte_dest
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cmp.b #0x5a:8, @byte_dest
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beq .Lbdisp16
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beq .Lbdisp16
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fail
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fail
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.Lbdisp16:
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.Lbdisp16:
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test_h_gr32 byte_dest+100 er0 ; er0 contains destination address
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test_h_gr32 byte_dest+100 er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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|
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not_b_disp32dst:
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not_b_disp32dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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set_ccr_zero
|
|
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;; not.b @(dd:32, erd)
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;; not.b @(dd:32, erd)
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mov #byte_dest-0xfffff, er0
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mov #byte_dest-0xfffff, er0
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not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement
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not.b @(0xfffff:32, er0) ; reg plus 32-bit displacement
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;;; .word 0x7804
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;;; .word 0x7804
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;;; .word 0x6a28
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;;; .word 0x6a28
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;;; .long 0xfffff
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;;; .long 0xfffff
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;;; .word 0x1700
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;;; .word 0x1700
|
|
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.b #0xa5:8, @byte_dest
|
cmp.b #0xa5:8, @byte_dest
|
beq .Lbdisp32
|
beq .Lbdisp32
|
fail
|
fail
|
.Lbdisp32:
|
.Lbdisp32:
|
test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
|
test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_b_abs16dst:
|
not_b_abs16dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.b @aa:16
|
;; not.b @aa:16
|
not.b @byte_dest:16 ; 16-bit absolute address
|
not.b @byte_dest:16 ; 16-bit absolute address
|
;;; .word 0x6a18
|
;;; .word 0x6a18
|
;;; .word byte_dest
|
;;; .word byte_dest
|
;;; .word 0x1700
|
;;; .word 0x1700
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.b #0x5a:8, @byte_dest
|
cmp.b #0x5a:8, @byte_dest
|
beq .Lbabs16
|
beq .Lbabs16
|
fail
|
fail
|
.Lbabs16:
|
.Lbabs16:
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_b_abs32dst:
|
not_b_abs32dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.b @aa:32
|
;; not.b @aa:32
|
not.b @byte_dest:32 ; 32-bit absolute address
|
not.b @byte_dest:32 ; 32-bit absolute address
|
;;; .word 0x6a38
|
;;; .word 0x6a38
|
;;; .long byte_dest
|
;;; .long byte_dest
|
;;; .word 0x1700
|
;;; .word 0x1700
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.b #0xa5:8, @byte_dest
|
cmp.b #0xa5:8, @byte_dest
|
beq .Lbabs32
|
beq .Lbabs32
|
fail
|
fail
|
.Lbabs32:
|
.Lbabs32:
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
.endif
|
.endif
|
|
|
#
|
#
|
# 16-bit word operations
|
# 16-bit word operations
|
#
|
#
|
|
|
.if (sim_cpu) ; any except plain-vanilla h8/300
|
.if (sim_cpu) ; any except plain-vanilla h8/300
|
not_w_reg16:
|
not_w_reg16:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
;; fixme set ccr
|
;; fixme set ccr
|
|
|
;; not.w Rd
|
;; not.w Rd
|
not r1 ; 16-bit register operand
|
not r1 ; 16-bit register operand
|
;;; .word 0x1711
|
;;; .word 0x1711
|
|
|
cmp.w #0x5a5a, r1 ; result of "not 0xa5a5"
|
cmp.w #0x5a5a, r1 ; result of "not 0xa5a5"
|
beq .Lwrd
|
beq .Lwrd
|
fail
|
fail
|
.Lwrd:
|
.Lwrd:
|
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
|
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
|
test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not'
|
test_h_gr32 0xa5a55a5a er1 ; er1 changed by 'not'
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.if (sim_cpu == h8sx)
|
.if (sim_cpu == h8sx)
|
not_w_rdind:
|
not_w_rdind:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @eRd
|
;; not.w @eRd
|
mov #word_dest, er1
|
mov #word_dest, er1
|
not.w @er1 ; register indirect operand
|
not.w @er1 ; register indirect operand
|
;;; .word 0x0154
|
;;; .word 0x0154
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.w #0x5a5a, @word_dest ; memory contents changed
|
cmp.w #0x5a5a, @word_dest ; memory contents changed
|
beq .Lwind
|
beq .Lwind
|
fail
|
fail
|
.Lwind:
|
.Lwind:
|
test_h_gr32 word_dest er1 ; er1 still contains address
|
test_h_gr32 word_dest er1 ; er1 still contains address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_rdpostinc:
|
not_w_rdpostinc:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @eRd+
|
;; not.w @eRd+
|
mov #word_dest, er1 ; register post-increment operand
|
mov #word_dest, er1 ; register post-increment operand
|
not.w @er1+
|
not.w @er1+
|
;;; .word 0x0154
|
;;; .word 0x0154
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.w #0xa5a5, @word_dest
|
cmp.w #0xa5a5, @word_dest
|
beq .Lwpostinc
|
beq .Lwpostinc
|
fail
|
fail
|
.Lwpostinc:
|
.Lwpostinc:
|
test_h_gr32 word_dest+2 er1 ; er1 contains address plus two
|
test_h_gr32 word_dest+2 er1 ; er1 contains address plus two
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_rdpostdec:
|
not_w_rdpostdec:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @eRd-
|
;; not.w @eRd-
|
mov #word_dest, er1
|
mov #word_dest, er1
|
not.w @er1-
|
not.w @er1-
|
;;; .word 0x0156
|
;;; .word 0x0156
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.w #0x5a5a, @word_dest
|
cmp.w #0x5a5a, @word_dest
|
beq .Lwpostdec
|
beq .Lwpostdec
|
fail
|
fail
|
.Lwpostdec:
|
.Lwpostdec:
|
test_h_gr32 word_dest-2 er1 ; er1 contains address minus two
|
test_h_gr32 word_dest-2 er1 ; er1 contains address minus two
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_rdpreinc:
|
not_w_rdpreinc:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @+eRd
|
;; not.w @+eRd
|
mov #word_dest-2, er1
|
mov #word_dest-2, er1
|
not.w @+er1 ; reg pre-increment operand
|
not.w @+er1 ; reg pre-increment operand
|
;;; .word 0x0155
|
;;; .word 0x0155
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.w #0xa5a5, @word_dest
|
cmp.w #0xa5a5, @word_dest
|
beq .Lwpreinc
|
beq .Lwpreinc
|
fail
|
fail
|
.Lwpreinc:
|
.Lwpreinc:
|
test_h_gr32 word_dest er1 ; er1 contains destination address
|
test_h_gr32 word_dest er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_rdpredec:
|
not_w_rdpredec:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @-eRd
|
;; not.w @-eRd
|
mov #word_dest+2, er1
|
mov #word_dest+2, er1
|
not.w @-er1 ; reg pre-decr operand
|
not.w @-er1 ; reg pre-decr operand
|
;;; .word 0x0157
|
;;; .word 0x0157
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.w #0x5a5a, @word_dest
|
cmp.w #0x5a5a, @word_dest
|
beq .Lwpredec
|
beq .Lwpredec
|
fail
|
fail
|
.Lwpredec:
|
.Lwpredec:
|
test_h_gr32 word_dest er1 ; er1 contains destination address
|
test_h_gr32 word_dest er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_disp2dst:
|
not_w_disp2dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @(dd:2, erd)
|
;; not.w @(dd:2, erd)
|
mov #word_dest-2, er1
|
mov #word_dest-2, er1
|
not.w @(2:2, er1) ; reg plus 2-bit displacement
|
not.w @(2:2, er1) ; reg plus 2-bit displacement
|
;;; .word 0x0155
|
;;; .word 0x0155
|
;;; .word 0x6918
|
;;; .word 0x6918
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.w #0xa5a5, @word_dest
|
cmp.w #0xa5a5, @word_dest
|
beq .Lwdisp2
|
beq .Lwdisp2
|
fail
|
fail
|
.Lwdisp2:
|
.Lwdisp2:
|
test_h_gr32 word_dest-2 er1 ; er1 contains address minus one
|
test_h_gr32 word_dest-2 er1 ; er1 contains address minus one
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_disp16dst:
|
not_w_disp16dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @(dd:16, erd)
|
;; not.w @(dd:16, erd)
|
mov #word_dest+100, er1
|
mov #word_dest+100, er1
|
not.w @(-100:16, er1) ; reg plus 16-bit displacement
|
not.w @(-100:16, er1) ; reg plus 16-bit displacement
|
;;; .word 0x0154
|
;;; .word 0x0154
|
;;; .word 0x6f18
|
;;; .word 0x6f18
|
;;; .word -100
|
;;; .word -100
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.w #0x5a5a, @word_dest
|
cmp.w #0x5a5a, @word_dest
|
beq .Lwdisp16
|
beq .Lwdisp16
|
fail
|
fail
|
.Lwdisp16:
|
.Lwdisp16:
|
test_h_gr32 word_dest+100 er1 ; er1 contains destination address
|
test_h_gr32 word_dest+100 er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_disp32dst:
|
not_w_disp32dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @(dd:32, erd)
|
;; not.w @(dd:32, erd)
|
mov #word_dest-0xfffff, er1
|
mov #word_dest-0xfffff, er1
|
not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement
|
not.w @(0xfffff:32, er1) ; reg plus 32-bit displacement
|
;;; .word 0x7814
|
;;; .word 0x7814
|
;;; .word 0x6b28
|
;;; .word 0x6b28
|
;;; .long 0xfffff
|
;;; .long 0xfffff
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.w #0xa5a5, @word_dest
|
cmp.w #0xa5a5, @word_dest
|
beq .Lwdisp32
|
beq .Lwdisp32
|
fail
|
fail
|
.Lwdisp32:
|
.Lwdisp32:
|
test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
|
test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_abs16dst:
|
not_w_abs16dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @aa:16
|
;; not.w @aa:16
|
not.w @word_dest:16 ; 16-bit absolute address
|
not.w @word_dest:16 ; 16-bit absolute address
|
;;; .word 0x6b18
|
;;; .word 0x6b18
|
;;; .word word_dest
|
;;; .word word_dest
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.w #0x5a5a, @word_dest
|
cmp.w #0x5a5a, @word_dest
|
beq .Lwabs16
|
beq .Lwabs16
|
fail
|
fail
|
.Lwabs16:
|
.Lwabs16:
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_w_abs32dst:
|
not_w_abs32dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.w @aa:32
|
;; not.w @aa:32
|
not.w @word_dest:32 ; 32-bit absolute address
|
not.w @word_dest:32 ; 32-bit absolute address
|
;;; .word 0x6b38
|
;;; .word 0x6b38
|
;;; .long word_dest
|
;;; .long word_dest
|
;;; .word 0x1710
|
;;; .word 0x1710
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.w #0xa5a5, @word_dest
|
cmp.w #0xa5a5, @word_dest
|
beq .Lwabs32
|
beq .Lwabs32
|
fail
|
fail
|
.Lwabs32:
|
.Lwabs32:
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.endif ; h8sx
|
.endif ; h8sx
|
.endif ; h8/300
|
.endif ; h8/300
|
|
|
#
|
#
|
# 32-bit word operations
|
# 32-bit word operations
|
#
|
#
|
|
|
.if (sim_cpu) ; any except plain-vanilla h8/300
|
.if (sim_cpu) ; any except plain-vanilla h8/300
|
not_l_reg16:
|
not_l_reg16:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
;; fixme set ccr
|
;; fixme set ccr
|
|
|
;; not.l eRd
|
;; not.l eRd
|
not er1 ; 32-bit register operand
|
not er1 ; 32-bit register operand
|
;;; .word 0x1731
|
;;; .word 0x1731
|
|
|
cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5"
|
cmp.l #0x5a5a5a5a, er1 ; result of "not 0xa5a5a5a5"
|
beq .Llrd
|
beq .Llrd
|
fail
|
fail
|
.Llrd:
|
.Llrd:
|
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
|
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
|
test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not'
|
test_h_gr32 0x5a5a5a5a er1 ; er1 changed by 'not'
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.if (sim_cpu == h8sx)
|
.if (sim_cpu == h8sx)
|
not_l_rdind:
|
not_l_rdind:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @eRd
|
;; not.l @eRd
|
mov #long_dest, er1
|
mov #long_dest, er1
|
not.l @er1 ; register indirect operand
|
not.l @er1 ; register indirect operand
|
;;; .word 0x0104
|
;;; .word 0x0104
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed
|
cmp.l #0x5a5a5a5a, @long_dest ; memory contents changed
|
beq .Llind
|
beq .Llind
|
fail
|
fail
|
.Llind:
|
.Llind:
|
test_h_gr32 long_dest er1 ; er1 still contains address
|
test_h_gr32 long_dest er1 ; er1 still contains address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_rdpostinc:
|
not_l_rdpostinc:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @eRd+
|
;; not.l @eRd+
|
mov #long_dest, er1 ; register post-increment operand
|
mov #long_dest, er1 ; register post-increment operand
|
not.l @er1+
|
not.l @er1+
|
;;; .word 0x0104
|
;;; .word 0x0104
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
cmp.l #0xa5a5a5a5, @long_dest
|
beq .Llpostinc
|
beq .Llpostinc
|
fail
|
fail
|
.Llpostinc:
|
.Llpostinc:
|
test_h_gr32 long_dest+4 er1 ; er1 contains address plus two
|
test_h_gr32 long_dest+4 er1 ; er1 contains address plus two
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_rdpostdec:
|
not_l_rdpostdec:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @eRd-
|
;; not.l @eRd-
|
mov #long_dest, er1
|
mov #long_dest, er1
|
not.l @er1-
|
not.l @er1-
|
;;; .word 0x0106
|
;;; .word 0x0106
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.l #0x5a5a5a5a, @long_dest
|
cmp.l #0x5a5a5a5a, @long_dest
|
beq .Llpostdec
|
beq .Llpostdec
|
fail
|
fail
|
.Llpostdec:
|
.Llpostdec:
|
test_h_gr32 long_dest-4 er1 ; er1 contains address minus two
|
test_h_gr32 long_dest-4 er1 ; er1 contains address minus two
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_rdpreinc:
|
not_l_rdpreinc:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @+eRd
|
;; not.l @+eRd
|
mov #long_dest-4, er1
|
mov #long_dest-4, er1
|
not.l @+er1 ; reg pre-increment operand
|
not.l @+er1 ; reg pre-increment operand
|
;;; .word 0x0105
|
;;; .word 0x0105
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
cmp.l #0xa5a5a5a5, @long_dest
|
beq .Llpreinc
|
beq .Llpreinc
|
fail
|
fail
|
.Llpreinc:
|
.Llpreinc:
|
test_h_gr32 long_dest er1 ; er1 contains destination address
|
test_h_gr32 long_dest er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_rdpredec:
|
not_l_rdpredec:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @-eRd
|
;; not.l @-eRd
|
mov #long_dest+4, er1
|
mov #long_dest+4, er1
|
not.l @-er1 ; reg pre-decr operand
|
not.l @-er1 ; reg pre-decr operand
|
;;; .word 0x0107
|
;;; .word 0x0107
|
;;; .word 0x6d18
|
;;; .word 0x6d18
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.l #0x5a5a5a5a, @long_dest
|
cmp.l #0x5a5a5a5a, @long_dest
|
beq .Llpredec
|
beq .Llpredec
|
fail
|
fail
|
.Llpredec:
|
.Llpredec:
|
test_h_gr32 long_dest er1 ; er1 contains destination address
|
test_h_gr32 long_dest er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_disp2dst:
|
not_l_disp2dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @(dd:2, erd)
|
;; not.l @(dd:2, erd)
|
mov #long_dest-4, er1
|
mov #long_dest-4, er1
|
not.l @(4:2, er1) ; reg plus 2-bit displacement
|
not.l @(4:2, er1) ; reg plus 2-bit displacement
|
;;; .word 0x0105
|
;;; .word 0x0105
|
;;; .word 0x6918
|
;;; .word 0x6918
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
cmp.l #0xa5a5a5a5, @long_dest
|
beq .Lldisp2
|
beq .Lldisp2
|
fail
|
fail
|
.Lldisp2:
|
.Lldisp2:
|
test_h_gr32 long_dest-4 er1 ; er1 contains address minus one
|
test_h_gr32 long_dest-4 er1 ; er1 contains address minus one
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_disp16dst:
|
not_l_disp16dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @(dd:16, erd)
|
;; not.l @(dd:16, erd)
|
mov #long_dest+100, er1
|
mov #long_dest+100, er1
|
not.l @(-100:16, er1) ; reg plus 16-bit displacement
|
not.l @(-100:16, er1) ; reg plus 16-bit displacement
|
;;; .word 0x0104
|
;;; .word 0x0104
|
;;; .word 0x6f18
|
;;; .word 0x6f18
|
;;; .word -100
|
;;; .word -100
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.l #0x5a5a5a5a, @long_dest
|
cmp.l #0x5a5a5a5a, @long_dest
|
beq .Lldisp16
|
beq .Lldisp16
|
fail
|
fail
|
.Lldisp16:
|
.Lldisp16:
|
test_h_gr32 long_dest+100 er1 ; er1 contains destination address
|
test_h_gr32 long_dest+100 er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_disp32dst:
|
not_l_disp32dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @(dd:32, erd)
|
;; not.l @(dd:32, erd)
|
mov #long_dest-0xfffff, er1
|
mov #long_dest-0xfffff, er1
|
not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement
|
not.l @(0xfffff:32, er1) ; reg plus 32-bit displacement
|
;;; .word 0x7894
|
;;; .word 0x7894
|
;;; .word 0x6b28
|
;;; .word 0x6b28
|
;;; .long 0xfffff
|
;;; .long 0xfffff
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
cmp.l #0xa5a5a5a5, @long_dest
|
beq .Lldisp32
|
beq .Lldisp32
|
fail
|
fail
|
.Lldisp32:
|
.Lldisp32:
|
test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
|
test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_abs16dst:
|
not_l_abs16dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @aa:16
|
;; not.l @aa:16
|
not.l @long_dest:16 ; 16-bit absolute address
|
not.l @long_dest:16 ; 16-bit absolute address
|
;;; .word 0x0104
|
;;; .word 0x0104
|
;;; .word 0x6b08
|
;;; .word 0x6b08
|
;;; .word long_dest
|
;;; .word long_dest
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_clear
|
test_neg_clear
|
|
|
cmp.l #0x5a5a5a5a, @long_dest
|
cmp.l #0x5a5a5a5a, @long_dest
|
beq .Llabs16
|
beq .Llabs16
|
fail
|
fail
|
.Llabs16:
|
.Llabs16:
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
not_l_abs32dst:
|
not_l_abs32dst:
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
set_ccr_zero
|
set_ccr_zero
|
|
|
;; not.l @aa:32
|
;; not.l @aa:32
|
not.l @long_dest:32 ; 32-bit absolute address
|
not.l @long_dest:32 ; 32-bit absolute address
|
;;; .word 0x0104
|
;;; .word 0x0104
|
;;; .word 0x6b28
|
;;; .word 0x6b28
|
;;; .long long_dest
|
;;; .long long_dest
|
;;; .word 0x1730
|
;;; .word 0x1730
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
test_ovf_clear
|
test_ovf_clear
|
test_zero_clear
|
test_zero_clear
|
test_neg_set
|
test_neg_set
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
cmp.l #0xa5a5a5a5, @long_dest
|
beq .Llabs32
|
beq .Llabs32
|
fail
|
fail
|
.Llabs32:
|
.Llabs32:
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
test_gr_a5a5 1
|
test_gr_a5a5 1
|
test_gr_a5a5 2
|
test_gr_a5a5 2
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
.endif ; h8sx
|
.endif ; h8sx
|
.endif ; h8/300
|
.endif ; h8/300
|
|
|
pass
|
pass
|
|
|
exit 0
|
exit 0
|
|
|
