# Hitachi H8 testcase 'stc'
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# Hitachi H8 testcase 'stc'
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# mach(): all
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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.data
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.data
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byte_dest1:
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byte_dest1:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest2:
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byte_dest2:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest3:
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byte_dest3:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest4:
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byte_dest4:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest5:
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byte_dest5:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest6:
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byte_dest6:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest7:
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byte_dest7:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest8:
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byte_dest8:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest9:
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byte_dest9:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest10:
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byte_dest10:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest11:
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byte_dest11:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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byte_dest12:
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byte_dest12:
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.byte 0
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.byte 0
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.byte 0
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.byte 0
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start
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start
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stc_ccr_reg8:
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stc_ccr_reg8:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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ldc #0xff, ccr ; test value
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ldc #0xff, ccr ; test value
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stc ccr, r0h ; copy test value to r0h
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stc ccr, r0h ; copy test value to r0h
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|
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test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
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test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
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.if (sim_cpu) ; h/s/sx
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.if (sim_cpu) ; h/s/sx
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test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
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test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
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.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
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stc_exr_reg8:
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stc_exr_reg8:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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ldc #0x87, exr ; set exr to 0x87
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ldc #0x87, exr ; set exr to 0x87
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stc exr, r0l ; retrieve and check exr value
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stc exr, r0l ; retrieve and check exr value
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cmp.b #0x87, r0l
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cmp.b #0x87, r0l
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beq .L21
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beq .L21
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fail
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fail
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.L21:
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.L21:
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test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
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test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_ccr_abs16:
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stc_ccr_abs16:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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ldc #0xff, ccr
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ldc #0xff, ccr
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stc ccr, @byte_dest1:16 ; abs16 dest
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stc ccr, @byte_dest1:16 ; abs16 dest
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_exr_abs16:
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stc_exr_abs16:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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ldc #0x87, exr
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ldc #0x87, exr
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stc exr, @byte_dest2:16 ; abs16 dest
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stc exr, @byte_dest2:16 ; abs16 dest
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_ccr_abs32:
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stc_ccr_abs32:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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ldc #0xff, ccr
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ldc #0xff, ccr
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stc ccr, @byte_dest3:32 ; abs32 dest
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stc ccr, @byte_dest3:32 ; abs32 dest
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_exr_abs32:
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stc_exr_abs32:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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ldc #0x87, exr
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ldc #0x87, exr
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stc exr, @byte_dest4:32 ; abs32 dest
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stc exr, @byte_dest4:32 ; abs32 dest
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_ccr_disp16:
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stc_ccr_disp16:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest5-1, er1
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mov #byte_dest5-1, er1
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ldc #0xff, ccr
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ldc #0xff, ccr
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stc ccr, @(1:16,er1) ; disp16 dest (5)
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stc ccr, @(1:16,er1) ; disp16 dest (5)
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test_h_gr32 byte_dest5-1, er1 ; er1 still contains address
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test_h_gr32 byte_dest5-1, er1 ; er1 still contains address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_exr_disp16:
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stc_exr_disp16:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest6+1, er1
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mov #byte_dest6+1, er1
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ldc #0x87, exr
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ldc #0x87, exr
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stc exr, @(-1:16,er1) ; disp16 dest (6)
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stc exr, @(-1:16,er1) ; disp16 dest (6)
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test_h_gr32 byte_dest6+1, er1 ; er1 still contains address
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test_h_gr32 byte_dest6+1, er1 ; er1 still contains address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_ccr_disp32:
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stc_ccr_disp32:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest7-1, er1
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mov #byte_dest7-1, er1
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ldc #0xff, ccr
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ldc #0xff, ccr
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stc ccr, @(1:32,er1) ; disp32 dest (7)
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stc ccr, @(1:32,er1) ; disp32 dest (7)
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test_h_gr32 byte_dest7-1, er1 ; er1 still contains address
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test_h_gr32 byte_dest7-1, er1 ; er1 still contains address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_exr_disp32:
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stc_exr_disp32:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest8+1, er1
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mov #byte_dest8+1, er1
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ldc #0x87, exr
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ldc #0x87, exr
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stc exr, @(-1:32,er1) ; disp16 dest (8)
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stc exr, @(-1:32,er1) ; disp16 dest (8)
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test_h_gr32 byte_dest8+1, er1 ; er1 still contains address
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test_h_gr32 byte_dest8+1, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_ccr_predecr:
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stc_ccr_predecr:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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mov #byte_dest9+2, er1
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mov #byte_dest9+2, er1
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ldc #0xff, ccr
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ldc #0xff, ccr
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stc ccr, @-er1 ; predecr dest (9)
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stc ccr, @-er1 ; predecr dest (9)
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|
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test_h_gr32 byte_dest9 er1 ; er1 still contains address
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test_h_gr32 byte_dest9 er1 ; er1 still contains address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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stc_exr_predecr:
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stc_exr_predecr:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
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|
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mov #byte_dest10+2, er1
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mov #byte_dest10+2, er1
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ldc #0x87, exr
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ldc #0x87, exr
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stc exr, @-er1 ; predecr dest (10)
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stc exr, @-er1 ; predecr dest (10)
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test_h_gr32 byte_dest10, er1 ; er1 still contains address
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test_h_gr32 byte_dest10, er1 ; er1 still contains address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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|
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stc_ccr_ind:
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stc_ccr_ind:
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set_grs_a5a5
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set_grs_a5a5
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set_ccr_zero
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set_ccr_zero
|
|
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mov #byte_dest11, er1
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mov #byte_dest11, er1
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ldc #0xff, ccr
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ldc #0xff, ccr
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stc ccr, @er1 ; postinc dest (11)
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stc ccr, @er1 ; postinc dest (11)
|
|
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test_h_gr32 byte_dest11, er1 ; er1 still contains address
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test_h_gr32 byte_dest11, er1 ; er1 still contains address
|
|
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
|
test_gr_a5a5 3
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test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
|
|
|
stc_exr_ind:
|
stc_exr_ind:
|
set_grs_a5a5
|
set_grs_a5a5
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set_ccr_zero
|
set_ccr_zero
|
|
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mov #byte_dest12, er1
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mov #byte_dest12, er1
|
ldc #0x87, exr
|
ldc #0x87, exr
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stc exr, @er1, exr ; postinc dest (12)
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stc exr, @er1, exr ; postinc dest (12)
|
|
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test_h_gr32 byte_dest12, er1 ; er1 still contains address
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test_h_gr32 byte_dest12, er1 ; er1 still contains address
|
|
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2
|
test_gr_a5a5 2
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test_gr_a5a5 3
|
test_gr_a5a5 3
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test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
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test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
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test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
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.endif
|
.endif
|
|
|
.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
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.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
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stc_sbr_reg:
|
stc_sbr_reg:
|
set_grs_a5a5
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set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov #0xaaaaaaaa, er0
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mov #0xaaaaaaaa, er0
|
ldc er0, sbr ; set sbr to 0xaaaaaaaa
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ldc er0, sbr ; set sbr to 0xaaaaaaaa
|
stc sbr, er1 ; retreive and check sbr value
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stc sbr, er1 ; retreive and check sbr value
|
|
|
test_h_gr32 0xaaaaaaaa er1
|
test_h_gr32 0xaaaaaaaa er1
|
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
|
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
test_gr_a5a5 3
|
test_gr_a5a5 3
|
test_gr_a5a5 4
|
test_gr_a5a5 4
|
test_gr_a5a5 5
|
test_gr_a5a5 5
|
test_gr_a5a5 6
|
test_gr_a5a5 6
|
test_gr_a5a5 7
|
test_gr_a5a5 7
|
|
|
stc_vbr_reg:
|
stc_vbr_reg:
|
set_grs_a5a5
|
set_grs_a5a5
|
set_ccr_zero
|
set_ccr_zero
|
|
|
mov #0xaaaaaaaa, er0
|
mov #0xaaaaaaaa, er0
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ldc er0, vbr ; set sbr to 0xaaaaaaaa
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ldc er0, vbr ; set sbr to 0xaaaaaaaa
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stc vbr, er1 ; retreive and check sbr value
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stc vbr, er1 ; retreive and check sbr value
|
|
|
test_h_gr32 0xaaaaaaaa er1
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test_h_gr32 0xaaaaaaaa er1
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test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
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test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
|
|
|
check_results:
|
check_results:
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;; Now check results
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;; Now check results
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mov @byte_dest1, r0h
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mov @byte_dest1, r0h
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cmp.b #0xff, r0h
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cmp.b #0xff, r0h
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beq .L1
|
beq .L1
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fail
|
fail
|
|
|
.L1: mov @byte_dest2, r0h
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.L1: mov @byte_dest2, r0h
|
cmp.b #0x87, r0h
|
cmp.b #0x87, r0h
|
beq .L2
|
beq .L2
|
fail
|
fail
|
|
|
.L2: mov @byte_dest3, r0h
|
.L2: mov @byte_dest3, r0h
|
cmp.b #0xff, r0h
|
cmp.b #0xff, r0h
|
beq .L3
|
beq .L3
|
fail
|
fail
|
|
|
.L3: mov @byte_dest4, r0h
|
.L3: mov @byte_dest4, r0h
|
cmp.b #0x87, r0h
|
cmp.b #0x87, r0h
|
beq .L4
|
beq .L4
|
fail
|
fail
|
|
|
.L4: mov @byte_dest5, r0h
|
.L4: mov @byte_dest5, r0h
|
cmp.b #0xff, r0h
|
cmp.b #0xff, r0h
|
beq .L5
|
beq .L5
|
fail
|
fail
|
|
|
.L5: mov @byte_dest6, r0h
|
.L5: mov @byte_dest6, r0h
|
cmp.b #0x87, r0h
|
cmp.b #0x87, r0h
|
beq .L6
|
beq .L6
|
fail
|
fail
|
|
|
.L6: mov @byte_dest7, r0h
|
.L6: mov @byte_dest7, r0h
|
cmp.b #0xff, r0h
|
cmp.b #0xff, r0h
|
beq .L7
|
beq .L7
|
fail
|
fail
|
|
|
.L7: mov @byte_dest8, r0h
|
.L7: mov @byte_dest8, r0h
|
cmp.b #0x87, r0h
|
cmp.b #0x87, r0h
|
beq .L8
|
beq .L8
|
fail
|
fail
|
|
|
.L8: mov @byte_dest9, r0h
|
.L8: mov @byte_dest9, r0h
|
cmp.b #0xff, r0h
|
cmp.b #0xff, r0h
|
beq .L9
|
beq .L9
|
fail
|
fail
|
|
|
.L9: mov @byte_dest10, r0h
|
.L9: mov @byte_dest10, r0h
|
cmp.b #0x87, r0h
|
cmp.b #0x87, r0h
|
beq .L10
|
beq .L10
|
fail
|
fail
|
|
|
.L10: mov @byte_dest11, r0h
|
.L10: mov @byte_dest11, r0h
|
cmp.b #0xff, r0h
|
cmp.b #0xff, r0h
|
beq .L11
|
beq .L11
|
fail
|
fail
|
|
|
.L11: mov @byte_dest12, r0h
|
.L11: mov @byte_dest12, r0h
|
cmp.b #0x87, r0h
|
cmp.b #0x87, r0h
|
beq .L12
|
beq .L12
|
fail
|
fail
|
|
|
.L12:
|
.L12:
|
.endif
|
.endif
|
pass
|
pass
|
|
|
exit 0
|
exit 0
|
|
|
