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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 157 |
Rev 223 |
# sh testcase for bclr
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# sh testcase for bclr
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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.align 2
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.align 2
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_x: .long 0xffffffff
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_x: .long 0xffffffff
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_y: .long 0x55555555
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_y: .long 0x55555555
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start
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start
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bclr_b_imm_disp12_reg:
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bclr_b_imm_disp12_reg:
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set_grs_a5a5
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set_grs_a5a5
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mov.l x, r1
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mov.l x, r1
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bclr.b #0, @(3, r1)
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bclr.b #0, @(3, r1)
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assertmem _x, 0xfffffffe
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assertmem _x, 0xfffffffe
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bclr.b #1, @(3, r1)
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bclr.b #1, @(3, r1)
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assertmem _x, 0xfffffffc
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assertmem _x, 0xfffffffc
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bclr.b #2, @(3, r1)
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bclr.b #2, @(3, r1)
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assertmem _x, 0xfffffff8
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assertmem _x, 0xfffffff8
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bclr.b #3, @(3, r1)
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bclr.b #3, @(3, r1)
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assertmem _x, 0xfffffff0
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assertmem _x, 0xfffffff0
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bclr.b #4, @(3, r1)
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bclr.b #4, @(3, r1)
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assertmem _x, 0xffffffe0
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assertmem _x, 0xffffffe0
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bclr.b #5, @(3, r1)
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bclr.b #5, @(3, r1)
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assertmem _x, 0xffffffc0
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assertmem _x, 0xffffffc0
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bclr.b #6, @(3, r1)
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bclr.b #6, @(3, r1)
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assertmem _x, 0xffffff80
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assertmem _x, 0xffffff80
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bclr.b #7, @(3, r1)
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bclr.b #7, @(3, r1)
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assertmem _x, 0xffffff00
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assertmem _x, 0xffffff00
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bclr.b #0, @(2, r1)
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bclr.b #0, @(2, r1)
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assertmem _x, 0xfffffe00
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assertmem _x, 0xfffffe00
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bclr.b #1, @(2, r1)
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bclr.b #1, @(2, r1)
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assertmem _x, 0xfffffc00
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assertmem _x, 0xfffffc00
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bclr.b #2, @(2, r1)
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bclr.b #2, @(2, r1)
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assertmem _x, 0xfffff800
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assertmem _x, 0xfffff800
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bclr.b #3, @(2, r1)
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bclr.b #3, @(2, r1)
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assertmem _x, 0xfffff000
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assertmem _x, 0xfffff000
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bra .L2
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bra .L2
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nop
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nop
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.align 2
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.align 2
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x: .long _x
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x: .long _x
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y: .long _y
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y: .long _y
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.L2:
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.L2:
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bclr.b #4, @(2, r1)
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bclr.b #4, @(2, r1)
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assertmem _x, 0xffffe000
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assertmem _x, 0xffffe000
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bclr.b #5, @(2, r1)
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bclr.b #5, @(2, r1)
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assertmem _x, 0xffffc000
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assertmem _x, 0xffffc000
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bclr.b #6, @(2, r1)
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bclr.b #6, @(2, r1)
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assertmem _x, 0xffff8000
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assertmem _x, 0xffff8000
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bclr.b #7, @(2, r1)
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bclr.b #7, @(2, r1)
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assertmem _x, 0xffff0000
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assertmem _x, 0xffff0000
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bclr.b #0, @(1, r1)
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bclr.b #0, @(1, r1)
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assertmem _x, 0xfffe0000
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assertmem _x, 0xfffe0000
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bclr.b #1, @(1, r1)
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bclr.b #1, @(1, r1)
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assertmem _x, 0xfffc0000
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assertmem _x, 0xfffc0000
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bclr.b #2, @(1, r1)
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bclr.b #2, @(1, r1)
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assertmem _x, 0xfff80000
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assertmem _x, 0xfff80000
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bclr.b #3, @(1, r1)
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bclr.b #3, @(1, r1)
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assertmem _x, 0xfff00000
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assertmem _x, 0xfff00000
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bclr.b #4, @(1, r1)
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bclr.b #4, @(1, r1)
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assertmem _x, 0xffe00000
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assertmem _x, 0xffe00000
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bclr.b #5, @(1, r1)
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bclr.b #5, @(1, r1)
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assertmem _x, 0xffc00000
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assertmem _x, 0xffc00000
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bclr.b #6, @(1, r1)
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bclr.b #6, @(1, r1)
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assertmem _x, 0xff800000
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assertmem _x, 0xff800000
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bclr.b #7, @(1, r1)
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bclr.b #7, @(1, r1)
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assertmem _x, 0xff000000
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assertmem _x, 0xff000000
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bclr.b #0, @(0, r1)
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bclr.b #0, @(0, r1)
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assertmem _x, 0xfe000000
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assertmem _x, 0xfe000000
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bclr.b #1, @(0, r1)
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bclr.b #1, @(0, r1)
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assertmem _x, 0xfc000000
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assertmem _x, 0xfc000000
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bclr.b #2, @(0, r1)
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bclr.b #2, @(0, r1)
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assertmem _x, 0xf8000000
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assertmem _x, 0xf8000000
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bclr.b #3, @(0, r1)
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bclr.b #3, @(0, r1)
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assertmem _x, 0xf0000000
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assertmem _x, 0xf0000000
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bclr.b #4, @(0, r1)
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bclr.b #4, @(0, r1)
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assertmem _x, 0xe0000000
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assertmem _x, 0xe0000000
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bclr.b #5, @(0, r1)
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bclr.b #5, @(0, r1)
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assertmem _x, 0xc0000000
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assertmem _x, 0xc0000000
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bclr.b #6, @(0, r1)
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bclr.b #6, @(0, r1)
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assertmem _x, 0x80000000
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assertmem _x, 0x80000000
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bclr.b #7, @(0, r1)
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bclr.b #7, @(0, r1)
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assertmem _x, 0x00000000
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assertmem _x, 0x00000000
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assertreg _x, r1
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assertreg _x, r1
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bclr_imm_reg:
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bclr_imm_reg:
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set_greg 0xff, r1
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set_greg 0xff, r1
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bclr #0, r1
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bclr #0, r1
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assertreg 0xfe, r1
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assertreg 0xfe, r1
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bclr #1, r1
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bclr #1, r1
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assertreg 0xfc, r1
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assertreg 0xfc, r1
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bclr #2, r1
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bclr #2, r1
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assertreg 0xf8, r1
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assertreg 0xf8, r1
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bclr #3, r1
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bclr #3, r1
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assertreg 0xf0, r1
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assertreg 0xf0, r1
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bclr #4, r1
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bclr #4, r1
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assertreg 0xe0, r1
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assertreg 0xe0, r1
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bclr #5, r1
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bclr #5, r1
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assertreg 0xc0, r1
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assertreg 0xc0, r1
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bclr #6, r1
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bclr #6, r1
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assertreg 0x80, r1
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assertreg 0x80, r1
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bclr #7, r1
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bclr #7, r1
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assertreg 0x00, r1
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assertreg 0x00, r1
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test_gr_a5a5 r0
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test_gr_a5a5 r0
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test_gr_a5a5 r2
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test_gr_a5a5 r2
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test_gr_a5a5 r3
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test_gr_a5a5 r3
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test_gr_a5a5 r4
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test_gr_a5a5 r4
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test_gr_a5a5 r5
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test_gr_a5a5 r5
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test_gr_a5a5 r6
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test_gr_a5a5 r6
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test_gr_a5a5 r7
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test_gr_a5a5 r7
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test_gr_a5a5 r8
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test_gr_a5a5 r8
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test_gr_a5a5 r9
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test_gr_a5a5 r9
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test_gr_a5a5 r10
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test_gr_a5a5 r10
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test_gr_a5a5 r11
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test_gr_a5a5 r11
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test_gr_a5a5 r12
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test_gr_a5a5 r12
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test_gr_a5a5 r13
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test_gr_a5a5 r13
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test_gr_a5a5 r14
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test_gr_a5a5 r14
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pass
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pass
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exit 0
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exit 0
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