# sh testcase for pshl <reg>
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# sh testcase for pshl <reg>
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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pshl_reg: ! shift arithmetic, register operand
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pshl_reg: ! shift arithmetic, register operand
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set_grs_a5a5
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set_grs_a5a5
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lds r0, a0
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lds r0, a0
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pcopy a0, a1
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pcopy a0, a1
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lds r0, x0
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lds r0, x0
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lds r0, x1
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lds r0, x1
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lds r0, y0
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lds r0, y0
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lds r0, y1
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lds r0, y1
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pcopy x0, m0
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pcopy x0, m0
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pcopy y1, m1
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pcopy y1, m1
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set_sreg 0x10000, x0
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set_sreg 0x10000, x0
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set_sreg 0x0, y0
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set_sreg 0x0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x10000, y0
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set_sreg 0x10000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x20000, x0
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assert_sreg 0x20000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x20000, y0
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set_sreg 0x20000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x40000, x0
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assert_sreg 0x40000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x30000, y0
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set_sreg 0x30000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x80000, x0
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assert_sreg 0x80000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x40000, y0
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set_sreg 0x40000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x100000, x0
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assert_sreg 0x100000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x50000, y0
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set_sreg 0x50000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x200000, x0
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assert_sreg 0x200000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x60000, y0
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set_sreg 0x60000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x400000, x0
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assert_sreg 0x400000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x70000, y0
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set_sreg 0x70000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x800000, x0
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assert_sreg 0x800000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x80000, y0
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set_sreg 0x80000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x1000000, x0
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assert_sreg 0x1000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x90000, y0
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set_sreg 0x90000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x2000000, x0
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assert_sreg 0x2000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0xa0000, y0
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set_sreg 0xa0000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x4000000, x0
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assert_sreg 0x4000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0xb0000, y0
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set_sreg 0xb0000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x8000000, x0
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assert_sreg 0x8000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0xc0000, y0
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set_sreg 0xc0000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000000, x0
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assert_sreg 0x10000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0xd0000, y0
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set_sreg 0xd0000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x20000000, x0
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assert_sreg 0x20000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0xe0000, y0
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set_sreg 0xe0000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x40000000, x0
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assert_sreg 0x40000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0xf0000, y0
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set_sreg 0xf0000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x80000000, x0
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assert_sreg 0x80000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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set_sreg 0x100000, y0
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set_sreg 0x100000, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x00000000, x0
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assert_sreg 0x00000000, x0
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pneg y0, y0
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pneg y0, y0
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pshl x0, y0, x0
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pshl x0, y0, x0
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assert_sreg 0x0, x0
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assert_sreg 0x0, x0
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test_grs_a5a5
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test_grs_a5a5
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assert_sreg2 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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assert_sreg2 0xa5a5a5a5, m1
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pass
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pass
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exit 0
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exit 0
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