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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 223 |
# sh testcase for psub
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# sh testcase for psub
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# mach: shdsp
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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set_grs_a5a5
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set_grs_a5a5
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lds r0, a0
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lds r0, a0
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pcopy a0, a1
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pcopy a0, a1
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lds r0, x0
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lds r0, x0
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lds r0, x1
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lds r0, x1
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lds r0, y0
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lds r0, y0
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lds r0, y1
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lds r0, y1
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pcopy x0, m0
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pcopy x0, m0
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pcopy y1, m1
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pcopy y1, m1
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psub_sx_sy:
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psub_sx_sy:
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# 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero
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# 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero
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psub x0, y0, a0
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psub x0, y0, a0
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assert_sreg 0, a0
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assert_sreg 0, a0
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psub_sy_sx:
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psub_sy_sx:
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# 100 - 25 = 75
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# 100 - 25 = 75
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mov #100, r0
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mov #100, r0
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mov #25, r1
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mov #25, r1
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lds r0, y1
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lds r0, y1
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lds r1, x1
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lds r1, x1
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psub y1, x1, a0
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psub y1, x1, a0
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assert_sreg 75, a0
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assert_sreg 75, a0
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dct_psub:
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dct_psub:
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# 100 - 25 = 75
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# 100 - 25 = 75
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set_dcfalse
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set_dcfalse
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dct psub y1, x1, a1
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dct psub y1, x1, a1
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, a1
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set_dctrue
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set_dctrue
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dct psub y1, x1, a1
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dct psub y1, x1, a1
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assert_sreg2 75, a1
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assert_sreg2 75, a1
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dcf_psub:
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dcf_psub:
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# 25 - 100 = -75
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# 25 - 100 = -75
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set_dctrue
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set_dctrue
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dcf psub x1, y1, m1
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dcf psub x1, y1, m1
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assert_sreg2 0xa5a5a5a5, m1
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assert_sreg2 0xa5a5a5a5, m1
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set_dcfalse
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set_dcfalse
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dcf psub x1, y1, m1
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dcf psub x1, y1, m1
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assert_sreg2 -75, m1
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assert_sreg2 -75, m1
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psub_pmuls:
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psub_pmuls:
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# 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four)
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# 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four)
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mov #2, r0
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mov #2, r0
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shll16 r0
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shll16 r0
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lds r0, x0
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lds r0, x0
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lds r0, y0
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lds r0, y0
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psub x1, y1, a1 pmuls x0, y0, a0
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psub x1, y1, a1 pmuls x0, y0, a0
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assert_sreg 8, a0
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assert_sreg 8, a0
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assert_sreg2 -75, a1
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assert_sreg2 -75, a1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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test_grs_a5a5
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pass
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pass
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exit 0
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exit 0
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