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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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# sh testcase for mov.l $rm, @-$rn -*- Asm -*-
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# sh testcase for mov.l $rm, @-$rn -*- Asm -*-
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# mach: all
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# mach: all
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# as: -isa=shcompact
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# as: -isa=shcompact
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# ld: -m shelf32
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# ld: -m shelf32
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.include "compact/testutils.inc"
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.include "compact/testutils.inc"
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start
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start
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mov #30, r1
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mov #30, r1
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shll8 r1
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shll8 r1
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# Save address.
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# Save address.
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mov r1, r7
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mov r1, r7
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init:
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init:
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# Build up a distinctive bit pattern.
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# Build up a distinctive bit pattern.
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mov #1, r2
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mov #1, r2
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shll8 r2
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shll8 r2
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add #12, r2
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add #12, r2
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shll8 r2
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shll8 r2
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add #85, r2
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add #85, r2
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shll8 r2
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shll8 r2
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add #170, r2
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add #170, r2
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mov.l r2, @-r1
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mov.l r2, @-r1
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check:
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check:
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# Compare the value loaded into another reg.
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# Compare the value loaded into another reg.
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mov.l @r1, r3
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mov.l @r1, r3
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cmp/eq r2, r3
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cmp/eq r2, r3
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bf wrong
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bf wrong
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dec:
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dec:
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# Ensure address is decremented.
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# Ensure address is decremented.
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mov #4, r6
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mov #4, r6
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sub r6, r7
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sub r6, r7
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cmp/eq r1, r7
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cmp/eq r1, r7
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bf wrong
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bf wrong
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okay:
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okay:
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pass
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pass
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wrong:
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wrong:
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fail
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fail
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