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| Rev 24 |
Rev 157 |
# v850 sar
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# v850 sar
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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# CY is set to 1 if the bit shifted out last is 1, else 0
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# CY is set to 1 if the bit shifted out last is 1, else 0
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# OV is set to zero.
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# OV is set to zero.
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# Z is set if the result is 0, else 0
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# Z is set if the result is 0, else 0
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noflags
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noflags
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seti 4, r1
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seti 4, r1
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seti 0x00000000, r2
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seti 0x00000000, r2
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sar r1, r2
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sar r1, r2
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flags z
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flags z
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reg r2, 0
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reg r2, 0
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noflags
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noflags
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seti 4, r1
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seti 4, r1
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seti 0x00000001, r2
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seti 0x00000001, r2
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sar r1, r2
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sar r1, r2
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flags z
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flags z
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reg r2, 0
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reg r2, 0
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noflags
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noflags
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seti 4, r1
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seti 4, r1
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seti 0x00000008, r2
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seti 0x00000008, r2
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sar r1, r2
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sar r1, r2
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flags c + z
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flags c + z
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reg r2, 0
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reg r2, 0
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noflags
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noflags
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seti 0x00000000, r2
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seti 0x00000000, r2
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sar 4, r2
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sar 4, r2
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flags z
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flags z
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reg r2, 0
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reg r2, 0
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noflags
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noflags
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seti 0x00000001, r2
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seti 0x00000001, r2
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sar 4, r2
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sar 4, r2
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flags z
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flags z
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reg r2, 0
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reg r2, 0
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noflags
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noflags
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seti 0x00000008, r2
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seti 0x00000008, r2
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sar 4, r2
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sar 4, r2
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flags c + z
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flags c + z
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reg r2, 0
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reg r2, 0
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# However, if the number of shifts is 0, CY is 0.
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# However, if the number of shifts is 0, CY is 0.
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noflags
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noflags
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seti 0, r1
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seti 0, r1
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seti 0xffffffff, r2
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seti 0xffffffff, r2
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sar r1, r2
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sar r1, r2
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flags s
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flags s
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reg r2, 0xffffffff
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reg r2, 0xffffffff
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noflags
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noflags
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seti 0xffffffff, r2
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seti 0xffffffff, r2
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sar 0, r2
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sar 0, r2
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flags s
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flags s
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reg r2, 0xffffffff
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reg r2, 0xffffffff
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# Old MSB is copied as new MSB after shift
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# Old MSB is copied as new MSB after shift
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# S is 1 if the result is negative, else 0
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# S is 1 if the result is negative, else 0
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noflags
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noflags
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seti 1, r1
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seti 1, r1
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seti 0x80000000, r2
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seti 0x80000000, r2
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sar r1, r2
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sar r1, r2
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flags s
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flags s
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reg r2, 0xc0000000
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reg r2, 0xc0000000
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noflags
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noflags
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seti 1, r1
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seti 1, r1
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seti 0x40000000, r2
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seti 0x40000000, r2
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sar r1, r2
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sar r1, r2
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flags 0
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flags 0
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reg r2, 0x20000000
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reg r2, 0x20000000
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pass
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pass
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